2 * RocketPort device driver for Linux
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Kernel Synchronization:
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
42 /****** Defines ******/
43 #define ROCKET_PARANOIA_CHECK
44 #define ROCKET_DISABLE_SIMUSAGE
46 #undef ROCKET_SOFT_FLOW
47 #undef ROCKET_DEBUG_OPEN
48 #undef ROCKET_DEBUG_INTR
49 #undef ROCKET_DEBUG_WRITE
50 #undef ROCKET_DEBUG_FLOW
51 #undef ROCKET_DEBUG_THROTTLE
52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
53 #undef ROCKET_DEBUG_RECEIVE
54 #undef ROCKET_DEBUG_HANGUP
56 #undef ROCKET_DEBUG_IO
58 #define POLL_PERIOD (HZ/100) /* Polling period .01 seconds (10ms) */
60 /****** Kernel includes ******/
62 #include <linux/module.h>
63 #include <linux/errno.h>
64 #include <linux/major.h>
65 #include <linux/kernel.h>
66 #include <linux/signal.h>
67 #include <linux/slab.h>
69 #include <linux/sched.h>
70 #include <linux/timer.h>
71 #include <linux/interrupt.h>
72 #include <linux/tty.h>
73 #include <linux/tty_driver.h>
74 #include <linux/tty_flip.h>
75 #include <linux/serial.h>
76 #include <linux/string.h>
77 #include <linux/fcntl.h>
78 #include <linux/ptrace.h>
79 #include <linux/mutex.h>
80 #include <linux/ioport.h>
81 #include <linux/delay.h>
82 #include <linux/completion.h>
83 #include <linux/wait.h>
84 #include <linux/pci.h>
85 #include <linux/uaccess.h>
86 #include <linux/atomic.h>
87 #include <asm/unaligned.h>
88 #include <linux/bitops.h>
89 #include <linux/spinlock.h>
90 #include <linux/init.h>
92 /****** RocketPort includes ******/
94 #include "rocket_int.h"
97 #define ROCKET_VERSION "2.09"
98 #define ROCKET_DATE "12-June-2003"
100 /****** RocketPort Local Variables ******/
102 static void rp_do_poll(unsigned long dummy);
104 static struct tty_driver *rocket_driver;
106 static struct rocket_version driver_version = {
107 ROCKET_VERSION, ROCKET_DATE
110 static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
111 static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
112 /* eg. Bit 0 indicates port 0 has xmit data, ... */
113 static atomic_t rp_num_ports_open; /* Number of serial ports open */
114 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
116 static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
117 static unsigned long board2;
118 static unsigned long board3;
119 static unsigned long board4;
120 static unsigned long controller;
121 static bool support_low_speed;
122 static unsigned long modem1;
123 static unsigned long modem2;
124 static unsigned long modem3;
125 static unsigned long modem4;
126 static unsigned long pc104_1[8];
127 static unsigned long pc104_2[8];
128 static unsigned long pc104_3[8];
129 static unsigned long pc104_4[8];
130 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
132 static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
133 static unsigned long rcktpt_io_addr[NUM_BOARDS];
134 static int rcktpt_type[NUM_BOARDS];
135 static int is_PCI[NUM_BOARDS];
136 static rocketModel_t rocketModel[NUM_BOARDS];
137 static int max_board;
138 static const struct tty_port_operations rocket_port_ops;
141 * The following arrays define the interrupt bits corresponding to each AIOP.
142 * These bits are different between the ISA and regular PCI boards and the
143 * Universal PCI boards.
146 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
153 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
154 UPCI_AIOP_INTR_BIT_0,
155 UPCI_AIOP_INTR_BIT_1,
156 UPCI_AIOP_INTR_BIT_2,
160 static Byte_t RData[RDATASIZE] = {
161 0x00, 0x09, 0xf6, 0x82,
162 0x02, 0x09, 0x86, 0xfb,
163 0x04, 0x09, 0x00, 0x0a,
164 0x06, 0x09, 0x01, 0x0a,
165 0x08, 0x09, 0x8a, 0x13,
166 0x0a, 0x09, 0xc5, 0x11,
167 0x0c, 0x09, 0x86, 0x85,
168 0x0e, 0x09, 0x20, 0x0a,
169 0x10, 0x09, 0x21, 0x0a,
170 0x12, 0x09, 0x41, 0xff,
171 0x14, 0x09, 0x82, 0x00,
172 0x16, 0x09, 0x82, 0x7b,
173 0x18, 0x09, 0x8a, 0x7d,
174 0x1a, 0x09, 0x88, 0x81,
175 0x1c, 0x09, 0x86, 0x7a,
176 0x1e, 0x09, 0x84, 0x81,
177 0x20, 0x09, 0x82, 0x7c,
178 0x22, 0x09, 0x0a, 0x0a
181 static Byte_t RRegData[RREGDATASIZE] = {
182 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
183 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
184 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
185 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
186 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
187 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
188 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
189 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
190 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
191 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
192 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
193 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
194 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
197 static CONTROLLER_T sController[CTL_SIZE] = {
198 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
199 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
200 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
201 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
202 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
203 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
204 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
205 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
208 static Byte_t sBitMapClrTbl[8] = {
209 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
212 static Byte_t sBitMapSetTbl[8] = {
213 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
216 static int sClockPrescale = 0x14;
219 * Line number is the ttySIx number (x), the Minor number. We
220 * assign them sequentially, starting at zero. The following
221 * array keeps track of the line number assigned to a given board/aiop/channel.
223 static unsigned char lineNumbers[MAX_RP_PORTS];
224 static unsigned long nextLineNumber;
226 /***** RocketPort Static Prototypes *********/
227 static int __init init_ISA(int i);
228 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
229 static void rp_flush_buffer(struct tty_struct *tty);
230 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
231 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
232 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
233 static void rp_start(struct tty_struct *tty);
234 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
236 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
237 static void sFlushRxFIFO(CHANNEL_T * ChP);
238 static void sFlushTxFIFO(CHANNEL_T * ChP);
239 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
240 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
241 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
242 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
243 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
244 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
245 ByteIO_t * AiopIOList, int AiopIOListSize,
246 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
247 int PeriodicOnly, int altChanRingIndicator,
249 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
250 ByteIO_t * AiopIOList, int AiopIOListSize,
251 int IRQNum, Byte_t Frequency, int PeriodicOnly);
252 static int sReadAiopID(ByteIO_t io);
253 static int sReadAiopNumChan(WordIO_t io);
255 MODULE_AUTHOR("Theodore Ts'o");
256 MODULE_DESCRIPTION("Comtrol RocketPort driver");
257 module_param(board1, ulong, 0);
258 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
259 module_param(board2, ulong, 0);
260 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
261 module_param(board3, ulong, 0);
262 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
263 module_param(board4, ulong, 0);
264 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
265 module_param(controller, ulong, 0);
266 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
267 module_param(support_low_speed, bool, 0);
268 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
269 module_param(modem1, ulong, 0);
270 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
271 module_param(modem2, ulong, 0);
272 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
273 module_param(modem3, ulong, 0);
274 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
275 module_param(modem4, ulong, 0);
276 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
277 module_param_array(pc104_1, ulong, NULL, 0);
278 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
279 module_param_array(pc104_2, ulong, NULL, 0);
280 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
281 module_param_array(pc104_3, ulong, NULL, 0);
282 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
283 module_param_array(pc104_4, ulong, NULL, 0);
284 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
286 static int rp_init(void);
287 static void rp_cleanup_module(void);
289 module_init(rp_init);
290 module_exit(rp_cleanup_module);
293 MODULE_LICENSE("Dual BSD/GPL");
295 /*************************************************************************/
296 /* Module code starts here */
298 static inline int rocket_paranoia_check(struct r_port *info,
301 #ifdef ROCKET_PARANOIA_CHECK
304 if (info->magic != RPORT_MAGIC) {
305 printk(KERN_WARNING "Warning: bad magic number for rocketport "
306 "struct in %s\n", routine);
314 /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
315 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
318 static void rp_do_receive(struct r_port *info, CHANNEL_t *cp,
319 unsigned int ChanStatus)
321 unsigned int CharNStat;
322 int ToRecv, wRecv, space;
325 ToRecv = sGetRxCnt(cp);
326 #ifdef ROCKET_DEBUG_INTR
327 printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
333 * if status indicates there are errored characters in the
334 * FIFO, then enter status mode (a word in FIFO holds
335 * character and status).
337 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
338 if (!(ChanStatus & STATMODE)) {
339 #ifdef ROCKET_DEBUG_RECEIVE
340 printk(KERN_INFO "Entering STATMODE...\n");
342 ChanStatus |= STATMODE;
348 * if we previously entered status mode, then read down the
349 * FIFO one word at a time, pulling apart the character and
350 * the status. Update error counters depending on status
352 if (ChanStatus & STATMODE) {
353 #ifdef ROCKET_DEBUG_RECEIVE
354 printk(KERN_INFO "Ignore %x, read %x...\n",
355 info->ignore_status_mask, info->read_status_mask);
360 CharNStat = sInW(sGetTxRxDataIO(cp));
361 #ifdef ROCKET_DEBUG_RECEIVE
362 printk(KERN_INFO "%x...\n", CharNStat);
364 if (CharNStat & STMBREAKH)
365 CharNStat &= ~(STMFRAMEH | STMPARITYH);
366 if (CharNStat & info->ignore_status_mask) {
370 CharNStat &= info->read_status_mask;
371 if (CharNStat & STMBREAKH)
373 else if (CharNStat & STMPARITYH)
375 else if (CharNStat & STMFRAMEH)
377 else if (CharNStat & STMRCVROVRH)
381 tty_insert_flip_char(&info->port, CharNStat & 0xff,
387 * after we've emptied the FIFO in status mode, turn
388 * status mode back off
390 if (sGetRxCnt(cp) == 0) {
391 #ifdef ROCKET_DEBUG_RECEIVE
392 printk(KERN_INFO "Status mode off.\n");
394 sDisRxStatusMode(cp);
398 * we aren't in status mode, so read down the FIFO two
399 * characters at time by doing repeated word IO
402 space = tty_prepare_flip_string(&info->port, &cbuf, ToRecv);
403 if (space < ToRecv) {
404 #ifdef ROCKET_DEBUG_RECEIVE
405 printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
413 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
415 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
417 /* Push the data up to the tty layer */
418 tty_flip_buffer_push(&info->port);
422 * Serial port transmit data function. Called from the timer polling loop as a
423 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
424 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
425 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
427 static void rp_do_transmit(struct r_port *info)
430 CHANNEL_t *cp = &info->channel;
431 struct tty_struct *tty;
434 #ifdef ROCKET_DEBUG_INTR
435 printk(KERN_DEBUG "%s\n", __func__);
439 tty = tty_port_tty_get(&info->port);
442 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
443 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
447 spin_lock_irqsave(&info->slock, flags);
448 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
450 /* Loop sending data to FIFO until done or FIFO full */
452 if (tty->stopped || tty->hw_stopped)
454 c = min(info->xmit_fifo_room, info->xmit_cnt);
455 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
456 if (c <= 0 || info->xmit_fifo_room <= 0)
458 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
460 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
461 info->xmit_tail += c;
462 info->xmit_tail &= XMIT_BUF_SIZE - 1;
464 info->xmit_fifo_room -= c;
465 #ifdef ROCKET_DEBUG_INTR
466 printk(KERN_INFO "tx %d chars...\n", c);
470 if (info->xmit_cnt == 0)
471 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
473 if (info->xmit_cnt < WAKEUP_CHARS) {
475 #ifdef ROCKETPORT_HAVE_POLL_WAIT
476 wake_up_interruptible(&tty->poll_wait);
480 spin_unlock_irqrestore(&info->slock, flags);
483 #ifdef ROCKET_DEBUG_INTR
484 printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
485 info->xmit_tail, info->xmit_fifo_room);
490 * Called when a serial port signals it has read data in it's RX FIFO.
491 * It checks what interrupts are pending and services them, including
492 * receiving serial data.
494 static void rp_handle_port(struct r_port *info)
497 unsigned int IntMask, ChanStatus;
502 if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
503 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
504 "info->flags & NOT_INIT\n");
510 IntMask = sGetChanIntID(cp) & info->intmask;
511 #ifdef ROCKET_DEBUG_INTR
512 printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
514 ChanStatus = sGetChanStatus(cp);
515 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
516 rp_do_receive(info, cp, ChanStatus);
518 if (IntMask & DELTA_CD) { /* CD change */
519 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
520 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
521 (ChanStatus & CD_ACT) ? "on" : "off");
523 if (!(ChanStatus & CD_ACT) && info->cd_status) {
524 struct tty_struct *tty;
525 #ifdef ROCKET_DEBUG_HANGUP
526 printk(KERN_INFO "CD drop, calling hangup.\n");
528 tty = tty_port_tty_get(&info->port);
534 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
535 wake_up_interruptible(&info->port.open_wait);
537 #ifdef ROCKET_DEBUG_INTR
538 if (IntMask & DELTA_CTS) { /* CTS change */
539 printk(KERN_INFO "CTS change...\n");
541 if (IntMask & DELTA_DSR) { /* DSR change */
542 printk(KERN_INFO "DSR change...\n");
548 * The top level polling routine. Repeats every 1/100 HZ (10ms).
550 static void rp_do_poll(unsigned long dummy)
553 int ctrl, aiop, ch, line;
554 unsigned int xmitmask, i;
555 unsigned int CtlMask;
556 unsigned char AiopMask;
559 /* Walk through all the boards (ctrl's) */
560 for (ctrl = 0; ctrl < max_board; ctrl++) {
561 if (rcktpt_io_addr[ctrl] <= 0)
564 /* Get a ptr to the board's control struct */
565 ctlp = sCtlNumToCtlPtr(ctrl);
567 /* Get the interrupt status from the board */
569 if (ctlp->BusType == isPCI)
570 CtlMask = sPCIGetControllerIntStatus(ctlp);
573 CtlMask = sGetControllerIntStatus(ctlp);
575 /* Check if any AIOP read bits are set */
576 for (aiop = 0; CtlMask; aiop++) {
577 bit = ctlp->AiopIntrBits[aiop];
580 AiopMask = sGetAiopIntStatus(ctlp, aiop);
582 /* Check if any port read bits are set */
583 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
586 /* Get the line number (/dev/ttyRx number). */
587 /* Read the data from the port. */
588 line = GetLineNumber(ctrl, aiop, ch);
589 rp_handle_port(rp_table[line]);
595 xmitmask = xmit_flags[ctrl];
598 * xmit_flags contains bit-significant flags, indicating there is data
599 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
600 * 1, ... (32 total possible). The variable i has the aiop and ch
601 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
604 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
605 if (xmitmask & (1 << i)) {
606 aiop = (i & 0x18) >> 3;
608 line = GetLineNumber(ctrl, aiop, ch);
609 rp_do_transmit(rp_table[line]);
616 * Reset the timer so we get called at the next clock tick (10ms).
618 if (atomic_read(&rp_num_ports_open))
619 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
623 * Initializes the r_port structure for a port, as well as enabling the port on
625 * Inputs: board, aiop, chan numbers
627 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
634 /* Get the next available line number */
635 line = SetLineNumber(board, aiop, chan);
637 ctlp = sCtlNumToCtlPtr(board);
639 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
640 info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
642 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
647 info->magic = RPORT_MAGIC;
653 tty_port_init(&info->port);
654 info->port.ops = &rocket_port_ops;
655 init_completion(&info->close_wait);
656 info->flags &= ~ROCKET_MODE_MASK;
657 switch (pc104[board][line]) {
659 info->flags |= ROCKET_MODE_RS422;
662 info->flags |= ROCKET_MODE_RS485;
666 info->flags |= ROCKET_MODE_RS232;
670 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
671 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
672 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
674 tty_port_destroy(&info->port);
679 rocketMode = info->flags & ROCKET_MODE_MASK;
681 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
682 sEnRTSToggle(&info->channel);
684 sDisRTSToggle(&info->channel);
686 if (ctlp->boardType == ROCKET_TYPE_PC104) {
687 switch (rocketMode) {
688 case ROCKET_MODE_RS485:
689 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
691 case ROCKET_MODE_RS422:
692 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
694 case ROCKET_MODE_RS232:
696 if (info->flags & ROCKET_RTS_TOGGLE)
697 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
699 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
703 spin_lock_init(&info->slock);
704 mutex_init(&info->write_mtx);
705 rp_table[line] = info;
706 tty_port_register_device(&info->port, rocket_driver, line,
707 pci_dev ? &pci_dev->dev : NULL);
711 * Configures a rocketport port according to its termio settings. Called from
712 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
714 static void configure_r_port(struct tty_struct *tty, struct r_port *info,
715 struct ktermios *old_termios)
720 int bits, baud, divisor;
722 struct ktermios *t = &tty->termios;
727 /* Byte size and parity */
728 if ((cflag & CSIZE) == CS8) {
735 if (cflag & CSTOPB) {
742 if (cflag & PARENB) {
745 if (cflag & PARODD) {
755 baud = tty_get_baud_rate(tty);
758 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
759 if ((divisor >= 8192 || divisor < 0) && old_termios) {
760 baud = tty_termios_baud_rate(old_termios);
763 divisor = (rp_baud_base[info->board] / baud) - 1;
765 if (divisor >= 8192 || divisor < 0) {
767 divisor = (rp_baud_base[info->board] / baud) - 1;
769 info->cps = baud / bits;
770 sSetBaud(cp, divisor);
772 /* FIXME: Should really back compute a baud rate from the divisor */
773 tty_encode_baud_rate(tty, baud, baud);
775 if (cflag & CRTSCTS) {
776 info->intmask |= DELTA_CTS;
779 info->intmask &= ~DELTA_CTS;
782 if (cflag & CLOCAL) {
783 info->intmask &= ~DELTA_CD;
785 spin_lock_irqsave(&info->slock, flags);
786 if (sGetChanStatus(cp) & CD_ACT)
790 info->intmask |= DELTA_CD;
791 spin_unlock_irqrestore(&info->slock, flags);
795 * Handle software flow control in the board
797 #ifdef ROCKET_SOFT_FLOW
799 sEnTxSoftFlowCtl(cp);
805 sSetTxXONChar(cp, START_CHAR(tty));
806 sSetTxXOFFChar(cp, STOP_CHAR(tty));
808 sDisTxSoftFlowCtl(cp);
815 * Set up ignore/read mask words
817 info->read_status_mask = STMRCVROVRH | 0xFF;
819 info->read_status_mask |= STMFRAMEH | STMPARITYH;
820 if (I_BRKINT(tty) || I_PARMRK(tty))
821 info->read_status_mask |= STMBREAKH;
824 * Characters to ignore
826 info->ignore_status_mask = 0;
828 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
830 info->ignore_status_mask |= STMBREAKH;
832 * If we're ignoring parity and break indicators,
833 * ignore overruns too. (For real raw support).
836 info->ignore_status_mask |= STMRCVROVRH;
839 rocketMode = info->flags & ROCKET_MODE_MASK;
841 if ((info->flags & ROCKET_RTS_TOGGLE)
842 || (rocketMode == ROCKET_MODE_RS485))
847 sSetRTS(&info->channel);
849 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
850 switch (rocketMode) {
851 case ROCKET_MODE_RS485:
852 sSetInterfaceMode(cp, InterfaceModeRS485);
854 case ROCKET_MODE_RS422:
855 sSetInterfaceMode(cp, InterfaceModeRS422);
857 case ROCKET_MODE_RS232:
859 if (info->flags & ROCKET_RTS_TOGGLE)
860 sSetInterfaceMode(cp, InterfaceModeRS232T);
862 sSetInterfaceMode(cp, InterfaceModeRS232);
868 static int carrier_raised(struct tty_port *port)
870 struct r_port *info = container_of(port, struct r_port, port);
871 return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
874 static void dtr_rts(struct tty_port *port, int on)
876 struct r_port *info = container_of(port, struct r_port, port);
878 sSetDTR(&info->channel);
879 sSetRTS(&info->channel);
881 sClrDTR(&info->channel);
882 sClrRTS(&info->channel);
887 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
888 * port's r_port struct. Initializes the port hardware.
890 static int rp_open(struct tty_struct *tty, struct file *filp)
893 struct tty_port *port;
898 info = rp_table[tty->index];
903 page = __get_free_page(GFP_KERNEL);
907 if (port->flags & ASYNC_CLOSING) {
908 retval = wait_for_completion_interruptible(&info->close_wait);
912 return ((port->flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
916 * We must not sleep from here until the port is marked fully in use.
921 info->xmit_buf = (unsigned char *) page;
923 tty->driver_data = info;
924 tty_port_tty_set(port, tty);
926 if (port->count++ == 0) {
927 atomic_inc(&rp_num_ports_open);
929 #ifdef ROCKET_DEBUG_OPEN
930 printk(KERN_INFO "rocket mod++ = %d...\n",
931 atomic_read(&rp_num_ports_open));
934 #ifdef ROCKET_DEBUG_OPEN
935 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
939 * Info->count is now 1; so it's safe to sleep now.
941 if (!test_bit(ASYNCB_INITIALIZED, &port->flags)) {
943 sSetRxTrigger(cp, TRIG_1);
944 if (sGetChanStatus(cp) & CD_ACT)
948 sDisRxStatusMode(cp);
952 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
953 sSetRxTrigger(cp, TRIG_1);
956 sDisRxStatusMode(cp);
960 sDisTxSoftFlowCtl(cp);
965 set_bit(ASYNCB_INITIALIZED, &info->port.flags);
968 * Set up the tty->alt_speed kludge
970 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
971 tty->alt_speed = 57600;
972 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
973 tty->alt_speed = 115200;
974 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
975 tty->alt_speed = 230400;
976 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
977 tty->alt_speed = 460800;
979 configure_r_port(tty, info, NULL);
980 if (tty->termios.c_cflag & CBAUD) {
985 /* Starts (or resets) the maint polling loop */
986 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
988 retval = tty_port_block_til_ready(port, tty, filp);
990 #ifdef ROCKET_DEBUG_OPEN
991 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
999 * Exception handler that closes a serial port. info->port.count is considered critical.
1001 static void rp_close(struct tty_struct *tty, struct file *filp)
1003 struct r_port *info = tty->driver_data;
1004 struct tty_port *port = &info->port;
1008 if (rocket_paranoia_check(info, "rp_close"))
1011 #ifdef ROCKET_DEBUG_OPEN
1012 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1015 if (tty_port_close_start(port, tty, filp) == 0)
1018 mutex_lock(&port->mutex);
1019 cp = &info->channel;
1021 * Before we drop DTR, make sure the UART transmitter
1022 * has completely drained; this is especially
1023 * important if there is a transmit FIFO!
1025 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1028 rp_wait_until_sent(tty, timeout);
1029 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1032 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1034 sDisTxSoftFlowCtl(cp);
1042 rp_flush_buffer(tty);
1044 tty_ldisc_flush(tty);
1046 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1048 /* We can't yet use tty_port_close_end as the buffer handling in this
1049 driver is a bit different to the usual */
1051 if (port->blocked_open) {
1052 if (port->close_delay) {
1053 msleep_interruptible(jiffies_to_msecs(port->close_delay));
1055 wake_up_interruptible(&port->open_wait);
1057 if (info->xmit_buf) {
1058 free_page((unsigned long) info->xmit_buf);
1059 info->xmit_buf = NULL;
1062 spin_lock_irq(&port->lock);
1063 info->port.flags &= ~(ASYNC_INITIALIZED | ASYNC_CLOSING | ASYNC_NORMAL_ACTIVE);
1065 spin_unlock_irq(&port->lock);
1066 mutex_unlock(&port->mutex);
1067 tty_port_tty_set(port, NULL);
1069 wake_up_interruptible(&port->close_wait);
1070 complete_all(&info->close_wait);
1071 atomic_dec(&rp_num_ports_open);
1073 #ifdef ROCKET_DEBUG_OPEN
1074 printk(KERN_INFO "rocket mod-- = %d...\n",
1075 atomic_read(&rp_num_ports_open));
1076 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1081 static void rp_set_termios(struct tty_struct *tty,
1082 struct ktermios *old_termios)
1084 struct r_port *info = tty->driver_data;
1088 if (rocket_paranoia_check(info, "rp_set_termios"))
1091 cflag = tty->termios.c_cflag;
1094 * This driver doesn't support CS5 or CS6
1096 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1097 tty->termios.c_cflag =
1098 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1100 tty->termios.c_cflag &= ~CMSPAR;
1102 configure_r_port(tty, info, old_termios);
1104 cp = &info->channel;
1106 /* Handle transition to B0 status */
1107 if ((old_termios->c_cflag & CBAUD) && !(tty->termios.c_cflag & CBAUD)) {
1112 /* Handle transition away from B0 status */
1113 if (!(old_termios->c_cflag & CBAUD) && (tty->termios.c_cflag & CBAUD)) {
1114 if (!tty->hw_stopped || !(tty->termios.c_cflag & CRTSCTS))
1119 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios.c_cflag & CRTSCTS)) {
1120 tty->hw_stopped = 0;
1125 static int rp_break(struct tty_struct *tty, int break_state)
1127 struct r_port *info = tty->driver_data;
1128 unsigned long flags;
1130 if (rocket_paranoia_check(info, "rp_break"))
1133 spin_lock_irqsave(&info->slock, flags);
1134 if (break_state == -1)
1135 sSendBreak(&info->channel);
1137 sClrBreak(&info->channel);
1138 spin_unlock_irqrestore(&info->slock, flags);
1143 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1144 * the UPCI boards was added, it was decided to make this a function because
1145 * the macro was getting too complicated. All cases except the first one
1146 * (UPCIRingInd) are taken directly from the original macro.
1148 static int sGetChanRI(CHANNEL_T * ChP)
1150 CONTROLLER_t *CtlP = ChP->CtlP;
1151 int ChanNum = ChP->ChanNum;
1154 if (CtlP->UPCIRingInd)
1155 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1156 else if (CtlP->AltChanRingIndicator)
1157 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1158 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1159 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1164 /********************************************************************************************/
1165 /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1168 * Returns the state of the serial modem control lines. These next 2 functions
1169 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1171 static int rp_tiocmget(struct tty_struct *tty)
1173 struct r_port *info = tty->driver_data;
1174 unsigned int control, result, ChanStatus;
1176 ChanStatus = sGetChanStatusLo(&info->channel);
1177 control = info->channel.TxControl[3];
1178 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1179 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1180 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1181 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1182 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1183 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1189 * Sets the modem control lines
1191 static int rp_tiocmset(struct tty_struct *tty,
1192 unsigned int set, unsigned int clear)
1194 struct r_port *info = tty->driver_data;
1196 if (set & TIOCM_RTS)
1197 info->channel.TxControl[3] |= SET_RTS;
1198 if (set & TIOCM_DTR)
1199 info->channel.TxControl[3] |= SET_DTR;
1200 if (clear & TIOCM_RTS)
1201 info->channel.TxControl[3] &= ~SET_RTS;
1202 if (clear & TIOCM_DTR)
1203 info->channel.TxControl[3] &= ~SET_DTR;
1205 out32(info->channel.IndexAddr, info->channel.TxControl);
1209 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1211 struct rocket_config tmp;
1215 memset(&tmp, 0, sizeof (tmp));
1216 mutex_lock(&info->port.mutex);
1217 tmp.line = info->line;
1218 tmp.flags = info->flags;
1219 tmp.close_delay = info->port.close_delay;
1220 tmp.closing_wait = info->port.closing_wait;
1221 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1222 mutex_unlock(&info->port.mutex);
1224 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1229 static int set_config(struct tty_struct *tty, struct r_port *info,
1230 struct rocket_config __user *new_info)
1232 struct rocket_config new_serial;
1234 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1237 mutex_lock(&info->port.mutex);
1238 if (!capable(CAP_SYS_ADMIN))
1240 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1241 mutex_unlock(&info->port.mutex);
1244 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1245 configure_r_port(tty, info, NULL);
1246 mutex_unlock(&info->port.mutex);
1250 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1251 info->port.close_delay = new_serial.close_delay;
1252 info->port.closing_wait = new_serial.closing_wait;
1254 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1255 tty->alt_speed = 57600;
1256 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1257 tty->alt_speed = 115200;
1258 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1259 tty->alt_speed = 230400;
1260 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1261 tty->alt_speed = 460800;
1262 mutex_unlock(&info->port.mutex);
1264 configure_r_port(tty, info, NULL);
1269 * This function fills in a rocket_ports struct with information
1270 * about what boards/ports are in the system. This info is passed
1271 * to user space. See setrocket.c where the info is used to create
1272 * the /dev/ttyRx ports.
1274 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1276 struct rocket_ports tmp;
1281 memset(&tmp, 0, sizeof (tmp));
1282 tmp.tty_major = rocket_driver->major;
1284 for (board = 0; board < 4; board++) {
1285 tmp.rocketModel[board].model = rocketModel[board].model;
1286 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1287 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1288 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1289 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1291 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1296 static int reset_rm2(struct r_port *info, void __user *arg)
1300 if (!capable(CAP_SYS_ADMIN))
1303 if (copy_from_user(&reset, arg, sizeof (int)))
1308 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1309 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1312 if (info->ctlp->BusType == isISA)
1313 sModemReset(info->ctlp, info->chan, reset);
1315 sPCIModemReset(info->ctlp, info->chan, reset);
1320 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1322 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1327 /* IOCTL call handler into the driver */
1328 static int rp_ioctl(struct tty_struct *tty,
1329 unsigned int cmd, unsigned long arg)
1331 struct r_port *info = tty->driver_data;
1332 void __user *argp = (void __user *)arg;
1335 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1339 case RCKP_GET_STRUCT:
1340 if (copy_to_user(argp, info, sizeof (struct r_port)))
1343 case RCKP_GET_CONFIG:
1344 ret = get_config(info, argp);
1346 case RCKP_SET_CONFIG:
1347 ret = set_config(tty, info, argp);
1349 case RCKP_GET_PORTS:
1350 ret = get_ports(info, argp);
1352 case RCKP_RESET_RM2:
1353 ret = reset_rm2(info, argp);
1355 case RCKP_GET_VERSION:
1356 ret = get_version(info, argp);
1364 static void rp_send_xchar(struct tty_struct *tty, char ch)
1366 struct r_port *info = tty->driver_data;
1369 if (rocket_paranoia_check(info, "rp_send_xchar"))
1372 cp = &info->channel;
1374 sWriteTxPrioByte(cp, ch);
1376 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1379 static void rp_throttle(struct tty_struct *tty)
1381 struct r_port *info = tty->driver_data;
1383 #ifdef ROCKET_DEBUG_THROTTLE
1384 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1385 tty->ldisc.chars_in_buffer(tty));
1388 if (rocket_paranoia_check(info, "rp_throttle"))
1392 rp_send_xchar(tty, STOP_CHAR(tty));
1394 sClrRTS(&info->channel);
1397 static void rp_unthrottle(struct tty_struct *tty)
1399 struct r_port *info = tty->driver_data;
1400 #ifdef ROCKET_DEBUG_THROTTLE
1401 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1402 tty->ldisc.chars_in_buffer(tty));
1405 if (rocket_paranoia_check(info, "rp_throttle"))
1409 rp_send_xchar(tty, START_CHAR(tty));
1411 sSetRTS(&info->channel);
1415 * ------------------------------------------------------------
1416 * rp_stop() and rp_start()
1418 * This routines are called before setting or resetting tty->stopped.
1419 * They enable or disable transmitter interrupts, as necessary.
1420 * ------------------------------------------------------------
1422 static void rp_stop(struct tty_struct *tty)
1424 struct r_port *info = tty->driver_data;
1426 #ifdef ROCKET_DEBUG_FLOW
1427 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1428 info->xmit_cnt, info->xmit_fifo_room);
1431 if (rocket_paranoia_check(info, "rp_stop"))
1434 if (sGetTxCnt(&info->channel))
1435 sDisTransmit(&info->channel);
1438 static void rp_start(struct tty_struct *tty)
1440 struct r_port *info = tty->driver_data;
1442 #ifdef ROCKET_DEBUG_FLOW
1443 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1444 info->xmit_cnt, info->xmit_fifo_room);
1447 if (rocket_paranoia_check(info, "rp_stop"))
1450 sEnTransmit(&info->channel);
1451 set_bit((info->aiop * 8) + info->chan,
1452 (void *) &xmit_flags[info->board]);
1456 * rp_wait_until_sent() --- wait until the transmitter is empty
1458 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1460 struct r_port *info = tty->driver_data;
1462 unsigned long orig_jiffies;
1463 int check_time, exit_time;
1466 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1469 cp = &info->channel;
1471 orig_jiffies = jiffies;
1472 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1473 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1475 printk(KERN_INFO "cps=%d...\n", info->cps);
1478 txcnt = sGetTxCnt(cp);
1480 if (sGetChanStatusLo(cp) & TXSHRMT)
1482 check_time = (HZ / info->cps) / 5;
1484 check_time = HZ * txcnt / info->cps;
1487 exit_time = orig_jiffies + timeout - jiffies;
1490 if (exit_time < check_time)
1491 check_time = exit_time;
1493 if (check_time == 0)
1495 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1496 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1497 jiffies, check_time);
1499 msleep_interruptible(jiffies_to_msecs(check_time));
1500 if (signal_pending(current))
1503 __set_current_state(TASK_RUNNING);
1504 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1505 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1510 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1512 static void rp_hangup(struct tty_struct *tty)
1515 struct r_port *info = tty->driver_data;
1516 unsigned long flags;
1518 if (rocket_paranoia_check(info, "rp_hangup"))
1521 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1522 printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1524 rp_flush_buffer(tty);
1525 spin_lock_irqsave(&info->port.lock, flags);
1526 if (info->port.flags & ASYNC_CLOSING) {
1527 spin_unlock_irqrestore(&info->port.lock, flags);
1530 if (info->port.count)
1531 atomic_dec(&rp_num_ports_open);
1532 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1533 spin_unlock_irqrestore(&info->port.lock, flags);
1535 tty_port_hangup(&info->port);
1537 cp = &info->channel;
1540 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1542 sDisTxSoftFlowCtl(cp);
1544 clear_bit(ASYNCB_INITIALIZED, &info->port.flags);
1546 wake_up_interruptible(&info->port.open_wait);
1550 * Exception handler - write char routine. The RocketPort driver uses a
1551 * double-buffering strategy, with the twist that if the in-memory CPU
1552 * buffer is empty, and there's space in the transmit FIFO, the
1553 * writing routines will write directly to transmit FIFO.
1554 * Write buffer and counters protected by spinlocks
1556 static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1558 struct r_port *info = tty->driver_data;
1560 unsigned long flags;
1562 if (rocket_paranoia_check(info, "rp_put_char"))
1566 * Grab the port write mutex, locking out other processes that try to
1567 * write to this port
1569 mutex_lock(&info->write_mtx);
1571 #ifdef ROCKET_DEBUG_WRITE
1572 printk(KERN_INFO "rp_put_char %c...\n", ch);
1575 spin_lock_irqsave(&info->slock, flags);
1576 cp = &info->channel;
1578 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1579 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1581 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1582 info->xmit_buf[info->xmit_head++] = ch;
1583 info->xmit_head &= XMIT_BUF_SIZE - 1;
1585 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1587 sOutB(sGetTxRxDataIO(cp), ch);
1588 info->xmit_fifo_room--;
1590 spin_unlock_irqrestore(&info->slock, flags);
1591 mutex_unlock(&info->write_mtx);
1596 * Exception handler - write routine, called when user app writes to the device.
1597 * A per port write mutex is used to protect from another process writing to
1598 * this port at the same time. This other process could be running on the other CPU
1599 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1600 * Spinlocks protect the info xmit members.
1602 static int rp_write(struct tty_struct *tty,
1603 const unsigned char *buf, int count)
1605 struct r_port *info = tty->driver_data;
1607 const unsigned char *b;
1609 unsigned long flags;
1611 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1614 if (mutex_lock_interruptible(&info->write_mtx))
1615 return -ERESTARTSYS;
1617 #ifdef ROCKET_DEBUG_WRITE
1618 printk(KERN_INFO "rp_write %d chars...\n", count);
1620 cp = &info->channel;
1622 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1623 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1626 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1627 * into FIFO. Use the write queue for temp storage.
1629 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1630 c = min(count, info->xmit_fifo_room);
1633 /* Push data into FIFO, 2 bytes at a time */
1634 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1636 /* If there is a byte remaining, write it */
1638 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1644 spin_lock_irqsave(&info->slock, flags);
1645 info->xmit_fifo_room -= c;
1646 spin_unlock_irqrestore(&info->slock, flags);
1649 /* If count is zero, we wrote it all and are done */
1653 /* Write remaining data into the port's xmit_buf */
1656 if (!test_bit(ASYNCB_NORMAL_ACTIVE, &info->port.flags))
1658 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1659 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1664 memcpy(info->xmit_buf + info->xmit_head, b, c);
1666 spin_lock_irqsave(&info->slock, flags);
1668 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1669 info->xmit_cnt += c;
1670 spin_unlock_irqrestore(&info->slock, flags);
1677 if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1678 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1681 if (info->xmit_cnt < WAKEUP_CHARS) {
1683 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1684 wake_up_interruptible(&tty->poll_wait);
1687 mutex_unlock(&info->write_mtx);
1692 * Return the number of characters that can be sent. We estimate
1693 * only using the in-memory transmit buffer only, and ignore the
1694 * potential space in the transmit FIFO.
1696 static int rp_write_room(struct tty_struct *tty)
1698 struct r_port *info = tty->driver_data;
1701 if (rocket_paranoia_check(info, "rp_write_room"))
1704 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1707 #ifdef ROCKET_DEBUG_WRITE
1708 printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1714 * Return the number of characters in the buffer. Again, this only
1715 * counts those characters in the in-memory transmit buffer.
1717 static int rp_chars_in_buffer(struct tty_struct *tty)
1719 struct r_port *info = tty->driver_data;
1721 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1724 #ifdef ROCKET_DEBUG_WRITE
1725 printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1727 return info->xmit_cnt;
1731 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1732 * r_port struct for the port. Note that spinlock are used to protect info members,
1733 * do not call this function if the spinlock is already held.
1735 static void rp_flush_buffer(struct tty_struct *tty)
1737 struct r_port *info = tty->driver_data;
1739 unsigned long flags;
1741 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1744 spin_lock_irqsave(&info->slock, flags);
1745 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1746 spin_unlock_irqrestore(&info->slock, flags);
1748 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1749 wake_up_interruptible(&tty->poll_wait);
1753 cp = &info->channel;
1759 static struct pci_device_id __used rocket_pci_ids[] = {
1760 { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) },
1763 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1766 * Called when a PCI card is found. Retrieves and stores model information,
1767 * init's aiopic and serial port hardware.
1768 * Inputs: i is the board number (0-n)
1770 static __init int register_PCI(int i, struct pci_dev *dev)
1772 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1773 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1777 int altChanRingIndicator = 0;
1778 int ports_per_aiop = 8;
1779 WordIO_t ConfigIO = 0;
1780 ByteIO_t UPCIRingInd = 0;
1782 if (!dev || pci_enable_device(dev))
1785 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1787 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1788 rocketModel[i].loadrm2 = 0;
1789 rocketModel[i].startingPortNumber = nextLineNumber;
1791 /* Depending on the model, set up some config variables */
1792 switch (dev->device) {
1793 case PCI_DEVICE_ID_RP4QUAD:
1796 rocketModel[i].model = MODEL_RP4QUAD;
1797 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1798 rocketModel[i].numPorts = 4;
1800 case PCI_DEVICE_ID_RP8OCTA:
1802 rocketModel[i].model = MODEL_RP8OCTA;
1803 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1804 rocketModel[i].numPorts = 8;
1806 case PCI_DEVICE_ID_URP8OCTA:
1808 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1809 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1810 rocketModel[i].numPorts = 8;
1812 case PCI_DEVICE_ID_RP8INTF:
1814 rocketModel[i].model = MODEL_RP8INTF;
1815 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1816 rocketModel[i].numPorts = 8;
1818 case PCI_DEVICE_ID_URP8INTF:
1820 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1821 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1822 rocketModel[i].numPorts = 8;
1824 case PCI_DEVICE_ID_RP8J:
1826 rocketModel[i].model = MODEL_RP8J;
1827 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1828 rocketModel[i].numPorts = 8;
1830 case PCI_DEVICE_ID_RP4J:
1833 rocketModel[i].model = MODEL_RP4J;
1834 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1835 rocketModel[i].numPorts = 4;
1837 case PCI_DEVICE_ID_RP8SNI:
1839 rocketModel[i].model = MODEL_RP8SNI;
1840 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1841 rocketModel[i].numPorts = 8;
1843 case PCI_DEVICE_ID_RP16SNI:
1845 rocketModel[i].model = MODEL_RP16SNI;
1846 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1847 rocketModel[i].numPorts = 16;
1849 case PCI_DEVICE_ID_RP16INTF:
1851 rocketModel[i].model = MODEL_RP16INTF;
1852 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1853 rocketModel[i].numPorts = 16;
1855 case PCI_DEVICE_ID_URP16INTF:
1857 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1858 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1859 rocketModel[i].numPorts = 16;
1861 case PCI_DEVICE_ID_CRP16INTF:
1863 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1864 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1865 rocketModel[i].numPorts = 16;
1867 case PCI_DEVICE_ID_RP32INTF:
1869 rocketModel[i].model = MODEL_RP32INTF;
1870 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1871 rocketModel[i].numPorts = 32;
1873 case PCI_DEVICE_ID_URP32INTF:
1875 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1876 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1877 rocketModel[i].numPorts = 32;
1879 case PCI_DEVICE_ID_RPP4:
1882 altChanRingIndicator++;
1884 rocketModel[i].model = MODEL_RPP4;
1885 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
1886 rocketModel[i].numPorts = 4;
1888 case PCI_DEVICE_ID_RPP8:
1891 altChanRingIndicator++;
1893 rocketModel[i].model = MODEL_RPP8;
1894 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
1895 rocketModel[i].numPorts = 8;
1897 case PCI_DEVICE_ID_RP2_232:
1900 altChanRingIndicator++;
1902 rocketModel[i].model = MODEL_RP2_232;
1903 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
1904 rocketModel[i].numPorts = 2;
1906 case PCI_DEVICE_ID_RP2_422:
1909 altChanRingIndicator++;
1911 rocketModel[i].model = MODEL_RP2_422;
1912 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
1913 rocketModel[i].numPorts = 2;
1915 case PCI_DEVICE_ID_RP6M:
1920 /* If revision is 1, the rocketmodem flash must be loaded.
1921 * If it is 2 it is a "socketed" version. */
1922 if (dev->revision == 1) {
1923 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1924 rocketModel[i].loadrm2 = 1;
1926 rcktpt_type[i] = ROCKET_TYPE_MODEM;
1929 rocketModel[i].model = MODEL_RP6M;
1930 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
1931 rocketModel[i].numPorts = 6;
1933 case PCI_DEVICE_ID_RP4M:
1936 if (dev->revision == 1) {
1937 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1938 rocketModel[i].loadrm2 = 1;
1940 rcktpt_type[i] = ROCKET_TYPE_MODEM;
1943 rocketModel[i].model = MODEL_RP4M;
1944 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
1945 rocketModel[i].numPorts = 4;
1953 * Check for UPCI boards.
1956 switch (dev->device) {
1957 case PCI_DEVICE_ID_URP32INTF:
1958 case PCI_DEVICE_ID_URP8INTF:
1959 case PCI_DEVICE_ID_URP16INTF:
1960 case PCI_DEVICE_ID_CRP16INTF:
1961 case PCI_DEVICE_ID_URP8OCTA:
1962 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1963 ConfigIO = pci_resource_start(dev, 1);
1964 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
1965 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
1968 * Check for octa or quad cable.
1971 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
1972 PCI_GPIO_CTRL_8PORT)) {
1974 rocketModel[i].numPorts = 4;
1978 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
1980 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
1981 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
1982 rocketModel[i].numPorts = 8;
1983 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1984 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
1985 ConfigIO = pci_resource_start(dev, 1);
1986 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
1988 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
1990 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
1991 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
1992 rocketModel[i].numPorts = 4;
1993 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1994 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
1995 ConfigIO = pci_resource_start(dev, 1);
1996 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2003 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2004 rp_baud_base[i] = 921600;
2007 * If support_low_speed is set, use the slow clock
2008 * prescale, which supports 50 bps
2010 if (support_low_speed) {
2011 /* mod 9 (divide by 10) prescale */
2012 sClockPrescale = 0x19;
2013 rp_baud_base[i] = 230400;
2015 /* mod 4 (divide by 5) prescale */
2016 sClockPrescale = 0x14;
2017 rp_baud_base[i] = 460800;
2021 for (aiop = 0; aiop < max_num_aiops; aiop++)
2022 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2023 ctlp = sCtlNumToCtlPtr(i);
2024 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2025 for (aiop = 0; aiop < max_num_aiops; aiop++)
2026 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2028 dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2029 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2030 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2031 rocketModel[i].startingPortNumber,
2032 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2034 if (num_aiops <= 0) {
2035 rcktpt_io_addr[i] = 0;
2040 /* Reset the AIOPIC, init the serial ports */
2041 for (aiop = 0; aiop < num_aiops; aiop++) {
2042 sResetAiopByNum(ctlp, aiop);
2043 num_chan = ports_per_aiop;
2044 for (chan = 0; chan < num_chan; chan++)
2045 init_r_port(i, aiop, chan, dev);
2048 /* Rocket modems must be reset */
2049 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2050 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2051 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2052 num_chan = ports_per_aiop;
2053 for (chan = 0; chan < num_chan; chan++)
2054 sPCIModemReset(ctlp, chan, 1);
2056 for (chan = 0; chan < num_chan; chan++)
2057 sPCIModemReset(ctlp, chan, 0);
2059 rmSpeakerReset(ctlp, rocketModel[i].model);
2065 * Probes for PCI cards, inits them if found
2066 * Input: board_found = number of ISA boards already found, or the
2067 * starting board number
2068 * Returns: Number of PCI boards found
2070 static int __init init_PCI(int boards_found)
2072 struct pci_dev *dev = NULL;
2075 /* Work through the PCI device list, pulling out ours */
2076 while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2077 if (register_PCI(count + boards_found, dev))
2083 #endif /* CONFIG_PCI */
2086 * Probes for ISA cards
2087 * Input: i = the board number to look for
2088 * Returns: 1 if board found, 0 else
2090 static int __init init_ISA(int i)
2092 int num_aiops, num_chan = 0, total_num_chan = 0;
2094 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2098 /* If io_addr is zero, no board configured */
2099 if (rcktpt_io_addr[i] == 0)
2102 /* Reserve the IO region */
2103 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2104 printk(KERN_ERR "Unable to reserve IO region for configured "
2105 "ISA RocketPort at address 0x%lx, board not "
2106 "installed...\n", rcktpt_io_addr[i]);
2107 rcktpt_io_addr[i] = 0;
2111 ctlp = sCtlNumToCtlPtr(i);
2113 ctlp->boardType = rcktpt_type[i];
2115 switch (rcktpt_type[i]) {
2116 case ROCKET_TYPE_PC104:
2117 type_string = "(PC104)";
2119 case ROCKET_TYPE_MODEM:
2120 type_string = "(RocketModem)";
2122 case ROCKET_TYPE_MODEMII:
2123 type_string = "(RocketModem II)";
2131 * If support_low_speed is set, use the slow clock prescale,
2132 * which supports 50 bps
2134 if (support_low_speed) {
2135 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2136 rp_baud_base[i] = 230400;
2138 sClockPrescale = 0x14; /* mod 4 (divide by 5) prescale */
2139 rp_baud_base[i] = 460800;
2142 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2143 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2145 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2147 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2148 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2149 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2152 /* If something went wrong initing the AIOP's release the ISA IO memory */
2153 if (num_aiops <= 0) {
2154 release_region(rcktpt_io_addr[i], 64);
2155 rcktpt_io_addr[i] = 0;
2159 rocketModel[i].startingPortNumber = nextLineNumber;
2161 for (aiop = 0; aiop < num_aiops; aiop++) {
2162 sResetAiopByNum(ctlp, aiop);
2163 sEnAiop(ctlp, aiop);
2164 num_chan = sGetAiopNumChan(ctlp, aiop);
2165 total_num_chan += num_chan;
2166 for (chan = 0; chan < num_chan; chan++)
2167 init_r_port(i, aiop, chan, NULL);
2170 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2171 num_chan = sGetAiopNumChan(ctlp, 0);
2172 total_num_chan = num_chan;
2173 for (chan = 0; chan < num_chan; chan++)
2174 sModemReset(ctlp, chan, 1);
2176 for (chan = 0; chan < num_chan; chan++)
2177 sModemReset(ctlp, chan, 0);
2179 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2181 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2183 rocketModel[i].numPorts = total_num_chan;
2184 rocketModel[i].model = MODEL_ISA;
2186 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2187 i, rcktpt_io_addr[i], num_aiops, type_string);
2189 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2190 rocketModel[i].modelString,
2191 rocketModel[i].startingPortNumber,
2192 rocketModel[i].startingPortNumber +
2193 rocketModel[i].numPorts - 1);
2198 static const struct tty_operations rocket_ops = {
2202 .put_char = rp_put_char,
2203 .write_room = rp_write_room,
2204 .chars_in_buffer = rp_chars_in_buffer,
2205 .flush_buffer = rp_flush_buffer,
2207 .throttle = rp_throttle,
2208 .unthrottle = rp_unthrottle,
2209 .set_termios = rp_set_termios,
2212 .hangup = rp_hangup,
2213 .break_ctl = rp_break,
2214 .send_xchar = rp_send_xchar,
2215 .wait_until_sent = rp_wait_until_sent,
2216 .tiocmget = rp_tiocmget,
2217 .tiocmset = rp_tiocmset,
2220 static const struct tty_port_operations rocket_port_ops = {
2221 .carrier_raised = carrier_raised,
2226 * The module "startup" routine; it's run when the module is loaded.
2228 static int __init rp_init(void)
2230 int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2232 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2233 ROCKET_VERSION, ROCKET_DATE);
2235 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2240 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2241 * zero, use the default controller IO address of board1 + 0x40.
2244 if (controller == 0)
2245 controller = board1 + 0x40;
2247 controller = 0; /* Used as a flag, meaning no ISA boards */
2250 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2251 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2252 printk(KERN_ERR "Unable to reserve IO region for first "
2253 "configured ISA RocketPort controller 0x%lx. "
2254 "Driver exiting\n", controller);
2259 /* Store ISA variable retrieved from command line or .conf file. */
2260 rcktpt_io_addr[0] = board1;
2261 rcktpt_io_addr[1] = board2;
2262 rcktpt_io_addr[2] = board3;
2263 rcktpt_io_addr[3] = board4;
2265 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2266 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2267 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2268 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2269 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2270 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2271 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2272 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2275 * Set up the tty driver structure and then register this
2276 * driver with the tty layer.
2279 rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2280 rocket_driver->name = "ttyR";
2281 rocket_driver->driver_name = "Comtrol RocketPort";
2282 rocket_driver->major = TTY_ROCKET_MAJOR;
2283 rocket_driver->minor_start = 0;
2284 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2285 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2286 rocket_driver->init_termios = tty_std_termios;
2287 rocket_driver->init_termios.c_cflag =
2288 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2289 rocket_driver->init_termios.c_ispeed = 9600;
2290 rocket_driver->init_termios.c_ospeed = 9600;
2291 #ifdef ROCKET_SOFT_FLOW
2292 rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2294 tty_set_operations(rocket_driver, &rocket_ops);
2296 ret = tty_register_driver(rocket_driver);
2298 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2299 goto err_controller;
2302 #ifdef ROCKET_DEBUG_OPEN
2303 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2307 * OK, let's probe each of the controllers looking for boards. Any boards found
2308 * will be initialized here.
2310 isa_boards_found = 0;
2311 pci_boards_found = 0;
2313 for (i = 0; i < NUM_BOARDS; i++) {
2319 if (isa_boards_found < NUM_BOARDS)
2320 pci_boards_found = init_PCI(isa_boards_found);
2323 max_board = pci_boards_found + isa_boards_found;
2325 if (max_board == 0) {
2326 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2333 tty_unregister_driver(rocket_driver);
2336 release_region(controller, 4);
2338 put_tty_driver(rocket_driver);
2344 static void rp_cleanup_module(void)
2349 del_timer_sync(&rocket_timer);
2351 retval = tty_unregister_driver(rocket_driver);
2353 printk(KERN_ERR "Error %d while trying to unregister "
2354 "rocketport driver\n", -retval);
2356 for (i = 0; i < MAX_RP_PORTS; i++)
2358 tty_unregister_device(rocket_driver, i);
2359 tty_port_destroy(&rp_table[i]->port);
2363 put_tty_driver(rocket_driver);
2365 for (i = 0; i < NUM_BOARDS; i++) {
2366 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2368 release_region(rcktpt_io_addr[i], 64);
2371 release_region(controller, 4);
2374 /***************************************************************************
2375 Function: sInitController
2376 Purpose: Initialization of controller global registers and controller
2378 Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2379 IRQNum,Frequency,PeriodicOnly)
2380 CONTROLLER_T *CtlP; Ptr to controller structure
2381 int CtlNum; Controller number
2382 ByteIO_t MudbacIO; Mudbac base I/O address.
2383 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2384 This list must be in the order the AIOPs will be found on the
2385 controller. Once an AIOP in the list is not found, it is
2386 assumed that there are no more AIOPs on the controller.
2387 int AiopIOListSize; Number of addresses in AiopIOList
2388 int IRQNum; Interrupt Request number. Can be any of the following:
2389 0: Disable global interrupts
2398 Byte_t Frequency: A flag identifying the frequency
2399 of the periodic interrupt, can be any one of the following:
2400 FREQ_DIS - periodic interrupt disabled
2401 FREQ_137HZ - 137 Hertz
2402 FREQ_69HZ - 69 Hertz
2403 FREQ_34HZ - 34 Hertz
2404 FREQ_17HZ - 17 Hertz
2407 If IRQNum is set to 0 the Frequency parameter is
2408 overidden, it is forced to a value of FREQ_DIS.
2409 int PeriodicOnly: 1 if all interrupts except the periodic
2410 interrupt are to be blocked.
2411 0 is both the periodic interrupt and
2412 other channel interrupts are allowed.
2413 If IRQNum is set to 0 the PeriodicOnly parameter is
2414 overidden, it is forced to a value of 0.
2415 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2416 initialization failed.
2419 If periodic interrupts are to be disabled but AIOP interrupts
2420 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2422 If interrupts are to be completely disabled set IRQNum to 0.
2424 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2425 invalid combination.
2427 This function performs initialization of global interrupt modes,
2428 but it does not actually enable global interrupts. To enable
2429 and disable global interrupts use functions sEnGlobalInt() and
2430 sDisGlobalInt(). Enabling of global interrupts is normally not
2431 done until all other initializations are complete.
2433 Even if interrupts are globally enabled, they must also be
2434 individually enabled for each channel that is to generate
2437 Warnings: No range checking on any of the parameters is done.
2439 No context switches are allowed while executing this function.
2441 After this function all AIOPs on the controller are disabled,
2442 they can be enabled with sEnAiop().
2444 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2445 ByteIO_t * AiopIOList, int AiopIOListSize,
2446 int IRQNum, Byte_t Frequency, int PeriodicOnly)
2452 CtlP->AiopIntrBits = aiop_intr_bits;
2453 CtlP->AltChanRingIndicator = 0;
2454 CtlP->CtlNum = CtlNum;
2455 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2456 CtlP->BusType = isISA;
2457 CtlP->MBaseIO = MudbacIO;
2458 CtlP->MReg1IO = MudbacIO + 1;
2459 CtlP->MReg2IO = MudbacIO + 2;
2460 CtlP->MReg3IO = MudbacIO + 3;
2462 CtlP->MReg2 = 0; /* interrupt disable */
2463 CtlP->MReg3 = 0; /* no periodic interrupts */
2465 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2466 CtlP->MReg2 = 0; /* interrupt disable */
2467 CtlP->MReg3 = 0; /* no periodic interrupts */
2469 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2470 CtlP->MReg3 = Frequency; /* set frequency */
2471 if (PeriodicOnly) { /* periodic interrupt only */
2472 CtlP->MReg3 |= PERIODIC_ONLY;
2476 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2477 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2478 sControllerEOI(CtlP); /* clear EOI if warm init */
2481 for (i = done = 0; i < AiopIOListSize; i++) {
2483 CtlP->AiopIO[i] = (WordIO_t) io;
2484 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2485 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2486 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2489 sEnAiop(CtlP, i); /* enable the AIOP */
2490 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2491 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2492 done = 1; /* done looking for AIOPs */
2494 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2495 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2496 sOutB(io + _INDX_DATA, sClockPrescale);
2497 CtlP->NumAiop++; /* bump count of AIOPs */
2499 sDisAiop(CtlP, i); /* disable AIOP */
2502 if (CtlP->NumAiop == 0)
2505 return (CtlP->NumAiop);
2508 /***************************************************************************
2509 Function: sPCIInitController
2510 Purpose: Initialization of controller global registers and controller
2512 Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2513 IRQNum,Frequency,PeriodicOnly)
2514 CONTROLLER_T *CtlP; Ptr to controller structure
2515 int CtlNum; Controller number
2516 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2517 This list must be in the order the AIOPs will be found on the
2518 controller. Once an AIOP in the list is not found, it is
2519 assumed that there are no more AIOPs on the controller.
2520 int AiopIOListSize; Number of addresses in AiopIOList
2521 int IRQNum; Interrupt Request number. Can be any of the following:
2522 0: Disable global interrupts
2531 Byte_t Frequency: A flag identifying the frequency
2532 of the periodic interrupt, can be any one of the following:
2533 FREQ_DIS - periodic interrupt disabled
2534 FREQ_137HZ - 137 Hertz
2535 FREQ_69HZ - 69 Hertz
2536 FREQ_34HZ - 34 Hertz
2537 FREQ_17HZ - 17 Hertz
2540 If IRQNum is set to 0 the Frequency parameter is
2541 overidden, it is forced to a value of FREQ_DIS.
2542 int PeriodicOnly: 1 if all interrupts except the periodic
2543 interrupt are to be blocked.
2544 0 is both the periodic interrupt and
2545 other channel interrupts are allowed.
2546 If IRQNum is set to 0 the PeriodicOnly parameter is
2547 overidden, it is forced to a value of 0.
2548 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2549 initialization failed.
2552 If periodic interrupts are to be disabled but AIOP interrupts
2553 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2555 If interrupts are to be completely disabled set IRQNum to 0.
2557 Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2558 invalid combination.
2560 This function performs initialization of global interrupt modes,
2561 but it does not actually enable global interrupts. To enable
2562 and disable global interrupts use functions sEnGlobalInt() and
2563 sDisGlobalInt(). Enabling of global interrupts is normally not
2564 done until all other initializations are complete.
2566 Even if interrupts are globally enabled, they must also be
2567 individually enabled for each channel that is to generate
2570 Warnings: No range checking on any of the parameters is done.
2572 No context switches are allowed while executing this function.
2574 After this function all AIOPs on the controller are disabled,
2575 they can be enabled with sEnAiop().
2577 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2578 ByteIO_t * AiopIOList, int AiopIOListSize,
2579 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2580 int PeriodicOnly, int altChanRingIndicator,
2586 CtlP->AltChanRingIndicator = altChanRingIndicator;
2587 CtlP->UPCIRingInd = UPCIRingInd;
2588 CtlP->CtlNum = CtlNum;
2589 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2590 CtlP->BusType = isPCI; /* controller release 1 */
2594 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2595 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2596 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2600 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2601 CtlP->AiopIntrBits = aiop_intr_bits;
2604 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2607 for (i = 0; i < AiopIOListSize; i++) {
2609 CtlP->AiopIO[i] = (WordIO_t) io;
2610 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2612 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2613 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2614 break; /* done looking for AIOPs */
2616 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2617 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2618 sOutB(io + _INDX_DATA, sClockPrescale);
2619 CtlP->NumAiop++; /* bump count of AIOPs */
2622 if (CtlP->NumAiop == 0)
2625 return (CtlP->NumAiop);
2628 /***************************************************************************
2629 Function: sReadAiopID
2630 Purpose: Read the AIOP idenfication number directly from an AIOP.
2631 Call: sReadAiopID(io)
2632 ByteIO_t io: AIOP base I/O address
2633 Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2634 is replace by an identifying number.
2635 Flag AIOPID_NULL if no valid AIOP is found
2636 Warnings: No context switches are allowed while executing this function.
2639 static int sReadAiopID(ByteIO_t io)
2641 Byte_t AiopID; /* ID byte from AIOP */
2643 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2644 sOutB(io + _CMD_REG, 0x0);
2645 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2648 else /* AIOP does not exist */
2652 /***************************************************************************
2653 Function: sReadAiopNumChan
2654 Purpose: Read the number of channels available in an AIOP directly from
2656 Call: sReadAiopNumChan(io)
2657 WordIO_t io: AIOP base I/O address
2658 Return: int: The number of channels available
2659 Comments: The number of channels is determined by write/reads from identical
2660 offsets within the SRAM address spaces for channels 0 and 4.
2661 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2662 AIOP, otherwise it is an 8 channel.
2663 Warnings: No context switches are allowed while executing this function.
2665 static int sReadAiopNumChan(WordIO_t io)
2668 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2670 /* write to chan 0 SRAM */
2671 out32((DWordIO_t) io + _INDX_ADDR, R);
2672 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2673 x = sInW(io + _INDX_DATA);
2674 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2675 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2681 /***************************************************************************
2683 Purpose: Initialization of a channel and channel structure
2684 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2685 CONTROLLER_T *CtlP; Ptr to controller structure
2686 CHANNEL_T *ChP; Ptr to channel structure
2687 int AiopNum; AIOP number within controller
2688 int ChanNum; Channel number within AIOP
2689 Return: int: 1 if initialization succeeded, 0 if it fails because channel
2690 number exceeds number of channels available in AIOP.
2691 Comments: This function must be called before a channel can be used.
2692 Warnings: No range checking on any of the parameters is done.
2694 No context switches are allowed while executing this function.
2696 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2707 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2708 return 0; /* exceeds num chans in AIOP */
2710 /* Channel, AIOP, and controller identifiers */
2712 ChP->ChanID = CtlP->AiopID[AiopNum];
2713 ChP->AiopNum = AiopNum;
2714 ChP->ChanNum = ChanNum;
2716 /* Global direct addresses */
2717 AiopIO = CtlP->AiopIO[AiopNum];
2718 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2719 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2720 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2721 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2722 ChP->IndexData = AiopIO + _INDX_DATA;
2724 /* Channel direct addresses */
2725 ChIOOff = AiopIO + ChP->ChanNum * 2;
2726 ChP->TxRxData = ChIOOff + _TD0;
2727 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2728 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2729 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2731 /* Initialize the channel from the RData array */
2732 for (i = 0; i < RDATASIZE; i += 4) {
2734 R[1] = RData[i + 1] + 0x10 * ChanNum;
2735 R[2] = RData[i + 2];
2736 R[3] = RData[i + 3];
2737 out32(ChP->IndexAddr, R);
2741 for (i = 0; i < RREGDATASIZE; i += 4) {
2742 ChR[i] = RRegData[i];
2743 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2744 ChR[i + 2] = RRegData[i + 2];
2745 ChR[i + 3] = RRegData[i + 3];
2748 /* Indexed registers */
2749 ChOff = (Word_t) ChanNum *0x1000;
2751 if (sClockPrescale == 0x14)
2756 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2757 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2758 ChP->BaudDiv[2] = (Byte_t) brd9600;
2759 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2760 out32(ChP->IndexAddr, ChP->BaudDiv);
2762 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2763 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2764 ChP->TxControl[2] = 0;
2765 ChP->TxControl[3] = 0;
2766 out32(ChP->IndexAddr, ChP->TxControl);
2768 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2769 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2770 ChP->RxControl[2] = 0;
2771 ChP->RxControl[3] = 0;
2772 out32(ChP->IndexAddr, ChP->RxControl);
2774 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2775 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2776 ChP->TxEnables[2] = 0;
2777 ChP->TxEnables[3] = 0;
2778 out32(ChP->IndexAddr, ChP->TxEnables);
2780 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2781 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2782 ChP->TxCompare[2] = 0;
2783 ChP->TxCompare[3] = 0;
2784 out32(ChP->IndexAddr, ChP->TxCompare);
2786 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2787 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2788 ChP->TxReplace1[2] = 0;
2789 ChP->TxReplace1[3] = 0;
2790 out32(ChP->IndexAddr, ChP->TxReplace1);
2792 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2793 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2794 ChP->TxReplace2[2] = 0;
2795 ChP->TxReplace2[3] = 0;
2796 out32(ChP->IndexAddr, ChP->TxReplace2);
2798 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2799 ChP->TxFIFO = ChOff + _TX_FIFO;
2801 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2802 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2803 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2804 sOutW(ChP->IndexData, 0);
2805 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2806 ChP->RxFIFO = ChOff + _RX_FIFO;
2808 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
2809 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
2810 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2811 sOutW(ChP->IndexData, 0);
2812 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2813 sOutW(ChP->IndexData, 0);
2814 ChP->TxPrioCnt = ChOff + _TXP_CNT;
2815 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2816 sOutB(ChP->IndexData, 0);
2817 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2818 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2819 sOutB(ChP->IndexData, 0);
2820 ChP->TxPrioBuf = ChOff + _TXP_BUF;
2821 sEnRxProcessor(ChP); /* start the Rx processor */
2826 /***************************************************************************
2827 Function: sStopRxProcessor
2828 Purpose: Stop the receive processor from processing a channel.
2829 Call: sStopRxProcessor(ChP)
2830 CHANNEL_T *ChP; Ptr to channel structure
2832 Comments: The receive processor can be started again with sStartRxProcessor().
2833 This function causes the receive processor to skip over the
2834 stopped channel. It does not stop it from processing other channels.
2836 Warnings: No context switches are allowed while executing this function.
2838 Do not leave the receive processor stopped for more than one
2841 After calling this function a delay of 4 uS is required to ensure
2842 that the receive processor is no longer processing this channel.
2844 static void sStopRxProcessor(CHANNEL_T * ChP)
2852 out32(ChP->IndexAddr, R);
2855 /***************************************************************************
2856 Function: sFlushRxFIFO
2857 Purpose: Flush the Rx FIFO
2858 Call: sFlushRxFIFO(ChP)
2859 CHANNEL_T *ChP; Ptr to channel structure
2861 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2862 while it is being flushed the receive processor is stopped
2863 and the transmitter is disabled. After these operations a
2864 4 uS delay is done before clearing the pointers to allow
2865 the receive processor to stop. These items are handled inside
2867 Warnings: No context switches are allowed while executing this function.
2869 static void sFlushRxFIFO(CHANNEL_T * ChP)
2872 Byte_t Ch; /* channel number within AIOP */
2873 int RxFIFOEnabled; /* 1 if Rx FIFO enabled */
2875 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
2876 return; /* don't need to flush */
2879 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
2881 sDisRxFIFO(ChP); /* disable it */
2882 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
2883 sInB(ChP->IntChan); /* depends on bus i/o timing */
2885 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
2886 Ch = (Byte_t) sGetChanNum(ChP);
2887 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
2888 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
2889 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
2890 sOutW(ChP->IndexData, 0);
2891 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
2892 sOutW(ChP->IndexData, 0);
2894 sEnRxFIFO(ChP); /* enable Rx FIFO */
2897 /***************************************************************************
2898 Function: sFlushTxFIFO
2899 Purpose: Flush the Tx FIFO
2900 Call: sFlushTxFIFO(ChP)
2901 CHANNEL_T *ChP; Ptr to channel structure
2903 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2904 while it is being flushed the receive processor is stopped
2905 and the transmitter is disabled. After these operations a
2906 4 uS delay is done before clearing the pointers to allow
2907 the receive processor to stop. These items are handled inside
2909 Warnings: No context switches are allowed while executing this function.
2911 static void sFlushTxFIFO(CHANNEL_T * ChP)
2914 Byte_t Ch; /* channel number within AIOP */
2915 int TxEnabled; /* 1 if transmitter enabled */
2917 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
2918 return; /* don't need to flush */
2921 if (ChP->TxControl[3] & TX_ENABLE) {
2923 sDisTransmit(ChP); /* disable transmitter */
2925 sStopRxProcessor(ChP); /* stop Rx processor */
2926 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
2927 sInB(ChP->IntChan); /* depends on bus i/o timing */
2928 Ch = (Byte_t) sGetChanNum(ChP);
2929 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
2930 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
2931 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2932 sOutW(ChP->IndexData, 0);
2934 sEnTransmit(ChP); /* enable transmitter */
2935 sStartRxProcessor(ChP); /* restart Rx processor */
2938 /***************************************************************************
2939 Function: sWriteTxPrioByte
2940 Purpose: Write a byte of priority transmit data to a channel
2941 Call: sWriteTxPrioByte(ChP,Data)
2942 CHANNEL_T *ChP; Ptr to channel structure
2943 Byte_t Data; The transmit data byte
2945 Return: int: 1 if the bytes is successfully written, otherwise 0.
2947 Comments: The priority byte is transmitted before any data in the Tx FIFO.
2949 Warnings: No context switches are allowed while executing this function.
2951 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
2953 Byte_t DWBuf[4]; /* buffer for double word writes */
2954 Word_t *WordPtr; /* must be far because Win SS != DS */
2955 register DWordIO_t IndexAddr;
2957 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
2958 IndexAddr = ChP->IndexAddr;
2959 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
2960 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
2961 return (0); /* nothing sent */
2963 WordPtr = (Word_t *) (&DWBuf[0]);
2964 *WordPtr = ChP->TxPrioBuf; /* data byte address */
2966 DWBuf[2] = Data; /* data byte value */
2967 out32(IndexAddr, DWBuf); /* write it out */
2969 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
2971 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
2972 DWBuf[3] = 0; /* priority buffer pointer */
2973 out32(IndexAddr, DWBuf); /* write it out */
2974 } else { /* write it to Tx FIFO */
2976 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
2978 return (1); /* 1 byte sent */
2981 /***************************************************************************
2982 Function: sEnInterrupts
2983 Purpose: Enable one or more interrupts for a channel
2984 Call: sEnInterrupts(ChP,Flags)
2985 CHANNEL_T *ChP; Ptr to channel structure
2986 Word_t Flags: Interrupt enable flags, can be any combination
2987 of the following flags:
2988 TXINT_EN: Interrupt on Tx FIFO empty
2989 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
2991 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
2992 MCINT_EN: Interrupt on modem input change
2993 CHANINT_EN: Allow channel interrupt signal to the AIOP's
2994 Interrupt Channel Register.
2996 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
2997 enabled. If an interrupt enable flag is not set in Flags, that
2998 interrupt will not be changed. Interrupts can be disabled with
2999 function sDisInterrupts().
3001 This function sets the appropriate bit for the channel in the AIOP's
3002 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3003 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3005 Interrupts must also be globally enabled before channel interrupts
3006 will be passed on to the host. This is done with function
3009 In some cases it may be desirable to disable interrupts globally but
3010 enable channel interrupts. This would allow the global interrupt
3011 status register to be used to determine which AIOPs need service.
3013 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3015 Byte_t Mask; /* Interrupt Mask Register */
3017 ChP->RxControl[2] |=
3018 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3020 out32(ChP->IndexAddr, ChP->RxControl);
3022 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3024 out32(ChP->IndexAddr, ChP->TxControl);
3026 if (Flags & CHANINT_EN) {
3027 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3028 sOutB(ChP->IntMask, Mask);
3032 /***************************************************************************
3033 Function: sDisInterrupts
3034 Purpose: Disable one or more interrupts for a channel
3035 Call: sDisInterrupts(ChP,Flags)
3036 CHANNEL_T *ChP; Ptr to channel structure
3037 Word_t Flags: Interrupt flags, can be any combination
3038 of the following flags:
3039 TXINT_EN: Interrupt on Tx FIFO empty
3040 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3042 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3043 MCINT_EN: Interrupt on modem input change
3044 CHANINT_EN: Disable channel interrupt signal to the
3045 AIOP's Interrupt Channel Register.
3047 Comments: If an interrupt flag is set in Flags, that interrupt will be
3048 disabled. If an interrupt flag is not set in Flags, that
3049 interrupt will not be changed. Interrupts can be enabled with
3050 function sEnInterrupts().
3052 This function clears the appropriate bit for the channel in the AIOP's
3053 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3054 this channel's bit from being set in the AIOP's Interrupt Channel
3057 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3059 Byte_t Mask; /* Interrupt Mask Register */
3061 ChP->RxControl[2] &=
3062 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3063 out32(ChP->IndexAddr, ChP->RxControl);
3064 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3065 out32(ChP->IndexAddr, ChP->TxControl);
3067 if (Flags & CHANINT_EN) {
3068 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3069 sOutB(ChP->IntMask, Mask);
3073 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3075 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3079 * Not an official SSCI function, but how to reset RocketModems.
3082 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3087 addr = CtlP->AiopIO[0] + 0x400;
3088 val = sInB(CtlP->MReg3IO);
3089 /* if AIOP[1] is not enabled, enable it */
3090 if ((val & 2) == 0) {
3091 val = sInB(CtlP->MReg2IO);
3092 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3093 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3099 sOutB(addr + chan, 0); /* apply or remove reset */
3104 * Not an official SSCI function, but how to reset RocketModems.
3107 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3111 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3114 sOutB(addr + chan, 0); /* apply or remove reset */
3117 /* Resets the speaker controller on RocketModem II and III devices */
3118 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3122 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3123 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3124 addr = CtlP->AiopIO[0] + 0x4F;
3128 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3129 if ((model == MODEL_UPCI_RM3_8PORT)
3130 || (model == MODEL_UPCI_RM3_4PORT)) {
3131 addr = CtlP->AiopIO[0] + 0x88;
3136 /* Returns the line number given the controller (board), aiop and channel number */
3137 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3139 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3143 * Stores the line number associated with a given controller (board), aiop
3144 * and channel number.
3145 * Returns: The line number assigned
3147 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3149 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3150 return (nextLineNumber - 1);