2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <linux/dma_remapping.h>
44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
45 static void intel_increase_pllclock(struct drm_crtc *crtc);
46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
69 #define INTEL_P2_NUM 2
70 typedef struct intel_limit intel_limit_t;
72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 * find_pll() - Find the best values for the PLL
76 * @limit: limits for the PLL
78 * @target: target frequency in kHz
79 * @refclk: reference clock frequency in kHz
80 * @match_clock: if provided, @best_clock P divider must
81 * match the P divider from @match_clock
82 * used for LVDS downclocking
83 * @best_clock: best PLL values found
85 * Returns true on success, false on failure.
87 bool (*find_pll)(const intel_limit_t *limit,
88 struct drm_crtc *crtc,
89 int target, int refclk,
90 intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
95 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
98 intel_pch_rawclk(struct drm_device *dev)
100 struct drm_i915_private *dev_priv = dev->dev_private;
102 WARN_ON(!HAS_PCH_SPLIT(dev));
104 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
108 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
109 int target, int refclk, intel_clock_t *match_clock,
110 intel_clock_t *best_clock);
112 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
113 int target, int refclk, intel_clock_t *match_clock,
114 intel_clock_t *best_clock);
117 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
118 int target, int refclk, intel_clock_t *match_clock,
119 intel_clock_t *best_clock);
121 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
122 int target, int refclk, intel_clock_t *match_clock,
123 intel_clock_t *best_clock);
126 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
127 int target, int refclk, intel_clock_t *match_clock,
128 intel_clock_t *best_clock);
130 static inline u32 /* units of 100MHz */
131 intel_fdi_link_freq(struct drm_device *dev)
134 struct drm_i915_private *dev_priv = dev->dev_private;
135 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
140 static const intel_limit_t intel_limits_i8xx_dvo = {
141 .dot = { .min = 25000, .max = 350000 },
142 .vco = { .min = 930000, .max = 1400000 },
143 .n = { .min = 3, .max = 16 },
144 .m = { .min = 96, .max = 140 },
145 .m1 = { .min = 18, .max = 26 },
146 .m2 = { .min = 6, .max = 16 },
147 .p = { .min = 4, .max = 128 },
148 .p1 = { .min = 2, .max = 33 },
149 .p2 = { .dot_limit = 165000,
150 .p2_slow = 4, .p2_fast = 2 },
151 .find_pll = intel_find_best_PLL,
154 static const intel_limit_t intel_limits_i8xx_lvds = {
155 .dot = { .min = 25000, .max = 350000 },
156 .vco = { .min = 930000, .max = 1400000 },
157 .n = { .min = 3, .max = 16 },
158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 1, .max = 6 },
163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 14, .p2_fast = 7 },
165 .find_pll = intel_find_best_PLL,
168 static const intel_limit_t intel_limits_i9xx_sdvo = {
169 .dot = { .min = 20000, .max = 400000 },
170 .vco = { .min = 1400000, .max = 2800000 },
171 .n = { .min = 1, .max = 6 },
172 .m = { .min = 70, .max = 120 },
173 .m1 = { .min = 8, .max = 18 },
174 .m2 = { .min = 3, .max = 7 },
175 .p = { .min = 5, .max = 80 },
176 .p1 = { .min = 1, .max = 8 },
177 .p2 = { .dot_limit = 200000,
178 .p2_slow = 10, .p2_fast = 5 },
179 .find_pll = intel_find_best_PLL,
182 static const intel_limit_t intel_limits_i9xx_lvds = {
183 .dot = { .min = 20000, .max = 400000 },
184 .vco = { .min = 1400000, .max = 2800000 },
185 .n = { .min = 1, .max = 6 },
186 .m = { .min = 70, .max = 120 },
187 .m1 = { .min = 8, .max = 18 },
188 .m2 = { .min = 3, .max = 7 },
189 .p = { .min = 7, .max = 98 },
190 .p1 = { .min = 1, .max = 8 },
191 .p2 = { .dot_limit = 112000,
192 .p2_slow = 14, .p2_fast = 7 },
193 .find_pll = intel_find_best_PLL,
197 static const intel_limit_t intel_limits_g4x_sdvo = {
198 .dot = { .min = 25000, .max = 270000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 17, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 10, .max = 30 },
205 .p1 = { .min = 1, .max = 3},
206 .p2 = { .dot_limit = 270000,
210 .find_pll = intel_g4x_find_best_PLL,
213 static const intel_limit_t intel_limits_g4x_hdmi = {
214 .dot = { .min = 22000, .max = 400000 },
215 .vco = { .min = 1750000, .max = 3500000},
216 .n = { .min = 1, .max = 4 },
217 .m = { .min = 104, .max = 138 },
218 .m1 = { .min = 16, .max = 23 },
219 .m2 = { .min = 5, .max = 11 },
220 .p = { .min = 5, .max = 80 },
221 .p1 = { .min = 1, .max = 8},
222 .p2 = { .dot_limit = 165000,
223 .p2_slow = 10, .p2_fast = 5 },
224 .find_pll = intel_g4x_find_best_PLL,
227 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
228 .dot = { .min = 20000, .max = 115000 },
229 .vco = { .min = 1750000, .max = 3500000 },
230 .n = { .min = 1, .max = 3 },
231 .m = { .min = 104, .max = 138 },
232 .m1 = { .min = 17, .max = 23 },
233 .m2 = { .min = 5, .max = 11 },
234 .p = { .min = 28, .max = 112 },
235 .p1 = { .min = 2, .max = 8 },
236 .p2 = { .dot_limit = 0,
237 .p2_slow = 14, .p2_fast = 14
239 .find_pll = intel_g4x_find_best_PLL,
242 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
243 .dot = { .min = 80000, .max = 224000 },
244 .vco = { .min = 1750000, .max = 3500000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 104, .max = 138 },
247 .m1 = { .min = 17, .max = 23 },
248 .m2 = { .min = 5, .max = 11 },
249 .p = { .min = 14, .max = 42 },
250 .p1 = { .min = 2, .max = 6 },
251 .p2 = { .dot_limit = 0,
252 .p2_slow = 7, .p2_fast = 7
254 .find_pll = intel_g4x_find_best_PLL,
257 static const intel_limit_t intel_limits_g4x_display_port = {
258 .dot = { .min = 161670, .max = 227000 },
259 .vco = { .min = 1750000, .max = 3500000},
260 .n = { .min = 1, .max = 2 },
261 .m = { .min = 97, .max = 108 },
262 .m1 = { .min = 0x10, .max = 0x12 },
263 .m2 = { .min = 0x05, .max = 0x06 },
264 .p = { .min = 10, .max = 20 },
265 .p1 = { .min = 1, .max = 2},
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 10, .p2_fast = 10 },
268 .find_pll = intel_find_pll_g4x_dp,
271 static const intel_limit_t intel_limits_pineview_sdvo = {
272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
274 /* Pineview's Ncounter is a ring counter */
275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
277 /* Pineview only has one combined m divider, which we treat as m2. */
278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
284 .find_pll = intel_find_best_PLL,
287 static const intel_limit_t intel_limits_pineview_lvds = {
288 .dot = { .min = 20000, .max = 400000 },
289 .vco = { .min = 1700000, .max = 3500000 },
290 .n = { .min = 3, .max = 6 },
291 .m = { .min = 2, .max = 256 },
292 .m1 = { .min = 0, .max = 0 },
293 .m2 = { .min = 0, .max = 254 },
294 .p = { .min = 7, .max = 112 },
295 .p1 = { .min = 1, .max = 8 },
296 .p2 = { .dot_limit = 112000,
297 .p2_slow = 14, .p2_fast = 14 },
298 .find_pll = intel_find_best_PLL,
301 /* Ironlake / Sandybridge
303 * We calculate clock using (register_value + 2) for N/M1/M2, so here
304 * the range value for them is (actual_value - 2).
306 static const intel_limit_t intel_limits_ironlake_dac = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 5 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 5, .max = 80 },
314 .p1 = { .min = 1, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 10, .p2_fast = 5 },
317 .find_pll = intel_g4x_find_best_PLL,
320 static const intel_limit_t intel_limits_ironlake_single_lvds = {
321 .dot = { .min = 25000, .max = 350000 },
322 .vco = { .min = 1760000, .max = 3510000 },
323 .n = { .min = 1, .max = 3 },
324 .m = { .min = 79, .max = 118 },
325 .m1 = { .min = 12, .max = 22 },
326 .m2 = { .min = 5, .max = 9 },
327 .p = { .min = 28, .max = 112 },
328 .p1 = { .min = 2, .max = 8 },
329 .p2 = { .dot_limit = 225000,
330 .p2_slow = 14, .p2_fast = 14 },
331 .find_pll = intel_g4x_find_best_PLL,
334 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
335 .dot = { .min = 25000, .max = 350000 },
336 .vco = { .min = 1760000, .max = 3510000 },
337 .n = { .min = 1, .max = 3 },
338 .m = { .min = 79, .max = 127 },
339 .m1 = { .min = 12, .max = 22 },
340 .m2 = { .min = 5, .max = 9 },
341 .p = { .min = 14, .max = 56 },
342 .p1 = { .min = 2, .max = 8 },
343 .p2 = { .dot_limit = 225000,
344 .p2_slow = 7, .p2_fast = 7 },
345 .find_pll = intel_g4x_find_best_PLL,
348 /* LVDS 100mhz refclk limits. */
349 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
357 .p1 = { .min = 2, .max = 8 },
358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
360 .find_pll = intel_g4x_find_best_PLL,
363 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
371 .p1 = { .min = 2, .max = 6 },
372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
374 .find_pll = intel_g4x_find_best_PLL,
377 static const intel_limit_t intel_limits_ironlake_display_port = {
378 .dot = { .min = 25000, .max = 350000 },
379 .vco = { .min = 1760000, .max = 3510000},
380 .n = { .min = 1, .max = 2 },
381 .m = { .min = 81, .max = 90 },
382 .m1 = { .min = 12, .max = 22 },
383 .m2 = { .min = 5, .max = 9 },
384 .p = { .min = 10, .max = 20 },
385 .p1 = { .min = 1, .max = 2},
386 .p2 = { .dot_limit = 0,
387 .p2_slow = 10, .p2_fast = 10 },
388 .find_pll = intel_find_pll_ironlake_dp,
391 static const intel_limit_t intel_limits_vlv_dac = {
392 .dot = { .min = 25000, .max = 270000 },
393 .vco = { .min = 4000000, .max = 6000000 },
394 .n = { .min = 1, .max = 7 },
395 .m = { .min = 22, .max = 450 }, /* guess */
396 .m1 = { .min = 2, .max = 3 },
397 .m2 = { .min = 11, .max = 156 },
398 .p = { .min = 10, .max = 30 },
399 .p1 = { .min = 1, .max = 3 },
400 .p2 = { .dot_limit = 270000,
401 .p2_slow = 2, .p2_fast = 20 },
402 .find_pll = intel_vlv_find_best_pll,
405 static const intel_limit_t intel_limits_vlv_hdmi = {
406 .dot = { .min = 25000, .max = 270000 },
407 .vco = { .min = 4000000, .max = 6000000 },
408 .n = { .min = 1, .max = 7 },
409 .m = { .min = 60, .max = 300 }, /* guess */
410 .m1 = { .min = 2, .max = 3 },
411 .m2 = { .min = 11, .max = 156 },
412 .p = { .min = 10, .max = 30 },
413 .p1 = { .min = 2, .max = 3 },
414 .p2 = { .dot_limit = 270000,
415 .p2_slow = 2, .p2_fast = 20 },
416 .find_pll = intel_vlv_find_best_pll,
419 static const intel_limit_t intel_limits_vlv_dp = {
420 .dot = { .min = 25000, .max = 270000 },
421 .vco = { .min = 4000000, .max = 6000000 },
422 .n = { .min = 1, .max = 7 },
423 .m = { .min = 22, .max = 450 },
424 .m1 = { .min = 2, .max = 3 },
425 .m2 = { .min = 11, .max = 156 },
426 .p = { .min = 10, .max = 30 },
427 .p1 = { .min = 1, .max = 3 },
428 .p2 = { .dot_limit = 270000,
429 .p2_slow = 2, .p2_fast = 20 },
430 .find_pll = intel_vlv_find_best_pll,
433 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
435 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
437 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
438 DRM_ERROR("DPIO idle wait timed out\n");
442 I915_WRITE(DPIO_REG, reg);
443 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
445 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
446 DRM_ERROR("DPIO read wait timed out\n");
450 return I915_READ(DPIO_DATA);
453 void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
455 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
457 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
458 DRM_ERROR("DPIO idle wait timed out\n");
462 I915_WRITE(DPIO_DATA, val);
463 I915_WRITE(DPIO_REG, reg);
464 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
466 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
467 DRM_ERROR("DPIO write wait timed out\n");
470 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
473 struct drm_device *dev = crtc->dev;
474 const intel_limit_t *limit;
476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
477 if (intel_is_dual_link_lvds(dev)) {
478 if (refclk == 100000)
479 limit = &intel_limits_ironlake_dual_lvds_100m;
481 limit = &intel_limits_ironlake_dual_lvds;
483 if (refclk == 100000)
484 limit = &intel_limits_ironlake_single_lvds_100m;
486 limit = &intel_limits_ironlake_single_lvds;
488 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
489 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
490 limit = &intel_limits_ironlake_display_port;
492 limit = &intel_limits_ironlake_dac;
497 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
499 struct drm_device *dev = crtc->dev;
500 const intel_limit_t *limit;
502 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
503 if (intel_is_dual_link_lvds(dev))
504 limit = &intel_limits_g4x_dual_channel_lvds;
506 limit = &intel_limits_g4x_single_channel_lvds;
507 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
508 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
509 limit = &intel_limits_g4x_hdmi;
510 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
511 limit = &intel_limits_g4x_sdvo;
512 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
513 limit = &intel_limits_g4x_display_port;
514 } else /* The option is for other outputs */
515 limit = &intel_limits_i9xx_sdvo;
520 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
522 struct drm_device *dev = crtc->dev;
523 const intel_limit_t *limit;
525 if (HAS_PCH_SPLIT(dev))
526 limit = intel_ironlake_limit(crtc, refclk);
527 else if (IS_G4X(dev)) {
528 limit = intel_g4x_limit(crtc);
529 } else if (IS_PINEVIEW(dev)) {
530 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
531 limit = &intel_limits_pineview_lvds;
533 limit = &intel_limits_pineview_sdvo;
534 } else if (IS_VALLEYVIEW(dev)) {
535 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
536 limit = &intel_limits_vlv_dac;
537 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
538 limit = &intel_limits_vlv_hdmi;
540 limit = &intel_limits_vlv_dp;
541 } else if (!IS_GEN2(dev)) {
542 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
543 limit = &intel_limits_i9xx_lvds;
545 limit = &intel_limits_i9xx_sdvo;
547 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
548 limit = &intel_limits_i8xx_lvds;
550 limit = &intel_limits_i8xx_dvo;
555 /* m1 is reserved as 0 in Pineview, n is a ring counter */
556 static void pineview_clock(int refclk, intel_clock_t *clock)
558 clock->m = clock->m2 + 2;
559 clock->p = clock->p1 * clock->p2;
560 clock->vco = refclk * clock->m / clock->n;
561 clock->dot = clock->vco / clock->p;
564 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
566 if (IS_PINEVIEW(dev)) {
567 pineview_clock(refclk, clock);
570 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
571 clock->p = clock->p1 * clock->p2;
572 clock->vco = refclk * clock->m / (clock->n + 2);
573 clock->dot = clock->vco / clock->p;
577 * Returns whether any output on the specified pipe is of the specified type
579 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
581 struct drm_device *dev = crtc->dev;
582 struct intel_encoder *encoder;
584 for_each_encoder_on_crtc(dev, crtc, encoder)
585 if (encoder->type == type)
591 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
593 * Returns whether the given set of divisors are valid for a given refclk with
594 * the given connectors.
597 static bool intel_PLL_is_valid(struct drm_device *dev,
598 const intel_limit_t *limit,
599 const intel_clock_t *clock)
601 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
602 INTELPllInvalid("p1 out of range\n");
603 if (clock->p < limit->p.min || limit->p.max < clock->p)
604 INTELPllInvalid("p out of range\n");
605 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
606 INTELPllInvalid("m2 out of range\n");
607 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
608 INTELPllInvalid("m1 out of range\n");
609 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
610 INTELPllInvalid("m1 <= m2\n");
611 if (clock->m < limit->m.min || limit->m.max < clock->m)
612 INTELPllInvalid("m out of range\n");
613 if (clock->n < limit->n.min || limit->n.max < clock->n)
614 INTELPllInvalid("n out of range\n");
615 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
616 INTELPllInvalid("vco out of range\n");
617 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
618 * connector, etc., rather than just a single range.
620 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
621 INTELPllInvalid("dot out of range\n");
627 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
628 int target, int refclk, intel_clock_t *match_clock,
629 intel_clock_t *best_clock)
632 struct drm_device *dev = crtc->dev;
636 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
638 * For LVDS just rely on its current settings for dual-channel.
639 * We haven't figured out how to reliably set up different
640 * single/dual channel state, if we even can.
642 if (intel_is_dual_link_lvds(dev))
643 clock.p2 = limit->p2.p2_fast;
645 clock.p2 = limit->p2.p2_slow;
647 if (target < limit->p2.dot_limit)
648 clock.p2 = limit->p2.p2_slow;
650 clock.p2 = limit->p2.p2_fast;
653 memset(best_clock, 0, sizeof(*best_clock));
655 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
657 for (clock.m2 = limit->m2.min;
658 clock.m2 <= limit->m2.max; clock.m2++) {
659 /* m1 is always 0 in Pineview */
660 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
662 for (clock.n = limit->n.min;
663 clock.n <= limit->n.max; clock.n++) {
664 for (clock.p1 = limit->p1.min;
665 clock.p1 <= limit->p1.max; clock.p1++) {
668 intel_clock(dev, refclk, &clock);
669 if (!intel_PLL_is_valid(dev, limit,
673 clock.p != match_clock->p)
676 this_err = abs(clock.dot - target);
677 if (this_err < err) {
686 return (err != target);
690 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
691 int target, int refclk, intel_clock_t *match_clock,
692 intel_clock_t *best_clock)
694 struct drm_device *dev = crtc->dev;
698 /* approximately equals target * 0.00585 */
699 int err_most = (target >> 8) + (target >> 9);
702 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
705 if (HAS_PCH_SPLIT(dev))
709 if (intel_is_dual_link_lvds(dev))
710 clock.p2 = limit->p2.p2_fast;
712 clock.p2 = limit->p2.p2_slow;
714 if (target < limit->p2.dot_limit)
715 clock.p2 = limit->p2.p2_slow;
717 clock.p2 = limit->p2.p2_fast;
720 memset(best_clock, 0, sizeof(*best_clock));
721 max_n = limit->n.max;
722 /* based on hardware requirement, prefer smaller n to precision */
723 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
724 /* based on hardware requirement, prefere larger m1,m2 */
725 for (clock.m1 = limit->m1.max;
726 clock.m1 >= limit->m1.min; clock.m1--) {
727 for (clock.m2 = limit->m2.max;
728 clock.m2 >= limit->m2.min; clock.m2--) {
729 for (clock.p1 = limit->p1.max;
730 clock.p1 >= limit->p1.min; clock.p1--) {
733 intel_clock(dev, refclk, &clock);
734 if (!intel_PLL_is_valid(dev, limit,
738 clock.p != match_clock->p)
741 this_err = abs(clock.dot - target);
742 if (this_err < err_most) {
756 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
757 int target, int refclk, intel_clock_t *match_clock,
758 intel_clock_t *best_clock)
760 struct drm_device *dev = crtc->dev;
763 if (target < 200000) {
776 intel_clock(dev, refclk, &clock);
777 memcpy(best_clock, &clock, sizeof(intel_clock_t));
781 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
783 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
784 int target, int refclk, intel_clock_t *match_clock,
785 intel_clock_t *best_clock)
788 if (target < 200000) {
801 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
802 clock.p = (clock.p1 * clock.p2);
803 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
805 memcpy(best_clock, &clock, sizeof(intel_clock_t));
809 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
813 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
815 u32 updrate, minupdate, fracbits, p;
816 unsigned long bestppm, ppm, absppm;
820 dotclk = target * 1000;
823 fastclk = dotclk / (2*100);
827 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
828 bestm1 = bestm2 = bestp1 = bestp2 = 0;
830 /* based on hardware requirement, prefer smaller n to precision */
831 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
832 updrate = refclk / n;
833 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
834 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
838 /* based on hardware requirement, prefer bigger m1,m2 values */
839 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
840 m2 = (((2*(fastclk * p * n / m1 )) +
841 refclk) / (2*refclk));
844 if (vco >= limit->vco.min && vco < limit->vco.max) {
845 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
846 absppm = (ppm > 0) ? ppm : (-ppm);
847 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
851 if (absppm < bestppm - 10) {
868 best_clock->n = bestn;
869 best_clock->m1 = bestm1;
870 best_clock->m2 = bestm2;
871 best_clock->p1 = bestp1;
872 best_clock->p2 = bestp2;
877 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
880 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
883 return intel_crtc->config.cpu_transcoder;
886 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
888 struct drm_i915_private *dev_priv = dev->dev_private;
889 u32 frame, frame_reg = PIPEFRAME(pipe);
891 frame = I915_READ(frame_reg);
893 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
894 DRM_DEBUG_KMS("vblank wait timed out\n");
898 * intel_wait_for_vblank - wait for vblank on a given pipe
900 * @pipe: pipe to wait for
902 * Wait for vblank to occur on a given pipe. Needed for various bits of
905 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
907 struct drm_i915_private *dev_priv = dev->dev_private;
908 int pipestat_reg = PIPESTAT(pipe);
910 if (INTEL_INFO(dev)->gen >= 5) {
911 ironlake_wait_for_vblank(dev, pipe);
915 /* Clear existing vblank status. Note this will clear any other
916 * sticky status fields as well.
918 * This races with i915_driver_irq_handler() with the result
919 * that either function could miss a vblank event. Here it is not
920 * fatal, as we will either wait upon the next vblank interrupt or
921 * timeout. Generally speaking intel_wait_for_vblank() is only
922 * called during modeset at which time the GPU should be idle and
923 * should *not* be performing page flips and thus not waiting on
925 * Currently, the result of us stealing a vblank from the irq
926 * handler is that a single frame will be skipped during swapbuffers.
928 I915_WRITE(pipestat_reg,
929 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
931 /* Wait for vblank interrupt bit to set */
932 if (wait_for(I915_READ(pipestat_reg) &
933 PIPE_VBLANK_INTERRUPT_STATUS,
935 DRM_DEBUG_KMS("vblank wait timed out\n");
939 * intel_wait_for_pipe_off - wait for pipe to turn off
941 * @pipe: pipe to wait for
943 * After disabling a pipe, we can't wait for vblank in the usual way,
944 * spinning on the vblank interrupt status bit, since we won't actually
945 * see an interrupt when the pipe is disabled.
948 * wait for the pipe register state bit to turn off
951 * wait for the display line value to settle (it usually
952 * ends up stopping at the start of the next frame).
955 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
957 struct drm_i915_private *dev_priv = dev->dev_private;
958 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
961 if (INTEL_INFO(dev)->gen >= 4) {
962 int reg = PIPECONF(cpu_transcoder);
964 /* Wait for the Pipe State to go off */
965 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
967 WARN(1, "pipe_off wait timed out\n");
969 u32 last_line, line_mask;
970 int reg = PIPEDSL(pipe);
971 unsigned long timeout = jiffies + msecs_to_jiffies(100);
974 line_mask = DSL_LINEMASK_GEN2;
976 line_mask = DSL_LINEMASK_GEN3;
978 /* Wait for the display line to settle */
980 last_line = I915_READ(reg) & line_mask;
982 } while (((I915_READ(reg) & line_mask) != last_line) &&
983 time_after(timeout, jiffies));
984 if (time_after(jiffies, timeout))
985 WARN(1, "pipe_off wait timed out\n");
990 * ibx_digital_port_connected - is the specified port connected?
991 * @dev_priv: i915 private structure
992 * @port: the port to test
994 * Returns true if @port is connected, false otherwise.
996 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
997 struct intel_digital_port *port)
1001 if (HAS_PCH_IBX(dev_priv->dev)) {
1002 switch(port->port) {
1004 bit = SDE_PORTB_HOTPLUG;
1007 bit = SDE_PORTC_HOTPLUG;
1010 bit = SDE_PORTD_HOTPLUG;
1016 switch(port->port) {
1018 bit = SDE_PORTB_HOTPLUG_CPT;
1021 bit = SDE_PORTC_HOTPLUG_CPT;
1024 bit = SDE_PORTD_HOTPLUG_CPT;
1031 return I915_READ(SDEISR) & bit;
1034 static const char *state_string(bool enabled)
1036 return enabled ? "on" : "off";
1039 /* Only for pre-ILK configs */
1040 static void assert_pll(struct drm_i915_private *dev_priv,
1041 enum pipe pipe, bool state)
1048 val = I915_READ(reg);
1049 cur_state = !!(val & DPLL_VCO_ENABLE);
1050 WARN(cur_state != state,
1051 "PLL state assertion failure (expected %s, current %s)\n",
1052 state_string(state), state_string(cur_state));
1054 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1055 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1058 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1059 struct intel_pch_pll *pll,
1060 struct intel_crtc *crtc,
1066 if (HAS_PCH_LPT(dev_priv->dev)) {
1067 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1072 "asserting PCH PLL %s with no PLL\n", state_string(state)))
1075 val = I915_READ(pll->pll_reg);
1076 cur_state = !!(val & DPLL_VCO_ENABLE);
1077 WARN(cur_state != state,
1078 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1079 pll->pll_reg, state_string(state), state_string(cur_state), val);
1081 /* Make sure the selected PLL is correctly attached to the transcoder */
1082 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1085 pch_dpll = I915_READ(PCH_DPLL_SEL);
1086 cur_state = pll->pll_reg == _PCH_DPLL_B;
1087 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1088 "PLL[%d] not attached to this transcoder %c: %08x\n",
1089 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
1090 cur_state = !!(val >> (4*crtc->pipe + 3));
1091 WARN(cur_state != state,
1092 "PLL[%d] not %s on this transcoder %c: %08x\n",
1093 pll->pll_reg == _PCH_DPLL_B,
1094 state_string(state),
1095 pipe_name(crtc->pipe),
1100 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1101 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1103 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1104 enum pipe pipe, bool state)
1109 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1112 if (HAS_DDI(dev_priv->dev)) {
1113 /* DDI does not have a specific FDI_TX register */
1114 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1115 val = I915_READ(reg);
1116 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1118 reg = FDI_TX_CTL(pipe);
1119 val = I915_READ(reg);
1120 cur_state = !!(val & FDI_TX_ENABLE);
1122 WARN(cur_state != state,
1123 "FDI TX state assertion failure (expected %s, current %s)\n",
1124 state_string(state), state_string(cur_state));
1126 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1127 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1129 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1130 enum pipe pipe, bool state)
1136 reg = FDI_RX_CTL(pipe);
1137 val = I915_READ(reg);
1138 cur_state = !!(val & FDI_RX_ENABLE);
1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (HAS_DDI(dev_priv->dev))
1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1171 reg = FDI_RX_CTL(pipe);
1172 val = I915_READ(reg);
1173 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1176 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1179 int pp_reg, lvds_reg;
1181 enum pipe panel_pipe = PIPE_A;
1184 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1185 pp_reg = PCH_PP_CONTROL;
1186 lvds_reg = PCH_LVDS;
1188 pp_reg = PP_CONTROL;
1192 val = I915_READ(pp_reg);
1193 if (!(val & PANEL_POWER_ON) ||
1194 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1197 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1198 panel_pipe = PIPE_B;
1200 WARN(panel_pipe == pipe && locked,
1201 "panel assertion failure, pipe %c regs locked\n",
1205 void assert_pipe(struct drm_i915_private *dev_priv,
1206 enum pipe pipe, bool state)
1211 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1214 /* if we need the pipe A quirk it must be always on */
1215 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 if (!intel_using_power_well(dev_priv->dev) &&
1219 cpu_transcoder != TRANSCODER_EDP) {
1222 reg = PIPECONF(cpu_transcoder);
1223 val = I915_READ(reg);
1224 cur_state = !!(val & PIPECONF_ENABLE);
1227 WARN(cur_state != state,
1228 "pipe %c assertion failure (expected %s, current %s)\n",
1229 pipe_name(pipe), state_string(state), state_string(cur_state));
1232 static void assert_plane(struct drm_i915_private *dev_priv,
1233 enum plane plane, bool state)
1239 reg = DSPCNTR(plane);
1240 val = I915_READ(reg);
1241 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1242 WARN(cur_state != state,
1243 "plane %c assertion failure (expected %s, current %s)\n",
1244 plane_name(plane), state_string(state), state_string(cur_state));
1247 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1248 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1250 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1257 /* Planes are fixed to pipes on ILK+ */
1258 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1259 reg = DSPCNTR(pipe);
1260 val = I915_READ(reg);
1261 WARN((val & DISPLAY_PLANE_ENABLE),
1262 "plane %c assertion failure, should be disabled but not\n",
1267 /* Need to check both planes against the pipe */
1268 for (i = 0; i < 2; i++) {
1270 val = I915_READ(reg);
1271 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1272 DISPPLANE_SEL_PIPE_SHIFT;
1273 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1274 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1275 plane_name(i), pipe_name(pipe));
1279 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1285 if (!IS_VALLEYVIEW(dev_priv->dev))
1288 /* Need to check both planes against the pipe */
1289 for (i = 0; i < dev_priv->num_plane; i++) {
1290 reg = SPCNTR(pipe, i);
1291 val = I915_READ(reg);
1292 WARN((val & SP_ENABLE),
1293 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1294 sprite_name(pipe, i), pipe_name(pipe));
1298 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1303 if (HAS_PCH_LPT(dev_priv->dev)) {
1304 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1308 val = I915_READ(PCH_DREF_CONTROL);
1309 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1310 DREF_SUPERSPREAD_SOURCE_MASK));
1311 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1314 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1321 reg = TRANSCONF(pipe);
1322 val = I915_READ(reg);
1323 enabled = !!(val & TRANS_ENABLE);
1325 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1329 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1330 enum pipe pipe, u32 port_sel, u32 val)
1332 if ((val & DP_PORT_EN) == 0)
1335 if (HAS_PCH_CPT(dev_priv->dev)) {
1336 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1337 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1338 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1341 if ((val & DP_PIPE_MASK) != (pipe << 30))
1347 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1348 enum pipe pipe, u32 val)
1350 if ((val & SDVO_ENABLE) == 0)
1353 if (HAS_PCH_CPT(dev_priv->dev)) {
1354 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1357 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1363 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe, u32 val)
1366 if ((val & LVDS_PORT_EN) == 0)
1369 if (HAS_PCH_CPT(dev_priv->dev)) {
1370 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1373 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1379 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1380 enum pipe pipe, u32 val)
1382 if ((val & ADPA_DAC_ENABLE) == 0)
1384 if (HAS_PCH_CPT(dev_priv->dev)) {
1385 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1388 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1394 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1395 enum pipe pipe, int reg, u32 port_sel)
1397 u32 val = I915_READ(reg);
1398 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1399 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1400 reg, pipe_name(pipe));
1402 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1403 && (val & DP_PIPEB_SELECT),
1404 "IBX PCH dp port still using transcoder B\n");
1407 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1408 enum pipe pipe, int reg)
1410 u32 val = I915_READ(reg);
1411 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1412 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1413 reg, pipe_name(pipe));
1415 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1416 && (val & SDVO_PIPE_B_SELECT),
1417 "IBX PCH hdmi port still using transcoder B\n");
1420 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1426 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1427 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1428 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1431 val = I915_READ(reg);
1432 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1433 "PCH VGA enabled on transcoder %c, should be disabled\n",
1437 val = I915_READ(reg);
1438 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1439 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1442 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1443 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1444 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1448 * intel_enable_pll - enable a PLL
1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to enable
1452 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1453 * make sure the PLL reg is writable first though, since the panel write
1454 * protect mechanism may be enabled.
1456 * Note! This is for pre-ILK only.
1458 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1460 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1465 assert_pipe_disabled(dev_priv, pipe);
1467 /* No really, not for ILK+ */
1468 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1470 /* PLL is protected by panel, make sure we can write it */
1471 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1472 assert_panel_unlocked(dev_priv, pipe);
1475 val = I915_READ(reg);
1476 val |= DPLL_VCO_ENABLE;
1478 /* We do this three times for luck */
1479 I915_WRITE(reg, val);
1481 udelay(150); /* wait for warmup */
1482 I915_WRITE(reg, val);
1484 udelay(150); /* wait for warmup */
1485 I915_WRITE(reg, val);
1487 udelay(150); /* wait for warmup */
1491 * intel_disable_pll - disable a PLL
1492 * @dev_priv: i915 private structure
1493 * @pipe: pipe PLL to disable
1495 * Disable the PLL for @pipe, making sure the pipe is off first.
1497 * Note! This is for pre-ILK only.
1499 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1504 /* Don't disable pipe A or pipe A PLLs if needed */
1505 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1508 /* Make sure the pipe isn't still relying on us */
1509 assert_pipe_disabled(dev_priv, pipe);
1512 val = I915_READ(reg);
1513 val &= ~DPLL_VCO_ENABLE;
1514 I915_WRITE(reg, val);
1520 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1521 enum intel_sbi_destination destination)
1525 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1527 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1529 DRM_ERROR("timeout waiting for SBI to become ready\n");
1533 I915_WRITE(SBI_ADDR, (reg << 16));
1534 I915_WRITE(SBI_DATA, value);
1536 if (destination == SBI_ICLK)
1537 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1539 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1540 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1542 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1544 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1550 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1551 enum intel_sbi_destination destination)
1554 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1556 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1558 DRM_ERROR("timeout waiting for SBI to become ready\n");
1562 I915_WRITE(SBI_ADDR, (reg << 16));
1564 if (destination == SBI_ICLK)
1565 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1567 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1568 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1570 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1572 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1576 return I915_READ(SBI_DATA);
1579 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1584 port_mask = DPLL_PORTB_READY_MASK;
1586 port_mask = DPLL_PORTC_READY_MASK;
1588 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1589 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1590 'B' + port, I915_READ(DPLL(0)));
1594 * ironlake_enable_pch_pll - enable PCH PLL
1595 * @dev_priv: i915 private structure
1596 * @pipe: pipe PLL to enable
1598 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1599 * drives the transcoder clock.
1601 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1603 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1604 struct intel_pch_pll *pll;
1608 /* PCH PLLs only available on ILK, SNB and IVB */
1609 BUG_ON(dev_priv->info->gen < 5);
1610 pll = intel_crtc->pch_pll;
1614 if (WARN_ON(pll->refcount == 0))
1617 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
1621 /* PCH refclock must be enabled first */
1622 assert_pch_refclk_enabled(dev_priv);
1624 if (pll->active++ && pll->on) {
1625 assert_pch_pll_enabled(dev_priv, pll, NULL);
1629 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1632 val = I915_READ(reg);
1633 val |= DPLL_VCO_ENABLE;
1634 I915_WRITE(reg, val);
1641 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1643 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1644 struct intel_pch_pll *pll = intel_crtc->pch_pll;
1648 /* PCH only available on ILK+ */
1649 BUG_ON(dev_priv->info->gen < 5);
1653 if (WARN_ON(pll->refcount == 0))
1656 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1657 pll->pll_reg, pll->active, pll->on,
1658 intel_crtc->base.base.id);
1660 if (WARN_ON(pll->active == 0)) {
1661 assert_pch_pll_disabled(dev_priv, pll, NULL);
1665 if (--pll->active) {
1666 assert_pch_pll_enabled(dev_priv, pll, NULL);
1670 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1672 /* Make sure transcoder isn't still depending on us */
1673 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1676 val = I915_READ(reg);
1677 val &= ~DPLL_VCO_ENABLE;
1678 I915_WRITE(reg, val);
1685 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1688 struct drm_device *dev = dev_priv->dev;
1689 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1690 uint32_t reg, val, pipeconf_val;
1692 /* PCH only available on ILK+ */
1693 BUG_ON(dev_priv->info->gen < 5);
1695 /* Make sure PCH DPLL is enabled */
1696 assert_pch_pll_enabled(dev_priv,
1697 to_intel_crtc(crtc)->pch_pll,
1698 to_intel_crtc(crtc));
1700 /* FDI must be feeding us bits for PCH ports */
1701 assert_fdi_tx_enabled(dev_priv, pipe);
1702 assert_fdi_rx_enabled(dev_priv, pipe);
1704 if (HAS_PCH_CPT(dev)) {
1705 /* Workaround: Set the timing override bit before enabling the
1706 * pch transcoder. */
1707 reg = TRANS_CHICKEN2(pipe);
1708 val = I915_READ(reg);
1709 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1710 I915_WRITE(reg, val);
1713 reg = TRANSCONF(pipe);
1714 val = I915_READ(reg);
1715 pipeconf_val = I915_READ(PIPECONF(pipe));
1717 if (HAS_PCH_IBX(dev_priv->dev)) {
1719 * make the BPC in transcoder be consistent with
1720 * that in pipeconf reg.
1722 val &= ~PIPECONF_BPC_MASK;
1723 val |= pipeconf_val & PIPECONF_BPC_MASK;
1726 val &= ~TRANS_INTERLACE_MASK;
1727 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1728 if (HAS_PCH_IBX(dev_priv->dev) &&
1729 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1730 val |= TRANS_LEGACY_INTERLACED_ILK;
1732 val |= TRANS_INTERLACED;
1734 val |= TRANS_PROGRESSIVE;
1736 I915_WRITE(reg, val | TRANS_ENABLE);
1737 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1738 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1741 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1742 enum transcoder cpu_transcoder)
1744 u32 val, pipeconf_val;
1746 /* PCH only available on ILK+ */
1747 BUG_ON(dev_priv->info->gen < 5);
1749 /* FDI must be feeding us bits for PCH ports */
1750 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1751 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1753 /* Workaround: set timing override bit. */
1754 val = I915_READ(_TRANSA_CHICKEN2);
1755 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1756 I915_WRITE(_TRANSA_CHICKEN2, val);
1759 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1761 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1762 PIPECONF_INTERLACED_ILK)
1763 val |= TRANS_INTERLACED;
1765 val |= TRANS_PROGRESSIVE;
1767 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1768 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1769 DRM_ERROR("Failed to enable PCH transcoder\n");
1772 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1775 struct drm_device *dev = dev_priv->dev;
1778 /* FDI relies on the transcoder */
1779 assert_fdi_tx_disabled(dev_priv, pipe);
1780 assert_fdi_rx_disabled(dev_priv, pipe);
1782 /* Ports must be off as well */
1783 assert_pch_ports_disabled(dev_priv, pipe);
1785 reg = TRANSCONF(pipe);
1786 val = I915_READ(reg);
1787 val &= ~TRANS_ENABLE;
1788 I915_WRITE(reg, val);
1789 /* wait for PCH transcoder off, transcoder state */
1790 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1791 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1793 if (!HAS_PCH_IBX(dev)) {
1794 /* Workaround: Clear the timing override chicken bit again. */
1795 reg = TRANS_CHICKEN2(pipe);
1796 val = I915_READ(reg);
1797 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1798 I915_WRITE(reg, val);
1802 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1806 val = I915_READ(_TRANSACONF);
1807 val &= ~TRANS_ENABLE;
1808 I915_WRITE(_TRANSACONF, val);
1809 /* wait for PCH transcoder off, transcoder state */
1810 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1811 DRM_ERROR("Failed to disable PCH transcoder\n");
1813 /* Workaround: clear timing override bit. */
1814 val = I915_READ(_TRANSA_CHICKEN2);
1815 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1816 I915_WRITE(_TRANSA_CHICKEN2, val);
1820 * intel_enable_pipe - enable a pipe, asserting requirements
1821 * @dev_priv: i915 private structure
1822 * @pipe: pipe to enable
1823 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1825 * Enable @pipe, making sure that various hardware specific requirements
1826 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1828 * @pipe should be %PIPE_A or %PIPE_B.
1830 * Will wait until the pipe is actually running (i.e. first vblank) before
1833 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1836 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1838 enum pipe pch_transcoder;
1842 assert_planes_disabled(dev_priv, pipe);
1843 assert_sprites_disabled(dev_priv, pipe);
1845 if (HAS_PCH_LPT(dev_priv->dev))
1846 pch_transcoder = TRANSCODER_A;
1848 pch_transcoder = pipe;
1851 * A pipe without a PLL won't actually be able to drive bits from
1852 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1855 if (!HAS_PCH_SPLIT(dev_priv->dev))
1856 assert_pll_enabled(dev_priv, pipe);
1859 /* if driving the PCH, we need FDI enabled */
1860 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1861 assert_fdi_tx_pll_enabled(dev_priv,
1862 (enum pipe) cpu_transcoder);
1864 /* FIXME: assert CPU port conditions for SNB+ */
1867 reg = PIPECONF(cpu_transcoder);
1868 val = I915_READ(reg);
1869 if (val & PIPECONF_ENABLE)
1872 I915_WRITE(reg, val | PIPECONF_ENABLE);
1873 intel_wait_for_vblank(dev_priv->dev, pipe);
1877 * intel_disable_pipe - disable a pipe, asserting requirements
1878 * @dev_priv: i915 private structure
1879 * @pipe: pipe to disable
1881 * Disable @pipe, making sure that various hardware specific requirements
1882 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1884 * @pipe should be %PIPE_A or %PIPE_B.
1886 * Will wait until the pipe has shut down before returning.
1888 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1891 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1897 * Make sure planes won't keep trying to pump pixels to us,
1898 * or we might hang the display.
1900 assert_planes_disabled(dev_priv, pipe);
1901 assert_sprites_disabled(dev_priv, pipe);
1903 /* Don't disable pipe A or pipe A PLLs if needed */
1904 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1907 reg = PIPECONF(cpu_transcoder);
1908 val = I915_READ(reg);
1909 if ((val & PIPECONF_ENABLE) == 0)
1912 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1913 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1917 * Plane regs are double buffered, going from enabled->disabled needs a
1918 * trigger in order to latch. The display address reg provides this.
1920 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1923 if (dev_priv->info->gen >= 4)
1924 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1926 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1930 * intel_enable_plane - enable a display plane on a given pipe
1931 * @dev_priv: i915 private structure
1932 * @plane: plane to enable
1933 * @pipe: pipe being fed
1935 * Enable @plane on @pipe, making sure that @pipe is running first.
1937 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1938 enum plane plane, enum pipe pipe)
1943 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1944 assert_pipe_enabled(dev_priv, pipe);
1946 reg = DSPCNTR(plane);
1947 val = I915_READ(reg);
1948 if (val & DISPLAY_PLANE_ENABLE)
1951 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1952 intel_flush_display_plane(dev_priv, plane);
1953 intel_wait_for_vblank(dev_priv->dev, pipe);
1957 * intel_disable_plane - disable a display plane
1958 * @dev_priv: i915 private structure
1959 * @plane: plane to disable
1960 * @pipe: pipe consuming the data
1962 * Disable @plane; should be an independent operation.
1964 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1965 enum plane plane, enum pipe pipe)
1970 reg = DSPCNTR(plane);
1971 val = I915_READ(reg);
1972 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1975 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1976 intel_flush_display_plane(dev_priv, plane);
1977 intel_wait_for_vblank(dev_priv->dev, pipe);
1980 static bool need_vtd_wa(struct drm_device *dev)
1982 #ifdef CONFIG_INTEL_IOMMU
1983 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1990 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1991 struct drm_i915_gem_object *obj,
1992 struct intel_ring_buffer *pipelined)
1994 struct drm_i915_private *dev_priv = dev->dev_private;
1998 switch (obj->tiling_mode) {
1999 case I915_TILING_NONE:
2000 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2001 alignment = 128 * 1024;
2002 else if (INTEL_INFO(dev)->gen >= 4)
2003 alignment = 4 * 1024;
2005 alignment = 64 * 1024;
2008 /* pin() will align the object as required by fence */
2012 /* Despite that we check this in framebuffer_init userspace can
2013 * screw us over and change the tiling after the fact. Only
2014 * pinned buffers can't change their tiling. */
2015 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
2021 /* Note that the w/a also requires 64 PTE of padding following the
2022 * bo. We currently fill all unused PTE with the shadow page and so
2023 * we should always have valid PTE following the scanout preventing
2026 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2027 alignment = 256 * 1024;
2029 dev_priv->mm.interruptible = false;
2030 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2032 goto err_interruptible;
2034 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2035 * fence, whereas 965+ only requires a fence if using
2036 * framebuffer compression. For simplicity, we always install
2037 * a fence as the cost is not that onerous.
2039 ret = i915_gem_object_get_fence(obj);
2043 i915_gem_object_pin_fence(obj);
2045 dev_priv->mm.interruptible = true;
2049 i915_gem_object_unpin(obj);
2051 dev_priv->mm.interruptible = true;
2055 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2057 i915_gem_object_unpin_fence(obj);
2058 i915_gem_object_unpin(obj);
2061 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2062 * is assumed to be a power-of-two. */
2063 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2064 unsigned int tiling_mode,
2068 if (tiling_mode != I915_TILING_NONE) {
2069 unsigned int tile_rows, tiles;
2074 tiles = *x / (512/cpp);
2077 return tile_rows * pitch * 8 + tiles * 4096;
2079 unsigned int offset;
2081 offset = *y * pitch + *x * cpp;
2083 *x = (offset & 4095) / cpp;
2084 return offset & -4096;
2088 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2091 struct drm_device *dev = crtc->dev;
2092 struct drm_i915_private *dev_priv = dev->dev_private;
2093 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2094 struct intel_framebuffer *intel_fb;
2095 struct drm_i915_gem_object *obj;
2096 int plane = intel_crtc->plane;
2097 unsigned long linear_offset;
2106 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2110 intel_fb = to_intel_framebuffer(fb);
2111 obj = intel_fb->obj;
2113 reg = DSPCNTR(plane);
2114 dspcntr = I915_READ(reg);
2115 /* Mask out pixel format bits in case we change it */
2116 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2117 switch (fb->pixel_format) {
2119 dspcntr |= DISPPLANE_8BPP;
2121 case DRM_FORMAT_XRGB1555:
2122 case DRM_FORMAT_ARGB1555:
2123 dspcntr |= DISPPLANE_BGRX555;
2125 case DRM_FORMAT_RGB565:
2126 dspcntr |= DISPPLANE_BGRX565;
2128 case DRM_FORMAT_XRGB8888:
2129 case DRM_FORMAT_ARGB8888:
2130 dspcntr |= DISPPLANE_BGRX888;
2132 case DRM_FORMAT_XBGR8888:
2133 case DRM_FORMAT_ABGR8888:
2134 dspcntr |= DISPPLANE_RGBX888;
2136 case DRM_FORMAT_XRGB2101010:
2137 case DRM_FORMAT_ARGB2101010:
2138 dspcntr |= DISPPLANE_BGRX101010;
2140 case DRM_FORMAT_XBGR2101010:
2141 case DRM_FORMAT_ABGR2101010:
2142 dspcntr |= DISPPLANE_RGBX101010;
2148 if (INTEL_INFO(dev)->gen >= 4) {
2149 if (obj->tiling_mode != I915_TILING_NONE)
2150 dspcntr |= DISPPLANE_TILED;
2152 dspcntr &= ~DISPPLANE_TILED;
2155 I915_WRITE(reg, dspcntr);
2157 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2159 if (INTEL_INFO(dev)->gen >= 4) {
2160 intel_crtc->dspaddr_offset =
2161 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2162 fb->bits_per_pixel / 8,
2164 linear_offset -= intel_crtc->dspaddr_offset;
2166 intel_crtc->dspaddr_offset = linear_offset;
2169 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2170 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2171 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2172 if (INTEL_INFO(dev)->gen >= 4) {
2173 I915_MODIFY_DISPBASE(DSPSURF(plane),
2174 obj->gtt_offset + intel_crtc->dspaddr_offset);
2175 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2176 I915_WRITE(DSPLINOFF(plane), linear_offset);
2178 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2184 static int ironlake_update_plane(struct drm_crtc *crtc,
2185 struct drm_framebuffer *fb, int x, int y)
2187 struct drm_device *dev = crtc->dev;
2188 struct drm_i915_private *dev_priv = dev->dev_private;
2189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2190 struct intel_framebuffer *intel_fb;
2191 struct drm_i915_gem_object *obj;
2192 int plane = intel_crtc->plane;
2193 unsigned long linear_offset;
2203 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2207 intel_fb = to_intel_framebuffer(fb);
2208 obj = intel_fb->obj;
2210 reg = DSPCNTR(plane);
2211 dspcntr = I915_READ(reg);
2212 /* Mask out pixel format bits in case we change it */
2213 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2214 switch (fb->pixel_format) {
2216 dspcntr |= DISPPLANE_8BPP;
2218 case DRM_FORMAT_RGB565:
2219 dspcntr |= DISPPLANE_BGRX565;
2221 case DRM_FORMAT_XRGB8888:
2222 case DRM_FORMAT_ARGB8888:
2223 dspcntr |= DISPPLANE_BGRX888;
2225 case DRM_FORMAT_XBGR8888:
2226 case DRM_FORMAT_ABGR8888:
2227 dspcntr |= DISPPLANE_RGBX888;
2229 case DRM_FORMAT_XRGB2101010:
2230 case DRM_FORMAT_ARGB2101010:
2231 dspcntr |= DISPPLANE_BGRX101010;
2233 case DRM_FORMAT_XBGR2101010:
2234 case DRM_FORMAT_ABGR2101010:
2235 dspcntr |= DISPPLANE_RGBX101010;
2241 if (obj->tiling_mode != I915_TILING_NONE)
2242 dspcntr |= DISPPLANE_TILED;
2244 dspcntr &= ~DISPPLANE_TILED;
2247 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2249 I915_WRITE(reg, dspcntr);
2251 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2252 intel_crtc->dspaddr_offset =
2253 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2254 fb->bits_per_pixel / 8,
2256 linear_offset -= intel_crtc->dspaddr_offset;
2258 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2259 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2260 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2261 I915_MODIFY_DISPBASE(DSPSURF(plane),
2262 obj->gtt_offset + intel_crtc->dspaddr_offset);
2263 if (IS_HASWELL(dev)) {
2264 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2266 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2267 I915_WRITE(DSPLINOFF(plane), linear_offset);
2274 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2276 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2277 int x, int y, enum mode_set_atomic state)
2279 struct drm_device *dev = crtc->dev;
2280 struct drm_i915_private *dev_priv = dev->dev_private;
2282 if (dev_priv->display.disable_fbc)
2283 dev_priv->display.disable_fbc(dev);
2284 intel_increase_pllclock(crtc);
2286 return dev_priv->display.update_plane(crtc, fb, x, y);
2289 void intel_display_handle_reset(struct drm_device *dev)
2291 struct drm_i915_private *dev_priv = dev->dev_private;
2292 struct drm_crtc *crtc;
2295 * Flips in the rings have been nuked by the reset,
2296 * so complete all pending flips so that user space
2297 * will get its events and not get stuck.
2299 * Also update the base address of all primary
2300 * planes to the the last fb to make sure we're
2301 * showing the correct fb after a reset.
2303 * Need to make two loops over the crtcs so that we
2304 * don't try to grab a crtc mutex before the
2305 * pending_flip_queue really got woken up.
2308 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2310 enum plane plane = intel_crtc->plane;
2312 intel_prepare_page_flip(dev, plane);
2313 intel_finish_page_flip_plane(dev, plane);
2316 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2319 mutex_lock(&crtc->mutex);
2320 if (intel_crtc->active)
2321 dev_priv->display.update_plane(crtc, crtc->fb,
2323 mutex_unlock(&crtc->mutex);
2328 intel_finish_fb(struct drm_framebuffer *old_fb)
2330 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2331 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2332 bool was_interruptible = dev_priv->mm.interruptible;
2335 /* Big Hammer, we also need to ensure that any pending
2336 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2337 * current scanout is retired before unpinning the old
2340 * This should only fail upon a hung GPU, in which case we
2341 * can safely continue.
2343 dev_priv->mm.interruptible = false;
2344 ret = i915_gem_object_finish_gpu(obj);
2345 dev_priv->mm.interruptible = was_interruptible;
2350 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2352 struct drm_device *dev = crtc->dev;
2353 struct drm_i915_master_private *master_priv;
2354 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2356 if (!dev->primary->master)
2359 master_priv = dev->primary->master->driver_priv;
2360 if (!master_priv->sarea_priv)
2363 switch (intel_crtc->pipe) {
2365 master_priv->sarea_priv->pipeA_x = x;
2366 master_priv->sarea_priv->pipeA_y = y;
2369 master_priv->sarea_priv->pipeB_x = x;
2370 master_priv->sarea_priv->pipeB_y = y;
2378 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2379 struct drm_framebuffer *fb)
2381 struct drm_device *dev = crtc->dev;
2382 struct drm_i915_private *dev_priv = dev->dev_private;
2383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2384 struct drm_framebuffer *old_fb;
2389 DRM_ERROR("No FB bound\n");
2393 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2394 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2395 plane_name(intel_crtc->plane),
2396 INTEL_INFO(dev)->num_pipes);
2400 mutex_lock(&dev->struct_mutex);
2401 ret = intel_pin_and_fence_fb_obj(dev,
2402 to_intel_framebuffer(fb)->obj,
2405 mutex_unlock(&dev->struct_mutex);
2406 DRM_ERROR("pin & fence failed\n");
2410 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2412 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2413 mutex_unlock(&dev->struct_mutex);
2414 DRM_ERROR("failed to update base address\n");
2424 intel_wait_for_vblank(dev, intel_crtc->pipe);
2425 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2428 intel_update_fbc(dev);
2429 mutex_unlock(&dev->struct_mutex);
2431 intel_crtc_update_sarea_pos(crtc, x, y);
2436 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2438 struct drm_device *dev = crtc->dev;
2439 struct drm_i915_private *dev_priv = dev->dev_private;
2440 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2441 int pipe = intel_crtc->pipe;
2444 /* enable normal train */
2445 reg = FDI_TX_CTL(pipe);
2446 temp = I915_READ(reg);
2447 if (IS_IVYBRIDGE(dev)) {
2448 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2449 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2451 temp &= ~FDI_LINK_TRAIN_NONE;
2452 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2454 I915_WRITE(reg, temp);
2456 reg = FDI_RX_CTL(pipe);
2457 temp = I915_READ(reg);
2458 if (HAS_PCH_CPT(dev)) {
2459 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2460 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2462 temp &= ~FDI_LINK_TRAIN_NONE;
2463 temp |= FDI_LINK_TRAIN_NONE;
2465 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2467 /* wait one idle pattern time */
2471 /* IVB wants error correction enabled */
2472 if (IS_IVYBRIDGE(dev))
2473 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2474 FDI_FE_ERRC_ENABLE);
2477 static void ivb_modeset_global_resources(struct drm_device *dev)
2479 struct drm_i915_private *dev_priv = dev->dev_private;
2480 struct intel_crtc *pipe_B_crtc =
2481 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2482 struct intel_crtc *pipe_C_crtc =
2483 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2486 /* When everything is off disable fdi C so that we could enable fdi B
2487 * with all lanes. XXX: This misses the case where a pipe is not using
2488 * any pch resources and so doesn't need any fdi lanes. */
2489 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2490 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2491 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2493 temp = I915_READ(SOUTH_CHICKEN1);
2494 temp &= ~FDI_BC_BIFURCATION_SELECT;
2495 DRM_DEBUG_KMS("disabling fdi C rx\n");
2496 I915_WRITE(SOUTH_CHICKEN1, temp);
2500 /* The FDI link training functions for ILK/Ibexpeak. */
2501 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2503 struct drm_device *dev = crtc->dev;
2504 struct drm_i915_private *dev_priv = dev->dev_private;
2505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2506 int pipe = intel_crtc->pipe;
2507 int plane = intel_crtc->plane;
2508 u32 reg, temp, tries;
2510 /* FDI needs bits from pipe & plane first */
2511 assert_pipe_enabled(dev_priv, pipe);
2512 assert_plane_enabled(dev_priv, plane);
2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2516 reg = FDI_RX_IMR(pipe);
2517 temp = I915_READ(reg);
2518 temp &= ~FDI_RX_SYMBOL_LOCK;
2519 temp &= ~FDI_RX_BIT_LOCK;
2520 I915_WRITE(reg, temp);
2524 /* enable CPU FDI TX and PCH FDI RX */
2525 reg = FDI_TX_CTL(pipe);
2526 temp = I915_READ(reg);
2528 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2529 temp &= ~FDI_LINK_TRAIN_NONE;
2530 temp |= FDI_LINK_TRAIN_PATTERN_1;
2531 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2533 reg = FDI_RX_CTL(pipe);
2534 temp = I915_READ(reg);
2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_1;
2537 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2542 /* Ironlake workaround, enable clock pointer after FDI enable*/
2543 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2544 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2545 FDI_RX_PHASE_SYNC_POINTER_EN);
2547 reg = FDI_RX_IIR(pipe);
2548 for (tries = 0; tries < 5; tries++) {
2549 temp = I915_READ(reg);
2550 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2552 if ((temp & FDI_RX_BIT_LOCK)) {
2553 DRM_DEBUG_KMS("FDI train 1 done.\n");
2554 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2559 DRM_ERROR("FDI train 1 fail!\n");
2562 reg = FDI_TX_CTL(pipe);
2563 temp = I915_READ(reg);
2564 temp &= ~FDI_LINK_TRAIN_NONE;
2565 temp |= FDI_LINK_TRAIN_PATTERN_2;
2566 I915_WRITE(reg, temp);
2568 reg = FDI_RX_CTL(pipe);
2569 temp = I915_READ(reg);
2570 temp &= ~FDI_LINK_TRAIN_NONE;
2571 temp |= FDI_LINK_TRAIN_PATTERN_2;
2572 I915_WRITE(reg, temp);
2577 reg = FDI_RX_IIR(pipe);
2578 for (tries = 0; tries < 5; tries++) {
2579 temp = I915_READ(reg);
2580 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582 if (temp & FDI_RX_SYMBOL_LOCK) {
2583 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2584 DRM_DEBUG_KMS("FDI train 2 done.\n");
2589 DRM_ERROR("FDI train 2 fail!\n");
2591 DRM_DEBUG_KMS("FDI train done\n");
2595 static const int snb_b_fdi_train_param[] = {
2596 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2597 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2598 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2599 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2602 /* The FDI link training functions for SNB/Cougarpoint. */
2603 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2605 struct drm_device *dev = crtc->dev;
2606 struct drm_i915_private *dev_priv = dev->dev_private;
2607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2608 int pipe = intel_crtc->pipe;
2609 u32 reg, temp, i, retry;
2611 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2613 reg = FDI_RX_IMR(pipe);
2614 temp = I915_READ(reg);
2615 temp &= ~FDI_RX_SYMBOL_LOCK;
2616 temp &= ~FDI_RX_BIT_LOCK;
2617 I915_WRITE(reg, temp);
2622 /* enable CPU FDI TX and PCH FDI RX */
2623 reg = FDI_TX_CTL(pipe);
2624 temp = I915_READ(reg);
2626 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2627 temp &= ~FDI_LINK_TRAIN_NONE;
2628 temp |= FDI_LINK_TRAIN_PATTERN_1;
2629 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2631 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2632 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2634 I915_WRITE(FDI_RX_MISC(pipe),
2635 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2637 reg = FDI_RX_CTL(pipe);
2638 temp = I915_READ(reg);
2639 if (HAS_PCH_CPT(dev)) {
2640 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2641 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2643 temp &= ~FDI_LINK_TRAIN_NONE;
2644 temp |= FDI_LINK_TRAIN_PATTERN_1;
2646 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2651 for (i = 0; i < 4; i++) {
2652 reg = FDI_TX_CTL(pipe);
2653 temp = I915_READ(reg);
2654 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2655 temp |= snb_b_fdi_train_param[i];
2656 I915_WRITE(reg, temp);
2661 for (retry = 0; retry < 5; retry++) {
2662 reg = FDI_RX_IIR(pipe);
2663 temp = I915_READ(reg);
2664 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2665 if (temp & FDI_RX_BIT_LOCK) {
2666 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2667 DRM_DEBUG_KMS("FDI train 1 done.\n");
2676 DRM_ERROR("FDI train 1 fail!\n");
2679 reg = FDI_TX_CTL(pipe);
2680 temp = I915_READ(reg);
2681 temp &= ~FDI_LINK_TRAIN_NONE;
2682 temp |= FDI_LINK_TRAIN_PATTERN_2;
2684 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2686 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2688 I915_WRITE(reg, temp);
2690 reg = FDI_RX_CTL(pipe);
2691 temp = I915_READ(reg);
2692 if (HAS_PCH_CPT(dev)) {
2693 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2694 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2696 temp &= ~FDI_LINK_TRAIN_NONE;
2697 temp |= FDI_LINK_TRAIN_PATTERN_2;
2699 I915_WRITE(reg, temp);
2704 for (i = 0; i < 4; i++) {
2705 reg = FDI_TX_CTL(pipe);
2706 temp = I915_READ(reg);
2707 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2708 temp |= snb_b_fdi_train_param[i];
2709 I915_WRITE(reg, temp);
2714 for (retry = 0; retry < 5; retry++) {
2715 reg = FDI_RX_IIR(pipe);
2716 temp = I915_READ(reg);
2717 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2718 if (temp & FDI_RX_SYMBOL_LOCK) {
2719 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2720 DRM_DEBUG_KMS("FDI train 2 done.\n");
2729 DRM_ERROR("FDI train 2 fail!\n");
2731 DRM_DEBUG_KMS("FDI train done.\n");
2734 /* Manual link training for Ivy Bridge A0 parts */
2735 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2737 struct drm_device *dev = crtc->dev;
2738 struct drm_i915_private *dev_priv = dev->dev_private;
2739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2740 int pipe = intel_crtc->pipe;
2743 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2745 reg = FDI_RX_IMR(pipe);
2746 temp = I915_READ(reg);
2747 temp &= ~FDI_RX_SYMBOL_LOCK;
2748 temp &= ~FDI_RX_BIT_LOCK;
2749 I915_WRITE(reg, temp);
2754 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2755 I915_READ(FDI_RX_IIR(pipe)));
2757 /* enable CPU FDI TX and PCH FDI RX */
2758 reg = FDI_TX_CTL(pipe);
2759 temp = I915_READ(reg);
2761 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2762 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2763 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2764 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2765 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2766 temp |= FDI_COMPOSITE_SYNC;
2767 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2769 I915_WRITE(FDI_RX_MISC(pipe),
2770 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2772 reg = FDI_RX_CTL(pipe);
2773 temp = I915_READ(reg);
2774 temp &= ~FDI_LINK_TRAIN_AUTO;
2775 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2776 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2777 temp |= FDI_COMPOSITE_SYNC;
2778 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2783 for (i = 0; i < 4; i++) {
2784 reg = FDI_TX_CTL(pipe);
2785 temp = I915_READ(reg);
2786 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2787 temp |= snb_b_fdi_train_param[i];
2788 I915_WRITE(reg, temp);
2793 reg = FDI_RX_IIR(pipe);
2794 temp = I915_READ(reg);
2795 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2797 if (temp & FDI_RX_BIT_LOCK ||
2798 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2799 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2800 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2805 DRM_ERROR("FDI train 1 fail!\n");
2808 reg = FDI_TX_CTL(pipe);
2809 temp = I915_READ(reg);
2810 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2811 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2812 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2813 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2814 I915_WRITE(reg, temp);
2816 reg = FDI_RX_CTL(pipe);
2817 temp = I915_READ(reg);
2818 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2819 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2820 I915_WRITE(reg, temp);
2825 for (i = 0; i < 4; i++) {
2826 reg = FDI_TX_CTL(pipe);
2827 temp = I915_READ(reg);
2828 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2829 temp |= snb_b_fdi_train_param[i];
2830 I915_WRITE(reg, temp);
2835 reg = FDI_RX_IIR(pipe);
2836 temp = I915_READ(reg);
2837 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2839 if (temp & FDI_RX_SYMBOL_LOCK) {
2840 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2841 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2846 DRM_ERROR("FDI train 2 fail!\n");
2848 DRM_DEBUG_KMS("FDI train done.\n");
2851 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2853 struct drm_device *dev = intel_crtc->base.dev;
2854 struct drm_i915_private *dev_priv = dev->dev_private;
2855 int pipe = intel_crtc->pipe;
2859 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2860 reg = FDI_RX_CTL(pipe);
2861 temp = I915_READ(reg);
2862 temp &= ~((0x7 << 19) | (0x7 << 16));
2863 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2864 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2865 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2870 /* Switch from Rawclk to PCDclk */
2871 temp = I915_READ(reg);
2872 I915_WRITE(reg, temp | FDI_PCDCLK);
2877 /* Enable CPU FDI TX PLL, always on for Ironlake */
2878 reg = FDI_TX_CTL(pipe);
2879 temp = I915_READ(reg);
2880 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2881 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2888 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2890 struct drm_device *dev = intel_crtc->base.dev;
2891 struct drm_i915_private *dev_priv = dev->dev_private;
2892 int pipe = intel_crtc->pipe;
2895 /* Switch from PCDclk to Rawclk */
2896 reg = FDI_RX_CTL(pipe);
2897 temp = I915_READ(reg);
2898 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2900 /* Disable CPU FDI TX PLL */
2901 reg = FDI_TX_CTL(pipe);
2902 temp = I915_READ(reg);
2903 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2908 reg = FDI_RX_CTL(pipe);
2909 temp = I915_READ(reg);
2910 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2912 /* Wait for the clocks to turn off. */
2917 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2919 struct drm_device *dev = crtc->dev;
2920 struct drm_i915_private *dev_priv = dev->dev_private;
2921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2922 int pipe = intel_crtc->pipe;
2925 /* disable CPU FDI tx and PCH FDI rx */
2926 reg = FDI_TX_CTL(pipe);
2927 temp = I915_READ(reg);
2928 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2931 reg = FDI_RX_CTL(pipe);
2932 temp = I915_READ(reg);
2933 temp &= ~(0x7 << 16);
2934 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2935 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2940 /* Ironlake workaround, disable clock pointer after downing FDI */
2941 if (HAS_PCH_IBX(dev)) {
2942 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2945 /* still set train pattern 1 */
2946 reg = FDI_TX_CTL(pipe);
2947 temp = I915_READ(reg);
2948 temp &= ~FDI_LINK_TRAIN_NONE;
2949 temp |= FDI_LINK_TRAIN_PATTERN_1;
2950 I915_WRITE(reg, temp);
2952 reg = FDI_RX_CTL(pipe);
2953 temp = I915_READ(reg);
2954 if (HAS_PCH_CPT(dev)) {
2955 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2956 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2958 temp &= ~FDI_LINK_TRAIN_NONE;
2959 temp |= FDI_LINK_TRAIN_PATTERN_1;
2961 /* BPC in FDI rx is consistent with that in PIPECONF */
2962 temp &= ~(0x07 << 16);
2963 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2964 I915_WRITE(reg, temp);
2970 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2972 struct drm_device *dev = crtc->dev;
2973 struct drm_i915_private *dev_priv = dev->dev_private;
2974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2975 unsigned long flags;
2978 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2979 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2982 spin_lock_irqsave(&dev->event_lock, flags);
2983 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2984 spin_unlock_irqrestore(&dev->event_lock, flags);
2989 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2991 struct drm_device *dev = crtc->dev;
2992 struct drm_i915_private *dev_priv = dev->dev_private;
2994 if (crtc->fb == NULL)
2997 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2999 wait_event(dev_priv->pending_flip_queue,
3000 !intel_crtc_has_pending_flip(crtc));
3002 mutex_lock(&dev->struct_mutex);
3003 intel_finish_fb(crtc->fb);
3004 mutex_unlock(&dev->struct_mutex);
3007 /* Program iCLKIP clock to the desired frequency */
3008 static void lpt_program_iclkip(struct drm_crtc *crtc)
3010 struct drm_device *dev = crtc->dev;
3011 struct drm_i915_private *dev_priv = dev->dev_private;
3012 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3015 mutex_lock(&dev_priv->dpio_lock);
3017 /* It is necessary to ungate the pixclk gate prior to programming
3018 * the divisors, and gate it back when it is done.
3020 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3022 /* Disable SSCCTL */
3023 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3024 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3028 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3029 if (crtc->mode.clock == 20000) {
3034 /* The iCLK virtual clock root frequency is in MHz,
3035 * but the crtc->mode.clock in in KHz. To get the divisors,
3036 * it is necessary to divide one by another, so we
3037 * convert the virtual clock precision to KHz here for higher
3040 u32 iclk_virtual_root_freq = 172800 * 1000;
3041 u32 iclk_pi_range = 64;
3042 u32 desired_divisor, msb_divisor_value, pi_value;
3044 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3045 msb_divisor_value = desired_divisor / iclk_pi_range;
3046 pi_value = desired_divisor % iclk_pi_range;
3049 divsel = msb_divisor_value - 2;
3050 phaseinc = pi_value;
3053 /* This should not happen with any sane values */
3054 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3055 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3056 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3057 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3059 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3066 /* Program SSCDIVINTPHASE6 */
3067 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3068 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3069 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3070 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3071 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3072 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3073 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3074 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3076 /* Program SSCAUXDIV */
3077 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3078 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3079 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3080 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3082 /* Enable modulator and associated divider */
3083 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3084 temp &= ~SBI_SSCCTL_DISABLE;
3085 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3087 /* Wait for initialization time */
3090 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3092 mutex_unlock(&dev_priv->dpio_lock);
3096 * Enable PCH resources required for PCH ports:
3098 * - FDI training & RX/TX
3099 * - update transcoder timings
3100 * - DP transcoding bits
3103 static void ironlake_pch_enable(struct drm_crtc *crtc)
3105 struct drm_device *dev = crtc->dev;
3106 struct drm_i915_private *dev_priv = dev->dev_private;
3107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3108 int pipe = intel_crtc->pipe;
3111 assert_transcoder_disabled(dev_priv, pipe);
3113 /* Write the TU size bits before fdi link training, so that error
3114 * detection works. */
3115 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3116 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3118 /* For PCH output, training FDI link */
3119 dev_priv->display.fdi_link_train(crtc);
3121 /* XXX: pch pll's can be enabled any time before we enable the PCH
3122 * transcoder, and we actually should do this to not upset any PCH
3123 * transcoder that already use the clock when we share it.
3125 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3126 * unconditionally resets the pll - we need that to have the right LVDS
3127 * enable sequence. */
3128 ironlake_enable_pch_pll(intel_crtc);
3130 if (HAS_PCH_CPT(dev)) {
3133 temp = I915_READ(PCH_DPLL_SEL);
3137 temp |= TRANSA_DPLL_ENABLE;
3138 sel = TRANSA_DPLLB_SEL;
3141 temp |= TRANSB_DPLL_ENABLE;
3142 sel = TRANSB_DPLLB_SEL;
3145 temp |= TRANSC_DPLL_ENABLE;
3146 sel = TRANSC_DPLLB_SEL;
3149 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3153 I915_WRITE(PCH_DPLL_SEL, temp);
3156 /* set transcoder timing, panel must allow it */
3157 assert_panel_unlocked(dev_priv, pipe);
3158 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3159 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3160 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
3162 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3163 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3164 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
3165 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
3167 intel_fdi_normal_train(crtc);
3169 /* For PCH DP, enable TRANS_DP_CTL */
3170 if (HAS_PCH_CPT(dev) &&
3171 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3172 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3173 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3174 reg = TRANS_DP_CTL(pipe);
3175 temp = I915_READ(reg);
3176 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3177 TRANS_DP_SYNC_MASK |
3179 temp |= (TRANS_DP_OUTPUT_ENABLE |
3180 TRANS_DP_ENH_FRAMING);
3181 temp |= bpc << 9; /* same format but at 11:9 */
3183 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3184 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3185 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3186 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3188 switch (intel_trans_dp_port_sel(crtc)) {
3190 temp |= TRANS_DP_PORT_SEL_B;
3193 temp |= TRANS_DP_PORT_SEL_C;
3196 temp |= TRANS_DP_PORT_SEL_D;
3202 I915_WRITE(reg, temp);
3205 ironlake_enable_pch_transcoder(dev_priv, pipe);
3208 static void lpt_pch_enable(struct drm_crtc *crtc)
3210 struct drm_device *dev = crtc->dev;
3211 struct drm_i915_private *dev_priv = dev->dev_private;
3212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3213 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3215 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3217 lpt_program_iclkip(crtc);
3219 /* Set transcoder timing. */
3220 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3221 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3222 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
3224 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3225 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3226 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3227 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3229 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3232 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3234 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3239 if (pll->refcount == 0) {
3240 WARN(1, "bad PCH PLL refcount\n");
3245 intel_crtc->pch_pll = NULL;
3248 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3250 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3251 struct intel_pch_pll *pll;
3254 pll = intel_crtc->pch_pll;
3256 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3257 intel_crtc->base.base.id, pll->pll_reg);
3261 if (HAS_PCH_IBX(dev_priv->dev)) {
3262 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3263 i = intel_crtc->pipe;
3264 pll = &dev_priv->pch_plls[i];
3266 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3267 intel_crtc->base.base.id, pll->pll_reg);
3272 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3273 pll = &dev_priv->pch_plls[i];
3275 /* Only want to check enabled timings first */
3276 if (pll->refcount == 0)
3279 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3280 fp == I915_READ(pll->fp0_reg)) {
3281 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3282 intel_crtc->base.base.id,
3283 pll->pll_reg, pll->refcount, pll->active);
3289 /* Ok no matching timings, maybe there's a free one? */
3290 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3291 pll = &dev_priv->pch_plls[i];
3292 if (pll->refcount == 0) {
3293 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3294 intel_crtc->base.base.id, pll->pll_reg);
3302 intel_crtc->pch_pll = pll;
3304 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3305 prepare: /* separate function? */
3306 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3308 /* Wait for the clocks to stabilize before rewriting the regs */
3309 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3310 POSTING_READ(pll->pll_reg);
3313 I915_WRITE(pll->fp0_reg, fp);
3314 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3319 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3321 struct drm_i915_private *dev_priv = dev->dev_private;
3322 int dslreg = PIPEDSL(pipe);
3325 temp = I915_READ(dslreg);
3327 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3328 if (wait_for(I915_READ(dslreg) != temp, 5))
3329 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3333 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3335 struct drm_device *dev = crtc->dev;
3336 struct drm_i915_private *dev_priv = dev->dev_private;
3337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3338 struct intel_encoder *encoder;
3339 int pipe = intel_crtc->pipe;
3340 int plane = intel_crtc->plane;
3343 WARN_ON(!crtc->enabled);
3345 if (intel_crtc->active)
3348 intel_crtc->active = true;
3350 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3351 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3353 intel_update_watermarks(dev);
3355 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3356 temp = I915_READ(PCH_LVDS);
3357 if ((temp & LVDS_PORT_EN) == 0)
3358 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3362 if (intel_crtc->config.has_pch_encoder) {
3363 /* Note: FDI PLL enabling _must_ be done before we enable the
3364 * cpu pipes, hence this is separate from all the other fdi/pch
3366 ironlake_fdi_pll_enable(intel_crtc);
3368 assert_fdi_tx_disabled(dev_priv, pipe);
3369 assert_fdi_rx_disabled(dev_priv, pipe);
3372 for_each_encoder_on_crtc(dev, crtc, encoder)
3373 if (encoder->pre_enable)
3374 encoder->pre_enable(encoder);
3376 /* Enable panel fitting for LVDS */
3377 if (dev_priv->pch_pf_size &&
3378 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3379 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3380 /* Force use of hard-coded filter coefficients
3381 * as some pre-programmed values are broken,
3384 if (IS_IVYBRIDGE(dev))
3385 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3386 PF_PIPE_SEL_IVB(pipe));
3388 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3389 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3390 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3394 * On ILK+ LUT must be loaded before the pipe is running but with
3397 intel_crtc_load_lut(crtc);
3399 intel_enable_pipe(dev_priv, pipe,
3400 intel_crtc->config.has_pch_encoder);
3401 intel_enable_plane(dev_priv, plane, pipe);
3403 if (intel_crtc->config.has_pch_encoder)
3404 ironlake_pch_enable(crtc);
3406 mutex_lock(&dev->struct_mutex);
3407 intel_update_fbc(dev);
3408 mutex_unlock(&dev->struct_mutex);
3410 intel_crtc_update_cursor(crtc, true);
3412 for_each_encoder_on_crtc(dev, crtc, encoder)
3413 encoder->enable(encoder);
3415 if (HAS_PCH_CPT(dev))
3416 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3419 * There seems to be a race in PCH platform hw (at least on some
3420 * outputs) where an enabled pipe still completes any pageflip right
3421 * away (as if the pipe is off) instead of waiting for vblank. As soon
3422 * as the first vblank happend, everything works as expected. Hence just
3423 * wait for one vblank before returning to avoid strange things
3426 intel_wait_for_vblank(dev, intel_crtc->pipe);
3429 static void haswell_crtc_enable(struct drm_crtc *crtc)
3431 struct drm_device *dev = crtc->dev;
3432 struct drm_i915_private *dev_priv = dev->dev_private;
3433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3434 struct intel_encoder *encoder;
3435 int pipe = intel_crtc->pipe;
3436 int plane = intel_crtc->plane;
3438 WARN_ON(!crtc->enabled);
3440 if (intel_crtc->active)
3443 intel_crtc->active = true;
3445 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3446 if (intel_crtc->config.has_pch_encoder)
3447 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3449 intel_update_watermarks(dev);
3451 if (intel_crtc->config.has_pch_encoder)
3452 dev_priv->display.fdi_link_train(crtc);
3454 for_each_encoder_on_crtc(dev, crtc, encoder)
3455 if (encoder->pre_enable)
3456 encoder->pre_enable(encoder);
3458 intel_ddi_enable_pipe_clock(intel_crtc);
3460 /* Enable panel fitting for eDP */
3461 if (dev_priv->pch_pf_size &&
3462 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3463 /* Force use of hard-coded filter coefficients
3464 * as some pre-programmed values are broken,
3467 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3468 PF_PIPE_SEL_IVB(pipe));
3469 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3470 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3474 * On ILK+ LUT must be loaded before the pipe is running but with
3477 intel_crtc_load_lut(crtc);
3479 intel_ddi_set_pipe_settings(crtc);
3480 intel_ddi_enable_transcoder_func(crtc);
3482 intel_enable_pipe(dev_priv, pipe,
3483 intel_crtc->config.has_pch_encoder);
3484 intel_enable_plane(dev_priv, plane, pipe);
3486 if (intel_crtc->config.has_pch_encoder)
3487 lpt_pch_enable(crtc);
3489 mutex_lock(&dev->struct_mutex);
3490 intel_update_fbc(dev);
3491 mutex_unlock(&dev->struct_mutex);
3493 intel_crtc_update_cursor(crtc, true);
3495 for_each_encoder_on_crtc(dev, crtc, encoder)
3496 encoder->enable(encoder);
3499 * There seems to be a race in PCH platform hw (at least on some
3500 * outputs) where an enabled pipe still completes any pageflip right
3501 * away (as if the pipe is off) instead of waiting for vblank. As soon
3502 * as the first vblank happend, everything works as expected. Hence just
3503 * wait for one vblank before returning to avoid strange things
3506 intel_wait_for_vblank(dev, intel_crtc->pipe);
3509 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3511 struct drm_device *dev = crtc->dev;
3512 struct drm_i915_private *dev_priv = dev->dev_private;
3513 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3514 struct intel_encoder *encoder;
3515 int pipe = intel_crtc->pipe;
3516 int plane = intel_crtc->plane;
3520 if (!intel_crtc->active)
3523 for_each_encoder_on_crtc(dev, crtc, encoder)
3524 encoder->disable(encoder);
3526 intel_crtc_wait_for_pending_flips(crtc);
3527 drm_vblank_off(dev, pipe);
3528 intel_crtc_update_cursor(crtc, false);
3530 intel_disable_plane(dev_priv, plane, pipe);
3532 if (dev_priv->cfb_plane == plane)
3533 intel_disable_fbc(dev);
3535 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3536 intel_disable_pipe(dev_priv, pipe);
3539 I915_WRITE(PF_CTL(pipe), 0);
3540 I915_WRITE(PF_WIN_SZ(pipe), 0);
3542 for_each_encoder_on_crtc(dev, crtc, encoder)
3543 if (encoder->post_disable)
3544 encoder->post_disable(encoder);
3546 ironlake_fdi_disable(crtc);
3548 ironlake_disable_pch_transcoder(dev_priv, pipe);
3549 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3551 if (HAS_PCH_CPT(dev)) {
3552 /* disable TRANS_DP_CTL */
3553 reg = TRANS_DP_CTL(pipe);
3554 temp = I915_READ(reg);
3555 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3556 temp |= TRANS_DP_PORT_SEL_NONE;
3557 I915_WRITE(reg, temp);
3559 /* disable DPLL_SEL */
3560 temp = I915_READ(PCH_DPLL_SEL);
3563 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3566 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3569 /* C shares PLL A or B */
3570 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3575 I915_WRITE(PCH_DPLL_SEL, temp);
3578 /* disable PCH DPLL */
3579 intel_disable_pch_pll(intel_crtc);
3581 ironlake_fdi_pll_disable(intel_crtc);
3583 intel_crtc->active = false;
3584 intel_update_watermarks(dev);
3586 mutex_lock(&dev->struct_mutex);
3587 intel_update_fbc(dev);
3588 mutex_unlock(&dev->struct_mutex);
3591 static void haswell_crtc_disable(struct drm_crtc *crtc)
3593 struct drm_device *dev = crtc->dev;
3594 struct drm_i915_private *dev_priv = dev->dev_private;
3595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3596 struct intel_encoder *encoder;
3597 int pipe = intel_crtc->pipe;
3598 int plane = intel_crtc->plane;
3599 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3601 if (!intel_crtc->active)
3604 for_each_encoder_on_crtc(dev, crtc, encoder)
3605 encoder->disable(encoder);
3607 intel_crtc_wait_for_pending_flips(crtc);
3608 drm_vblank_off(dev, pipe);
3609 intel_crtc_update_cursor(crtc, false);
3611 intel_disable_plane(dev_priv, plane, pipe);
3613 if (dev_priv->cfb_plane == plane)
3614 intel_disable_fbc(dev);
3616 if (intel_crtc->config.has_pch_encoder)
3617 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3618 intel_disable_pipe(dev_priv, pipe);
3620 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3622 /* XXX: Once we have proper panel fitter state tracking implemented with
3623 * hardware state read/check support we should switch to only disable
3624 * the panel fitter when we know it's used. */
3625 if (intel_using_power_well(dev)) {
3626 I915_WRITE(PF_CTL(pipe), 0);
3627 I915_WRITE(PF_WIN_SZ(pipe), 0);
3630 intel_ddi_disable_pipe_clock(intel_crtc);
3632 for_each_encoder_on_crtc(dev, crtc, encoder)
3633 if (encoder->post_disable)
3634 encoder->post_disable(encoder);
3636 if (intel_crtc->config.has_pch_encoder) {
3637 lpt_disable_pch_transcoder(dev_priv);
3638 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3639 intel_ddi_fdi_disable(crtc);
3642 intel_crtc->active = false;
3643 intel_update_watermarks(dev);
3645 mutex_lock(&dev->struct_mutex);
3646 intel_update_fbc(dev);
3647 mutex_unlock(&dev->struct_mutex);
3650 static void ironlake_crtc_off(struct drm_crtc *crtc)
3652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3653 intel_put_pch_pll(intel_crtc);
3656 static void haswell_crtc_off(struct drm_crtc *crtc)
3658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3660 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3661 * start using it. */
3662 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3664 intel_ddi_put_crtc_pll(crtc);
3667 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3669 if (!enable && intel_crtc->overlay) {
3670 struct drm_device *dev = intel_crtc->base.dev;
3671 struct drm_i915_private *dev_priv = dev->dev_private;
3673 mutex_lock(&dev->struct_mutex);
3674 dev_priv->mm.interruptible = false;
3675 (void) intel_overlay_switch_off(intel_crtc->overlay);
3676 dev_priv->mm.interruptible = true;
3677 mutex_unlock(&dev->struct_mutex);
3680 /* Let userspace switch the overlay on again. In most cases userspace
3681 * has to recompute where to put it anyway.
3686 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3687 * cursor plane briefly if not already running after enabling the display
3689 * This workaround avoids occasional blank screens when self refresh is
3693 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3695 u32 cntl = I915_READ(CURCNTR(pipe));
3697 if ((cntl & CURSOR_MODE) == 0) {
3698 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3700 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3701 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3702 intel_wait_for_vblank(dev_priv->dev, pipe);
3703 I915_WRITE(CURCNTR(pipe), cntl);
3704 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3705 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3709 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3711 struct drm_device *dev = crtc->dev;
3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3714 struct intel_encoder *encoder;
3715 int pipe = intel_crtc->pipe;
3716 int plane = intel_crtc->plane;
3718 WARN_ON(!crtc->enabled);
3720 if (intel_crtc->active)
3723 intel_crtc->active = true;
3724 intel_update_watermarks(dev);
3726 mutex_lock(&dev_priv->dpio_lock);
3728 for_each_encoder_on_crtc(dev, crtc, encoder)
3729 if (encoder->pre_pll_enable)
3730 encoder->pre_pll_enable(encoder);
3732 intel_enable_pll(dev_priv, pipe);
3734 for_each_encoder_on_crtc(dev, crtc, encoder)
3735 if (encoder->pre_enable)
3736 encoder->pre_enable(encoder);
3738 /* VLV wants encoder enabling _before_ the pipe is up. */
3739 for_each_encoder_on_crtc(dev, crtc, encoder)
3740 encoder->enable(encoder);
3742 intel_enable_pipe(dev_priv, pipe, false);
3743 intel_enable_plane(dev_priv, plane, pipe);
3745 intel_crtc_load_lut(crtc);
3746 intel_update_fbc(dev);
3748 /* Give the overlay scaler a chance to enable if it's on this pipe */
3749 intel_crtc_dpms_overlay(intel_crtc, true);
3750 intel_crtc_update_cursor(crtc, true);
3752 mutex_unlock(&dev_priv->dpio_lock);
3755 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3757 struct drm_device *dev = crtc->dev;
3758 struct drm_i915_private *dev_priv = dev->dev_private;
3759 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3760 struct intel_encoder *encoder;
3761 int pipe = intel_crtc->pipe;
3762 int plane = intel_crtc->plane;
3764 WARN_ON(!crtc->enabled);
3766 if (intel_crtc->active)
3769 intel_crtc->active = true;
3770 intel_update_watermarks(dev);
3772 intel_enable_pll(dev_priv, pipe);
3774 for_each_encoder_on_crtc(dev, crtc, encoder)
3775 if (encoder->pre_enable)
3776 encoder->pre_enable(encoder);
3778 intel_enable_pipe(dev_priv, pipe, false);
3779 intel_enable_plane(dev_priv, plane, pipe);
3781 g4x_fixup_plane(dev_priv, pipe);
3783 intel_crtc_load_lut(crtc);
3784 intel_update_fbc(dev);
3786 /* Give the overlay scaler a chance to enable if it's on this pipe */
3787 intel_crtc_dpms_overlay(intel_crtc, true);
3788 intel_crtc_update_cursor(crtc, true);
3790 for_each_encoder_on_crtc(dev, crtc, encoder)
3791 encoder->enable(encoder);
3794 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3796 struct drm_device *dev = crtc->base.dev;
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3799 uint32_t pctl = I915_READ(PFIT_CONTROL);
3801 assert_pipe_disabled(dev_priv, crtc->pipe);
3803 if (INTEL_INFO(dev)->gen >= 4)
3804 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3808 if (pipe == crtc->pipe) {
3809 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3810 I915_WRITE(PFIT_CONTROL, 0);
3814 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3816 struct drm_device *dev = crtc->dev;
3817 struct drm_i915_private *dev_priv = dev->dev_private;
3818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3819 struct intel_encoder *encoder;
3820 int pipe = intel_crtc->pipe;
3821 int plane = intel_crtc->plane;
3823 if (!intel_crtc->active)
3826 for_each_encoder_on_crtc(dev, crtc, encoder)
3827 encoder->disable(encoder);
3829 /* Give the overlay scaler a chance to disable if it's on this pipe */
3830 intel_crtc_wait_for_pending_flips(crtc);
3831 drm_vblank_off(dev, pipe);
3832 intel_crtc_dpms_overlay(intel_crtc, false);
3833 intel_crtc_update_cursor(crtc, false);
3835 if (dev_priv->cfb_plane == plane)
3836 intel_disable_fbc(dev);
3838 intel_disable_plane(dev_priv, plane, pipe);
3839 intel_disable_pipe(dev_priv, pipe);
3841 i9xx_pfit_disable(intel_crtc);
3843 for_each_encoder_on_crtc(dev, crtc, encoder)
3844 if (encoder->post_disable)
3845 encoder->post_disable(encoder);
3847 intel_disable_pll(dev_priv, pipe);
3849 intel_crtc->active = false;
3850 intel_update_fbc(dev);
3851 intel_update_watermarks(dev);
3854 static void i9xx_crtc_off(struct drm_crtc *crtc)
3858 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3861 struct drm_device *dev = crtc->dev;
3862 struct drm_i915_master_private *master_priv;
3863 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3864 int pipe = intel_crtc->pipe;
3866 if (!dev->primary->master)
3869 master_priv = dev->primary->master->driver_priv;
3870 if (!master_priv->sarea_priv)
3875 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3876 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3879 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3880 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3883 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3889 * Sets the power management mode of the pipe and plane.
3891 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3893 struct drm_device *dev = crtc->dev;
3894 struct drm_i915_private *dev_priv = dev->dev_private;
3895 struct intel_encoder *intel_encoder;
3896 bool enable = false;
3898 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3899 enable |= intel_encoder->connectors_active;
3902 dev_priv->display.crtc_enable(crtc);
3904 dev_priv->display.crtc_disable(crtc);
3906 intel_crtc_update_sarea(crtc, enable);
3909 static void intel_crtc_disable(struct drm_crtc *crtc)
3911 struct drm_device *dev = crtc->dev;
3912 struct drm_connector *connector;
3913 struct drm_i915_private *dev_priv = dev->dev_private;
3914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3916 /* crtc should still be enabled when we disable it. */
3917 WARN_ON(!crtc->enabled);
3919 intel_crtc->eld_vld = false;
3920 dev_priv->display.crtc_disable(crtc);
3921 intel_crtc_update_sarea(crtc, false);
3922 dev_priv->display.off(crtc);
3924 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3925 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3928 mutex_lock(&dev->struct_mutex);
3929 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3930 mutex_unlock(&dev->struct_mutex);
3934 /* Update computed state. */
3935 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3936 if (!connector->encoder || !connector->encoder->crtc)
3939 if (connector->encoder->crtc != crtc)
3942 connector->dpms = DRM_MODE_DPMS_OFF;
3943 to_intel_encoder(connector->encoder)->connectors_active = false;
3947 void intel_modeset_disable(struct drm_device *dev)
3949 struct drm_crtc *crtc;
3951 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3953 intel_crtc_disable(crtc);
3957 void intel_encoder_destroy(struct drm_encoder *encoder)
3959 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3961 drm_encoder_cleanup(encoder);
3962 kfree(intel_encoder);
3965 /* Simple dpms helper for encodres with just one connector, no cloning and only
3966 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3967 * state of the entire output pipe. */
3968 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3970 if (mode == DRM_MODE_DPMS_ON) {
3971 encoder->connectors_active = true;
3973 intel_crtc_update_dpms(encoder->base.crtc);
3975 encoder->connectors_active = false;
3977 intel_crtc_update_dpms(encoder->base.crtc);
3981 /* Cross check the actual hw state with our own modeset state tracking (and it's
3982 * internal consistency). */
3983 static void intel_connector_check_state(struct intel_connector *connector)
3985 if (connector->get_hw_state(connector)) {
3986 struct intel_encoder *encoder = connector->encoder;
3987 struct drm_crtc *crtc;
3988 bool encoder_enabled;
3991 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3992 connector->base.base.id,
3993 drm_get_connector_name(&connector->base));
3995 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3996 "wrong connector dpms state\n");
3997 WARN(connector->base.encoder != &encoder->base,
3998 "active connector not linked to encoder\n");
3999 WARN(!encoder->connectors_active,
4000 "encoder->connectors_active not set\n");
4002 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4003 WARN(!encoder_enabled, "encoder not enabled\n");
4004 if (WARN_ON(!encoder->base.crtc))
4007 crtc = encoder->base.crtc;
4009 WARN(!crtc->enabled, "crtc not enabled\n");
4010 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4011 WARN(pipe != to_intel_crtc(crtc)->pipe,
4012 "encoder active on the wrong pipe\n");
4016 /* Even simpler default implementation, if there's really no special case to
4018 void intel_connector_dpms(struct drm_connector *connector, int mode)
4020 struct intel_encoder *encoder = intel_attached_encoder(connector);
4022 /* All the simple cases only support two dpms states. */
4023 if (mode != DRM_MODE_DPMS_ON)
4024 mode = DRM_MODE_DPMS_OFF;
4026 if (mode == connector->dpms)
4029 connector->dpms = mode;
4031 /* Only need to change hw state when actually enabled */
4032 if (encoder->base.crtc)
4033 intel_encoder_dpms(encoder, mode);
4035 WARN_ON(encoder->connectors_active != false);
4037 intel_modeset_check_state(connector->dev);
4040 /* Simple connector->get_hw_state implementation for encoders that support only
4041 * one connector and no cloning and hence the encoder state determines the state
4042 * of the connector. */
4043 bool intel_connector_get_hw_state(struct intel_connector *connector)
4046 struct intel_encoder *encoder = connector->encoder;
4048 return encoder->get_hw_state(encoder, &pipe);
4051 static bool intel_crtc_compute_config(struct drm_crtc *crtc,
4052 struct intel_crtc_config *pipe_config)
4054 struct drm_device *dev = crtc->dev;
4055 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4057 if (HAS_PCH_SPLIT(dev)) {
4058 /* FDI link clock is fixed at 2.7G */
4059 if (pipe_config->requested_mode.clock * 3
4060 > IRONLAKE_FDI_FREQ * 4)
4064 /* All interlaced capable intel hw wants timings in frames. Note though
4065 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4066 * timings, so we need to be careful not to clobber these.*/
4067 if (!pipe_config->timings_set)
4068 drm_mode_set_crtcinfo(adjusted_mode, 0);
4070 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4071 * with a hsync front porch of 0.
4073 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4074 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4077 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4078 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4079 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4080 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4082 pipe_config->pipe_bpp = 8*3;
4088 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4090 return 400000; /* FIXME */
4093 static int i945_get_display_clock_speed(struct drm_device *dev)
4098 static int i915_get_display_clock_speed(struct drm_device *dev)
4103 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4108 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4112 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4114 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4117 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4118 case GC_DISPLAY_CLOCK_333_MHZ:
4121 case GC_DISPLAY_CLOCK_190_200_MHZ:
4127 static int i865_get_display_clock_speed(struct drm_device *dev)
4132 static int i855_get_display_clock_speed(struct drm_device *dev)
4135 /* Assume that the hardware is in the high speed state. This
4136 * should be the default.
4138 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4139 case GC_CLOCK_133_200:
4140 case GC_CLOCK_100_200:
4142 case GC_CLOCK_166_250:
4144 case GC_CLOCK_100_133:
4148 /* Shouldn't happen */
4152 static int i830_get_display_clock_speed(struct drm_device *dev)
4158 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4160 while (*num > 0xffffff || *den > 0xffffff) {
4167 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4168 int pixel_clock, int link_clock,
4169 struct intel_link_m_n *m_n)
4172 m_n->gmch_m = bits_per_pixel * pixel_clock;
4173 m_n->gmch_n = link_clock * nlanes * 8;
4174 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4175 m_n->link_m = pixel_clock;
4176 m_n->link_n = link_clock;
4177 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4180 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4182 if (i915_panel_use_ssc >= 0)
4183 return i915_panel_use_ssc != 0;
4184 return dev_priv->lvds_use_ssc
4185 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4188 static int vlv_get_refclk(struct drm_crtc *crtc)
4190 struct drm_device *dev = crtc->dev;
4191 struct drm_i915_private *dev_priv = dev->dev_private;
4192 int refclk = 27000; /* for DP & HDMI */
4194 return 100000; /* only one validated so far */
4196 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4198 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4199 if (intel_panel_use_ssc(dev_priv))
4203 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4210 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4212 struct drm_device *dev = crtc->dev;
4213 struct drm_i915_private *dev_priv = dev->dev_private;
4216 if (IS_VALLEYVIEW(dev)) {
4217 refclk = vlv_get_refclk(crtc);
4218 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4219 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4220 refclk = dev_priv->lvds_ssc_freq * 1000;
4221 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4223 } else if (!IS_GEN2(dev)) {
4232 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
4234 unsigned dotclock = crtc->config.adjusted_mode.clock;
4235 struct dpll *clock = &crtc->config.dpll;
4237 /* SDVO TV has fixed PLL values depend on its clock range,
4238 this mirrors vbios setting. */
4239 if (dotclock >= 100000 && dotclock < 140500) {
4245 } else if (dotclock >= 140500 && dotclock <= 200000) {
4253 crtc->config.clock_set = true;
4256 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4257 intel_clock_t *reduced_clock)
4259 struct drm_device *dev = crtc->base.dev;
4260 struct drm_i915_private *dev_priv = dev->dev_private;
4261 int pipe = crtc->pipe;
4263 struct dpll *clock = &crtc->config.dpll;
4265 if (IS_PINEVIEW(dev)) {
4266 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4268 fp2 = (1 << reduced_clock->n) << 16 |
4269 reduced_clock->m1 << 8 | reduced_clock->m2;
4271 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4273 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4277 I915_WRITE(FP0(pipe), fp);
4279 crtc->lowfreq_avail = false;
4280 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4281 reduced_clock && i915_powersave) {
4282 I915_WRITE(FP1(pipe), fp2);
4283 crtc->lowfreq_avail = true;
4285 I915_WRITE(FP1(pipe), fp);
4289 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4294 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4295 * and set it to a reasonable value instead.
4297 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4298 reg_val &= 0xffffff00;
4299 reg_val |= 0x00000030;
4300 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4302 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4303 reg_val &= 0x8cffffff;
4304 reg_val = 0x8c000000;
4305 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4307 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4308 reg_val &= 0xffffff00;
4309 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4311 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4312 reg_val &= 0x00ffffff;
4313 reg_val |= 0xb0000000;
4314 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4317 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4319 if (crtc->config.has_pch_encoder)
4320 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4322 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4325 static void vlv_update_pll(struct intel_crtc *crtc)
4327 struct drm_device *dev = crtc->base.dev;
4328 struct drm_i915_private *dev_priv = dev->dev_private;
4329 struct drm_display_mode *adjusted_mode =
4330 &crtc->config.adjusted_mode;
4331 struct intel_encoder *encoder;
4332 int pipe = crtc->pipe;
4334 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4336 u32 coreclk, reg_val, temp;
4338 mutex_lock(&dev_priv->dpio_lock);
4340 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4342 bestn = crtc->config.dpll.n;
4343 bestm1 = crtc->config.dpll.m1;
4344 bestm2 = crtc->config.dpll.m2;
4345 bestp1 = crtc->config.dpll.p1;
4346 bestp2 = crtc->config.dpll.p2;
4348 /* See eDP HDMI DPIO driver vbios notes doc */
4350 /* PLL B needs special handling */
4352 vlv_pllb_recal_opamp(dev_priv);
4354 /* Set up Tx target for periodic Rcomp update */
4355 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4357 /* Disable target IRef on PLL */
4358 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4359 reg_val &= 0x00ffffff;
4360 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4362 /* Disable fast lock */
4363 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4365 /* Set idtafcrecal before PLL is enabled */
4366 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4367 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4368 mdiv |= ((bestn << DPIO_N_SHIFT));
4369 mdiv |= (1 << DPIO_K_SHIFT);
4370 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
4371 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4372 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4373 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4374 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4376 mdiv |= DPIO_ENABLE_CALIBRATION;
4377 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4379 /* Set HBR and RBR LPF coefficients */
4380 if (adjusted_mode->clock == 162000 ||
4381 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4382 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4385 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4388 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4389 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4390 /* Use SSC source */
4392 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4395 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4397 } else { /* HDMI or VGA */
4398 /* Use bend source */
4400 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4403 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4407 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4408 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4409 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4410 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4411 coreclk |= 0x01000000;
4412 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4414 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4416 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4417 if (encoder->pre_pll_enable)
4418 encoder->pre_pll_enable(encoder);
4420 /* Enable DPIO clock input */
4421 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4422 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4424 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4426 dpll |= DPLL_VCO_ENABLE;
4427 I915_WRITE(DPLL(pipe), dpll);
4428 POSTING_READ(DPLL(pipe));
4431 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4432 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4436 if (crtc->config.pixel_multiplier > 1) {
4437 temp = (crtc->config.pixel_multiplier - 1)
4438 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4441 I915_WRITE(DPLL_MD(pipe), temp);
4442 POSTING_READ(DPLL_MD(pipe));
4445 if (crtc->config.has_dp_encoder)
4446 intel_dp_set_m_n(crtc);
4448 mutex_unlock(&dev_priv->dpio_lock);
4451 static void i9xx_update_pll(struct intel_crtc *crtc,
4452 intel_clock_t *reduced_clock,
4455 struct drm_device *dev = crtc->base.dev;
4456 struct drm_i915_private *dev_priv = dev->dev_private;
4457 struct intel_encoder *encoder;
4458 int pipe = crtc->pipe;
4461 struct dpll *clock = &crtc->config.dpll;
4463 i9xx_update_pll_dividers(crtc, reduced_clock);
4465 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4466 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4468 dpll = DPLL_VGA_MODE_DIS;
4470 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4471 dpll |= DPLLB_MODE_LVDS;
4473 dpll |= DPLLB_MODE_DAC_SERIAL;
4476 if ((crtc->config.pixel_multiplier > 1) &&
4477 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4478 dpll |= (crtc->config.pixel_multiplier - 1)
4479 << SDVO_MULTIPLIER_SHIFT_HIRES;
4481 dpll |= DPLL_DVO_HIGH_SPEED;
4483 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4484 dpll |= DPLL_DVO_HIGH_SPEED;
4486 /* compute bitmask from p1 value */
4487 if (IS_PINEVIEW(dev))
4488 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4490 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4491 if (IS_G4X(dev) && reduced_clock)
4492 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4494 switch (clock->p2) {
4496 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4499 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4502 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4505 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4508 if (INTEL_INFO(dev)->gen >= 4)
4509 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4511 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4512 dpll |= PLL_REF_INPUT_TVCLKINBC;
4513 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4514 /* XXX: just matching BIOS for now */
4515 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4517 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4518 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4519 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4521 dpll |= PLL_REF_INPUT_DREFCLK;
4523 dpll |= DPLL_VCO_ENABLE;
4524 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4525 POSTING_READ(DPLL(pipe));
4528 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4529 if (encoder->pre_pll_enable)
4530 encoder->pre_pll_enable(encoder);
4532 if (crtc->config.has_dp_encoder)
4533 intel_dp_set_m_n(crtc);
4535 I915_WRITE(DPLL(pipe), dpll);
4537 /* Wait for the clocks to stabilize. */
4538 POSTING_READ(DPLL(pipe));
4541 if (INTEL_INFO(dev)->gen >= 4) {
4545 if (crtc->config.pixel_multiplier > 1) {
4546 temp = (crtc->config.pixel_multiplier - 1)
4547 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4550 I915_WRITE(DPLL_MD(pipe), temp);
4552 /* The pixel multiplier can only be updated once the
4553 * DPLL is enabled and the clocks are stable.
4555 * So write it again.
4557 I915_WRITE(DPLL(pipe), dpll);
4561 static void i8xx_update_pll(struct intel_crtc *crtc,
4562 struct drm_display_mode *adjusted_mode,
4563 intel_clock_t *reduced_clock,
4566 struct drm_device *dev = crtc->base.dev;
4567 struct drm_i915_private *dev_priv = dev->dev_private;
4568 struct intel_encoder *encoder;
4569 int pipe = crtc->pipe;
4571 struct dpll *clock = &crtc->config.dpll;
4573 i9xx_update_pll_dividers(crtc, reduced_clock);
4575 dpll = DPLL_VGA_MODE_DIS;
4577 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4578 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4581 dpll |= PLL_P1_DIVIDE_BY_TWO;
4583 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4585 dpll |= PLL_P2_DIVIDE_BY_4;
4588 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4589 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4590 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4592 dpll |= PLL_REF_INPUT_DREFCLK;
4594 dpll |= DPLL_VCO_ENABLE;
4595 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4596 POSTING_READ(DPLL(pipe));
4599 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4600 if (encoder->pre_pll_enable)
4601 encoder->pre_pll_enable(encoder);
4603 I915_WRITE(DPLL(pipe), dpll);
4605 /* Wait for the clocks to stabilize. */
4606 POSTING_READ(DPLL(pipe));
4609 /* The pixel multiplier can only be updated once the
4610 * DPLL is enabled and the clocks are stable.
4612 * So write it again.
4614 I915_WRITE(DPLL(pipe), dpll);
4617 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4618 struct drm_display_mode *mode,
4619 struct drm_display_mode *adjusted_mode)
4621 struct drm_device *dev = intel_crtc->base.dev;
4622 struct drm_i915_private *dev_priv = dev->dev_private;
4623 enum pipe pipe = intel_crtc->pipe;
4624 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4625 uint32_t vsyncshift;
4627 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4628 /* the chip adds 2 halflines automatically */
4629 adjusted_mode->crtc_vtotal -= 1;
4630 adjusted_mode->crtc_vblank_end -= 1;
4631 vsyncshift = adjusted_mode->crtc_hsync_start
4632 - adjusted_mode->crtc_htotal / 2;
4637 if (INTEL_INFO(dev)->gen > 3)
4638 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4640 I915_WRITE(HTOTAL(cpu_transcoder),
4641 (adjusted_mode->crtc_hdisplay - 1) |
4642 ((adjusted_mode->crtc_htotal - 1) << 16));
4643 I915_WRITE(HBLANK(cpu_transcoder),
4644 (adjusted_mode->crtc_hblank_start - 1) |
4645 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4646 I915_WRITE(HSYNC(cpu_transcoder),
4647 (adjusted_mode->crtc_hsync_start - 1) |
4648 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4650 I915_WRITE(VTOTAL(cpu_transcoder),
4651 (adjusted_mode->crtc_vdisplay - 1) |
4652 ((adjusted_mode->crtc_vtotal - 1) << 16));
4653 I915_WRITE(VBLANK(cpu_transcoder),
4654 (adjusted_mode->crtc_vblank_start - 1) |
4655 ((adjusted_mode->crtc_vblank_end - 1) << 16));
4656 I915_WRITE(VSYNC(cpu_transcoder),
4657 (adjusted_mode->crtc_vsync_start - 1) |
4658 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4660 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4661 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4662 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4664 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4665 (pipe == PIPE_B || pipe == PIPE_C))
4666 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4668 /* pipesrc controls the size that is scaled from, which should
4669 * always be the user's requested size.
4671 I915_WRITE(PIPESRC(pipe),
4672 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4675 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4677 struct drm_device *dev = intel_crtc->base.dev;
4678 struct drm_i915_private *dev_priv = dev->dev_private;
4681 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4683 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4684 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4687 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4690 if (intel_crtc->config.requested_mode.clock >
4691 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4692 pipeconf |= PIPECONF_DOUBLE_WIDE;
4694 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4697 /* default to 8bpc */
4698 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
4699 if (intel_crtc->config.has_dp_encoder) {
4700 if (intel_crtc->config.dither) {
4701 pipeconf |= PIPECONF_6BPC |
4702 PIPECONF_DITHER_EN |
4703 PIPECONF_DITHER_TYPE_SP;
4707 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(&intel_crtc->base,
4708 INTEL_OUTPUT_EDP)) {
4709 if (intel_crtc->config.dither) {
4710 pipeconf |= PIPECONF_6BPC |
4712 I965_PIPECONF_ACTIVE;
4716 if (HAS_PIPE_CXSR(dev)) {
4717 if (intel_crtc->lowfreq_avail) {
4718 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4719 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4721 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4722 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4726 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4727 if (!IS_GEN2(dev) &&
4728 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4729 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4731 pipeconf |= PIPECONF_PROGRESSIVE;
4733 if (IS_VALLEYVIEW(dev)) {
4734 if (intel_crtc->config.limited_color_range)
4735 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4737 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4740 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4741 POSTING_READ(PIPECONF(intel_crtc->pipe));
4744 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4746 struct drm_framebuffer *fb)
4748 struct drm_device *dev = crtc->dev;
4749 struct drm_i915_private *dev_priv = dev->dev_private;
4750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4751 struct drm_display_mode *adjusted_mode =
4752 &intel_crtc->config.adjusted_mode;
4753 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4754 int pipe = intel_crtc->pipe;
4755 int plane = intel_crtc->plane;
4756 int refclk, num_connectors = 0;
4757 intel_clock_t clock, reduced_clock;
4759 bool ok, has_reduced_clock = false, is_sdvo = false;
4760 bool is_lvds = false, is_tv = false;
4761 struct intel_encoder *encoder;
4762 const intel_limit_t *limit;
4765 for_each_encoder_on_crtc(dev, crtc, encoder) {
4766 switch (encoder->type) {
4767 case INTEL_OUTPUT_LVDS:
4770 case INTEL_OUTPUT_SDVO:
4771 case INTEL_OUTPUT_HDMI:
4773 if (encoder->needs_tv_clock)
4776 case INTEL_OUTPUT_TVOUT:
4784 refclk = i9xx_get_refclk(crtc, num_connectors);
4787 * Returns a set of divisors for the desired target clock with the given
4788 * refclk, or FALSE. The returned values represent the clock equation:
4789 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4791 limit = intel_limit(crtc, refclk);
4792 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4795 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4799 /* Ensure that the cursor is valid for the new mode before changing... */
4800 intel_crtc_update_cursor(crtc, true);
4802 if (is_lvds && dev_priv->lvds_downclock_avail) {
4804 * Ensure we match the reduced clock's P to the target clock.
4805 * If the clocks don't match, we can't switch the display clock
4806 * by using the FP0/FP1. In such case we will disable the LVDS
4807 * downclock feature.
4809 has_reduced_clock = limit->find_pll(limit, crtc,
4810 dev_priv->lvds_downclock,
4815 /* Compat-code for transition, will disappear. */
4816 if (!intel_crtc->config.clock_set) {
4817 intel_crtc->config.dpll.n = clock.n;
4818 intel_crtc->config.dpll.m1 = clock.m1;
4819 intel_crtc->config.dpll.m2 = clock.m2;
4820 intel_crtc->config.dpll.p1 = clock.p1;
4821 intel_crtc->config.dpll.p2 = clock.p2;
4824 if (is_sdvo && is_tv)
4825 i9xx_adjust_sdvo_tv_clock(intel_crtc);
4828 i8xx_update_pll(intel_crtc, adjusted_mode,
4829 has_reduced_clock ? &reduced_clock : NULL,
4831 else if (IS_VALLEYVIEW(dev))
4832 vlv_update_pll(intel_crtc);
4834 i9xx_update_pll(intel_crtc,
4835 has_reduced_clock ? &reduced_clock : NULL,
4838 /* Set up the display plane register */
4839 dspcntr = DISPPLANE_GAMMA_ENABLE;
4841 if (!IS_VALLEYVIEW(dev)) {
4843 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4845 dspcntr |= DISPPLANE_SEL_PIPE_B;
4848 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
4849 drm_mode_debug_printmodeline(mode);
4851 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4853 /* pipesrc and dspsize control the size that is scaled from,
4854 * which should always be the user's requested size.
4856 I915_WRITE(DSPSIZE(plane),
4857 ((mode->vdisplay - 1) << 16) |
4858 (mode->hdisplay - 1));
4859 I915_WRITE(DSPPOS(plane), 0);
4861 i9xx_set_pipeconf(intel_crtc);
4863 I915_WRITE(DSPCNTR(plane), dspcntr);
4864 POSTING_READ(DSPCNTR(plane));
4866 ret = intel_pipe_set_base(crtc, x, y, fb);
4868 intel_update_watermarks(dev);
4873 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4874 struct intel_crtc_config *pipe_config)
4876 struct drm_device *dev = crtc->base.dev;
4877 struct drm_i915_private *dev_priv = dev->dev_private;
4880 tmp = I915_READ(PIPECONF(crtc->pipe));
4881 if (!(tmp & PIPECONF_ENABLE))
4887 static void ironlake_init_pch_refclk(struct drm_device *dev)
4889 struct drm_i915_private *dev_priv = dev->dev_private;
4890 struct drm_mode_config *mode_config = &dev->mode_config;
4891 struct intel_encoder *encoder;
4893 bool has_lvds = false;
4894 bool has_cpu_edp = false;
4895 bool has_pch_edp = false;
4896 bool has_panel = false;
4897 bool has_ck505 = false;
4898 bool can_ssc = false;
4900 /* We need to take the global config into account */
4901 list_for_each_entry(encoder, &mode_config->encoder_list,
4903 switch (encoder->type) {
4904 case INTEL_OUTPUT_LVDS:
4908 case INTEL_OUTPUT_EDP:
4910 if (intel_encoder_is_pch_edp(&encoder->base))
4918 if (HAS_PCH_IBX(dev)) {
4919 has_ck505 = dev_priv->display_clock_mode;
4920 can_ssc = has_ck505;
4926 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4927 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4930 /* Ironlake: try to setup display ref clock before DPLL
4931 * enabling. This is only under driver's control after
4932 * PCH B stepping, previous chipset stepping should be
4933 * ignoring this setting.
4935 val = I915_READ(PCH_DREF_CONTROL);
4937 /* As we must carefully and slowly disable/enable each source in turn,
4938 * compute the final state we want first and check if we need to
4939 * make any changes at all.
4942 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4944 final |= DREF_NONSPREAD_CK505_ENABLE;
4946 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4948 final &= ~DREF_SSC_SOURCE_MASK;
4949 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4950 final &= ~DREF_SSC1_ENABLE;
4953 final |= DREF_SSC_SOURCE_ENABLE;
4955 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4956 final |= DREF_SSC1_ENABLE;
4959 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4960 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4962 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4964 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4966 final |= DREF_SSC_SOURCE_DISABLE;
4967 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4973 /* Always enable nonspread source */
4974 val &= ~DREF_NONSPREAD_SOURCE_MASK;
4977 val |= DREF_NONSPREAD_CK505_ENABLE;
4979 val |= DREF_NONSPREAD_SOURCE_ENABLE;
4982 val &= ~DREF_SSC_SOURCE_MASK;
4983 val |= DREF_SSC_SOURCE_ENABLE;
4985 /* SSC must be turned on before enabling the CPU output */
4986 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4987 DRM_DEBUG_KMS("Using SSC on panel\n");
4988 val |= DREF_SSC1_ENABLE;
4990 val &= ~DREF_SSC1_ENABLE;
4992 /* Get SSC going before enabling the outputs */
4993 I915_WRITE(PCH_DREF_CONTROL, val);
4994 POSTING_READ(PCH_DREF_CONTROL);
4997 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4999 /* Enable CPU source on CPU attached eDP */
5001 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5002 DRM_DEBUG_KMS("Using SSC on eDP\n");
5003 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5006 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5008 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5010 I915_WRITE(PCH_DREF_CONTROL, val);
5011 POSTING_READ(PCH_DREF_CONTROL);
5014 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5016 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5018 /* Turn off CPU output */
5019 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5021 I915_WRITE(PCH_DREF_CONTROL, val);
5022 POSTING_READ(PCH_DREF_CONTROL);
5025 /* Turn off the SSC source */
5026 val &= ~DREF_SSC_SOURCE_MASK;
5027 val |= DREF_SSC_SOURCE_DISABLE;
5030 val &= ~DREF_SSC1_ENABLE;
5032 I915_WRITE(PCH_DREF_CONTROL, val);
5033 POSTING_READ(PCH_DREF_CONTROL);
5037 BUG_ON(val != final);
5040 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5041 static void lpt_init_pch_refclk(struct drm_device *dev)
5043 struct drm_i915_private *dev_priv = dev->dev_private;
5044 struct drm_mode_config *mode_config = &dev->mode_config;
5045 struct intel_encoder *encoder;
5046 bool has_vga = false;
5047 bool is_sdv = false;
5050 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5051 switch (encoder->type) {
5052 case INTEL_OUTPUT_ANALOG:
5061 mutex_lock(&dev_priv->dpio_lock);
5063 /* XXX: Rip out SDV support once Haswell ships for real. */
5064 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5067 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5068 tmp &= ~SBI_SSCCTL_DISABLE;
5069 tmp |= SBI_SSCCTL_PATHALT;
5070 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5074 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5075 tmp &= ~SBI_SSCCTL_PATHALT;
5076 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5079 tmp = I915_READ(SOUTH_CHICKEN2);
5080 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5081 I915_WRITE(SOUTH_CHICKEN2, tmp);
5083 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5084 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5085 DRM_ERROR("FDI mPHY reset assert timeout\n");
5087 tmp = I915_READ(SOUTH_CHICKEN2);
5088 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5089 I915_WRITE(SOUTH_CHICKEN2, tmp);
5091 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5092 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5094 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5097 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5098 tmp &= ~(0xFF << 24);
5099 tmp |= (0x12 << 24);
5100 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5103 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5105 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5108 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5110 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5112 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5114 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5117 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5118 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5119 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5121 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5122 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5123 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5125 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5127 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5129 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5131 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5134 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5135 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5136 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5138 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5139 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5140 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5143 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5146 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5148 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5151 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5154 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5157 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5159 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5162 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5164 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5165 tmp &= ~(0xFF << 16);
5166 tmp |= (0x1C << 16);
5167 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5169 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5170 tmp &= ~(0xFF << 16);
5171 tmp |= (0x1C << 16);
5172 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5175 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5177 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5179 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5181 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5183 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5184 tmp &= ~(0xF << 28);
5186 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5188 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5189 tmp &= ~(0xF << 28);
5191 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5194 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5195 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5196 tmp |= SBI_DBUFF0_ENABLE;
5197 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5199 mutex_unlock(&dev_priv->dpio_lock);
5203 * Initialize reference clocks when the driver loads
5205 void intel_init_pch_refclk(struct drm_device *dev)
5207 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5208 ironlake_init_pch_refclk(dev);
5209 else if (HAS_PCH_LPT(dev))
5210 lpt_init_pch_refclk(dev);
5213 static int ironlake_get_refclk(struct drm_crtc *crtc)
5215 struct drm_device *dev = crtc->dev;
5216 struct drm_i915_private *dev_priv = dev->dev_private;
5217 struct intel_encoder *encoder;
5218 struct intel_encoder *edp_encoder = NULL;
5219 int num_connectors = 0;
5220 bool is_lvds = false;
5222 for_each_encoder_on_crtc(dev, crtc, encoder) {
5223 switch (encoder->type) {
5224 case INTEL_OUTPUT_LVDS:
5227 case INTEL_OUTPUT_EDP:
5228 edp_encoder = encoder;
5234 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5235 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5236 dev_priv->lvds_ssc_freq);
5237 return dev_priv->lvds_ssc_freq * 1000;
5243 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
5244 struct drm_display_mode *adjusted_mode,
5247 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5248 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5249 int pipe = intel_crtc->pipe;
5252 val = I915_READ(PIPECONF(pipe));
5254 val &= ~PIPECONF_BPC_MASK;
5255 switch (intel_crtc->config.pipe_bpp) {
5257 val |= PIPECONF_6BPC;
5260 val |= PIPECONF_8BPC;
5263 val |= PIPECONF_10BPC;
5266 val |= PIPECONF_12BPC;
5269 /* Case prevented by intel_choose_pipe_bpp_dither. */
5273 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5275 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5277 val &= ~PIPECONF_INTERLACE_MASK;
5278 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5279 val |= PIPECONF_INTERLACED_ILK;
5281 val |= PIPECONF_PROGRESSIVE;
5283 if (intel_crtc->config.limited_color_range)
5284 val |= PIPECONF_COLOR_RANGE_SELECT;
5286 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5288 I915_WRITE(PIPECONF(pipe), val);
5289 POSTING_READ(PIPECONF(pipe));
5293 * Set up the pipe CSC unit.
5295 * Currently only full range RGB to limited range RGB conversion
5296 * is supported, but eventually this should handle various
5297 * RGB<->YCbCr scenarios as well.
5299 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5301 struct drm_device *dev = crtc->dev;
5302 struct drm_i915_private *dev_priv = dev->dev_private;
5303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5304 int pipe = intel_crtc->pipe;
5305 uint16_t coeff = 0x7800; /* 1.0 */
5308 * TODO: Check what kind of values actually come out of the pipe
5309 * with these coeff/postoff values and adjust to get the best
5310 * accuracy. Perhaps we even need to take the bpc value into
5314 if (intel_crtc->config.limited_color_range)
5315 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5318 * GY/GU and RY/RU should be the other way around according
5319 * to BSpec, but reality doesn't agree. Just set them up in
5320 * a way that results in the correct picture.
5322 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5323 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5325 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5326 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5328 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5329 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5331 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5332 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5333 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5335 if (INTEL_INFO(dev)->gen > 6) {
5336 uint16_t postoff = 0;
5338 if (intel_crtc->config.limited_color_range)
5339 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5341 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5342 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5343 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5345 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5347 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5349 if (intel_crtc->config.limited_color_range)
5350 mode |= CSC_BLACK_SCREEN_OFFSET;
5352 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5356 static void haswell_set_pipeconf(struct drm_crtc *crtc,
5357 struct drm_display_mode *adjusted_mode,
5360 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5362 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5365 val = I915_READ(PIPECONF(cpu_transcoder));
5367 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5369 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5371 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5372 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5373 val |= PIPECONF_INTERLACED_ILK;
5375 val |= PIPECONF_PROGRESSIVE;
5377 I915_WRITE(PIPECONF(cpu_transcoder), val);
5378 POSTING_READ(PIPECONF(cpu_transcoder));
5381 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5382 struct drm_display_mode *adjusted_mode,
5383 intel_clock_t *clock,
5384 bool *has_reduced_clock,
5385 intel_clock_t *reduced_clock)
5387 struct drm_device *dev = crtc->dev;
5388 struct drm_i915_private *dev_priv = dev->dev_private;
5389 struct intel_encoder *intel_encoder;
5391 const intel_limit_t *limit;
5392 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5394 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5395 switch (intel_encoder->type) {
5396 case INTEL_OUTPUT_LVDS:
5399 case INTEL_OUTPUT_SDVO:
5400 case INTEL_OUTPUT_HDMI:
5402 if (intel_encoder->needs_tv_clock)
5405 case INTEL_OUTPUT_TVOUT:
5411 refclk = ironlake_get_refclk(crtc);
5414 * Returns a set of divisors for the desired target clock with the given
5415 * refclk, or FALSE. The returned values represent the clock equation:
5416 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5418 limit = intel_limit(crtc, refclk);
5419 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5424 if (is_lvds && dev_priv->lvds_downclock_avail) {
5426 * Ensure we match the reduced clock's P to the target clock.
5427 * If the clocks don't match, we can't switch the display clock
5428 * by using the FP0/FP1. In such case we will disable the LVDS
5429 * downclock feature.
5431 *has_reduced_clock = limit->find_pll(limit, crtc,
5432 dev_priv->lvds_downclock,
5438 if (is_sdvo && is_tv)
5439 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
5444 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5446 struct drm_i915_private *dev_priv = dev->dev_private;
5449 temp = I915_READ(SOUTH_CHICKEN1);
5450 if (temp & FDI_BC_BIFURCATION_SELECT)
5453 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5454 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5456 temp |= FDI_BC_BIFURCATION_SELECT;
5457 DRM_DEBUG_KMS("enabling fdi C rx\n");
5458 I915_WRITE(SOUTH_CHICKEN1, temp);
5459 POSTING_READ(SOUTH_CHICKEN1);
5462 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5464 struct drm_device *dev = intel_crtc->base.dev;
5465 struct drm_i915_private *dev_priv = dev->dev_private;
5466 struct intel_crtc *pipe_B_crtc =
5467 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5469 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5470 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5471 if (intel_crtc->fdi_lanes > 4) {
5472 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5473 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5474 /* Clamp lanes to avoid programming the hw with bogus values. */
5475 intel_crtc->fdi_lanes = 4;
5480 if (INTEL_INFO(dev)->num_pipes == 2)
5483 switch (intel_crtc->pipe) {
5487 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5488 intel_crtc->fdi_lanes > 2) {
5489 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5490 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5491 /* Clamp lanes to avoid programming the hw with bogus values. */
5492 intel_crtc->fdi_lanes = 2;
5497 if (intel_crtc->fdi_lanes > 2)
5498 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5500 cpt_enable_fdi_bc_bifurcation(dev);
5504 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5505 if (intel_crtc->fdi_lanes > 2) {
5506 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5507 pipe_name(intel_crtc->pipe), intel_crtc->fdi_lanes);
5508 /* Clamp lanes to avoid programming the hw with bogus values. */
5509 intel_crtc->fdi_lanes = 2;
5514 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5518 cpt_enable_fdi_bc_bifurcation(dev);
5526 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5529 * Account for spread spectrum to avoid
5530 * oversubscribing the link. Max center spread
5531 * is 2.5%; use 5% for safety's sake.
5533 u32 bps = target_clock * bpp * 21 / 20;
5534 return bps / (link_bw * 8) + 1;
5537 void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5538 struct intel_link_m_n *m_n)
5540 struct drm_device *dev = crtc->base.dev;
5541 struct drm_i915_private *dev_priv = dev->dev_private;
5542 int pipe = crtc->pipe;
5544 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5545 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5546 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5547 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5550 void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5551 struct intel_link_m_n *m_n)
5553 struct drm_device *dev = crtc->base.dev;
5554 struct drm_i915_private *dev_priv = dev->dev_private;
5555 int pipe = crtc->pipe;
5556 enum transcoder transcoder = crtc->config.cpu_transcoder;
5558 if (INTEL_INFO(dev)->gen >= 5) {
5559 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5560 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5561 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5562 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5564 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5565 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5566 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5567 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5571 static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5573 struct drm_device *dev = crtc->dev;
5574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5575 struct drm_display_mode *adjusted_mode =
5576 &intel_crtc->config.adjusted_mode;
5577 struct intel_link_m_n m_n = {0};
5578 int target_clock, lane, link_bw;
5580 /* FDI is a binary signal running at ~2.7GHz, encoding
5581 * each output octet as 10 bits. The actual frequency
5582 * is stored as a divider into a 100MHz clock, and the
5583 * mode pixel clock is stored in units of 1KHz.
5584 * Hence the bw of each lane in terms of the mode signal
5587 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5589 if (intel_crtc->config.pixel_target_clock)
5590 target_clock = intel_crtc->config.pixel_target_clock;
5592 target_clock = adjusted_mode->clock;
5594 lane = ironlake_get_lanes_required(target_clock, link_bw,
5595 intel_crtc->config.pipe_bpp);
5597 intel_crtc->fdi_lanes = lane;
5599 if (intel_crtc->config.pixel_multiplier > 1)
5600 link_bw *= intel_crtc->config.pixel_multiplier;
5601 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5604 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
5607 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5608 intel_clock_t *clock, u32 *fp,
5609 intel_clock_t *reduced_clock, u32 *fp2)
5611 struct drm_crtc *crtc = &intel_crtc->base;
5612 struct drm_device *dev = crtc->dev;
5613 struct drm_i915_private *dev_priv = dev->dev_private;
5614 struct intel_encoder *intel_encoder;
5616 int factor, num_connectors = 0;
5617 bool is_lvds = false, is_sdvo = false, is_tv = false;
5619 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5620 switch (intel_encoder->type) {
5621 case INTEL_OUTPUT_LVDS:
5624 case INTEL_OUTPUT_SDVO:
5625 case INTEL_OUTPUT_HDMI:
5627 if (intel_encoder->needs_tv_clock)
5630 case INTEL_OUTPUT_TVOUT:
5638 /* Enable autotuning of the PLL clock (if permissible) */
5641 if ((intel_panel_use_ssc(dev_priv) &&
5642 dev_priv->lvds_ssc_freq == 100) ||
5643 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5645 } else if (is_sdvo && is_tv)
5648 if (clock->m < factor * clock->n)
5651 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5657 dpll |= DPLLB_MODE_LVDS;
5659 dpll |= DPLLB_MODE_DAC_SERIAL;
5661 if (intel_crtc->config.pixel_multiplier > 1) {
5662 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5663 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5665 dpll |= DPLL_DVO_HIGH_SPEED;
5667 if (intel_crtc->config.has_dp_encoder &&
5668 intel_crtc->config.has_pch_encoder)
5669 dpll |= DPLL_DVO_HIGH_SPEED;
5671 /* compute bitmask from p1 value */
5672 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5674 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5676 switch (clock->p2) {
5678 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5681 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5684 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5687 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5691 if (is_sdvo && is_tv)
5692 dpll |= PLL_REF_INPUT_TVCLKINBC;
5694 /* XXX: just matching BIOS for now */
5695 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
5697 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5698 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5700 dpll |= PLL_REF_INPUT_DREFCLK;
5705 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5707 struct drm_framebuffer *fb)
5709 struct drm_device *dev = crtc->dev;
5710 struct drm_i915_private *dev_priv = dev->dev_private;
5711 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5712 struct drm_display_mode *adjusted_mode =
5713 &intel_crtc->config.adjusted_mode;
5714 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5715 int pipe = intel_crtc->pipe;
5716 int plane = intel_crtc->plane;
5717 int num_connectors = 0;
5718 intel_clock_t clock, reduced_clock;
5719 u32 dpll, fp = 0, fp2 = 0;
5720 bool ok, has_reduced_clock = false;
5721 bool is_lvds = false;
5722 struct intel_encoder *encoder;
5724 bool dither, fdi_config_ok;
5726 for_each_encoder_on_crtc(dev, crtc, encoder) {
5727 switch (encoder->type) {
5728 case INTEL_OUTPUT_LVDS:
5736 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5737 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5739 intel_crtc->config.cpu_transcoder = pipe;
5741 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5742 &has_reduced_clock, &reduced_clock);
5744 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5747 /* Compat-code for transition, will disappear. */
5748 if (!intel_crtc->config.clock_set) {
5749 intel_crtc->config.dpll.n = clock.n;
5750 intel_crtc->config.dpll.m1 = clock.m1;
5751 intel_crtc->config.dpll.m2 = clock.m2;
5752 intel_crtc->config.dpll.p1 = clock.p1;
5753 intel_crtc->config.dpll.p2 = clock.p2;
5756 /* Ensure that the cursor is valid for the new mode before changing... */
5757 intel_crtc_update_cursor(crtc, true);
5759 /* determine panel color depth */
5760 dither = intel_crtc->config.dither;
5761 if (is_lvds && dev_priv->lvds_dither)
5764 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5765 if (has_reduced_clock)
5766 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5769 dpll = ironlake_compute_dpll(intel_crtc, &clock, &fp, &reduced_clock,
5770 has_reduced_clock ? &fp2 : NULL);
5772 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5773 drm_mode_debug_printmodeline(mode);
5775 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5776 if (intel_crtc->config.has_pch_encoder) {
5777 struct intel_pch_pll *pll;
5779 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5781 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5786 intel_put_pch_pll(intel_crtc);
5788 if (intel_crtc->config.has_dp_encoder)
5789 intel_dp_set_m_n(intel_crtc);
5791 for_each_encoder_on_crtc(dev, crtc, encoder)
5792 if (encoder->pre_pll_enable)
5793 encoder->pre_pll_enable(encoder);
5795 if (intel_crtc->pch_pll) {
5796 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5798 /* Wait for the clocks to stabilize. */
5799 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5802 /* The pixel multiplier can only be updated once the
5803 * DPLL is enabled and the clocks are stable.
5805 * So write it again.
5807 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5810 intel_crtc->lowfreq_avail = false;
5811 if (intel_crtc->pch_pll) {
5812 if (is_lvds && has_reduced_clock && i915_powersave) {
5813 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5814 intel_crtc->lowfreq_avail = true;
5816 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5820 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5822 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5823 * ironlake_check_fdi_lanes. */
5824 intel_crtc->fdi_lanes = 0;
5825 if (intel_crtc->config.has_pch_encoder)
5826 ironlake_fdi_set_m_n(crtc);
5828 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5830 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5832 /* Set up the display plane register */
5833 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5834 POSTING_READ(DSPCNTR(plane));
5836 ret = intel_pipe_set_base(crtc, x, y, fb);
5838 intel_update_watermarks(dev);
5840 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5842 return fdi_config_ok ? ret : -EINVAL;
5845 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5846 struct intel_crtc_config *pipe_config)
5848 struct drm_device *dev = crtc->base.dev;
5849 struct drm_i915_private *dev_priv = dev->dev_private;
5852 tmp = I915_READ(PIPECONF(crtc->pipe));
5853 if (!(tmp & PIPECONF_ENABLE))
5856 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5857 pipe_config->has_pch_encoder = true;
5862 static void haswell_modeset_global_resources(struct drm_device *dev)
5864 struct drm_i915_private *dev_priv = dev->dev_private;
5865 bool enable = false;
5866 struct intel_crtc *crtc;
5867 struct intel_encoder *encoder;
5869 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5870 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5872 /* XXX: Should check for edp transcoder here, but thanks to init
5873 * sequence that's not yet available. Just in case desktop eDP
5874 * on PORT D is possible on haswell, too. */
5877 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5879 if (encoder->type != INTEL_OUTPUT_EDP &&
5880 encoder->connectors_active)
5884 /* Even the eDP panel fitter is outside the always-on well. */
5885 if (dev_priv->pch_pf_size)
5888 intel_set_power_well(dev, enable);
5891 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5893 struct drm_framebuffer *fb)
5895 struct drm_device *dev = crtc->dev;
5896 struct drm_i915_private *dev_priv = dev->dev_private;
5897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5898 struct drm_display_mode *adjusted_mode =
5899 &intel_crtc->config.adjusted_mode;
5900 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5901 int pipe = intel_crtc->pipe;
5902 int plane = intel_crtc->plane;
5903 int num_connectors = 0;
5904 bool is_cpu_edp = false;
5905 struct intel_encoder *encoder;
5909 for_each_encoder_on_crtc(dev, crtc, encoder) {
5910 switch (encoder->type) {
5911 case INTEL_OUTPUT_EDP:
5912 if (!intel_encoder_is_pch_edp(&encoder->base))
5921 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
5923 intel_crtc->config.cpu_transcoder = pipe;
5925 /* We are not sure yet this won't happen. */
5926 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5927 INTEL_PCH_TYPE(dev));
5929 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5930 num_connectors, pipe_name(pipe));
5932 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
5933 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5935 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5937 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5940 /* Ensure that the cursor is valid for the new mode before changing... */
5941 intel_crtc_update_cursor(crtc, true);
5943 /* determine panel color depth */
5944 dither = intel_crtc->config.dither;
5946 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5947 drm_mode_debug_printmodeline(mode);
5949 if (intel_crtc->config.has_dp_encoder)
5950 intel_dp_set_m_n(intel_crtc);
5952 intel_crtc->lowfreq_avail = false;
5954 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5956 if (intel_crtc->config.has_pch_encoder)
5957 ironlake_fdi_set_m_n(crtc);
5959 haswell_set_pipeconf(crtc, adjusted_mode, dither);
5961 intel_set_pipe_csc(crtc);
5963 /* Set up the display plane register */
5964 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5965 POSTING_READ(DSPCNTR(plane));
5967 ret = intel_pipe_set_base(crtc, x, y, fb);
5969 intel_update_watermarks(dev);
5971 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5976 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5977 struct intel_crtc_config *pipe_config)
5979 struct drm_device *dev = crtc->base.dev;
5980 struct drm_i915_private *dev_priv = dev->dev_private;
5981 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
5984 if (!intel_using_power_well(dev_priv->dev) &&
5985 cpu_transcoder != TRANSCODER_EDP)
5988 tmp = I915_READ(PIPECONF(cpu_transcoder));
5989 if (!(tmp & PIPECONF_ENABLE))
5993 * aswell has only FDI/PCH transcoder A. It is which is connected to
5994 * DDI E. So just check whether this pipe is wired to DDI E and whether
5995 * the PCH transcoder is on.
5997 tmp = I915_READ(TRANS_DDI_FUNC_CTL(crtc->pipe));
5998 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5999 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
6000 pipe_config->has_pch_encoder = true;
6006 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6008 struct drm_framebuffer *fb)
6010 struct drm_device *dev = crtc->dev;
6011 struct drm_i915_private *dev_priv = dev->dev_private;
6012 struct drm_encoder_helper_funcs *encoder_funcs;
6013 struct intel_encoder *encoder;
6014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6015 struct drm_display_mode *adjusted_mode =
6016 &intel_crtc->config.adjusted_mode;
6017 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6018 int pipe = intel_crtc->pipe;
6021 drm_vblank_pre_modeset(dev, pipe);
6023 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6025 drm_vblank_post_modeset(dev, pipe);
6030 for_each_encoder_on_crtc(dev, crtc, encoder) {
6031 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6032 encoder->base.base.id,
6033 drm_get_encoder_name(&encoder->base),
6034 mode->base.id, mode->name);
6035 if (encoder->mode_set) {
6036 encoder->mode_set(encoder);
6038 encoder_funcs = encoder->base.helper_private;
6039 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6046 static bool intel_eld_uptodate(struct drm_connector *connector,
6047 int reg_eldv, uint32_t bits_eldv,
6048 int reg_elda, uint32_t bits_elda,
6051 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6052 uint8_t *eld = connector->eld;
6055 i = I915_READ(reg_eldv);
6064 i = I915_READ(reg_elda);
6066 I915_WRITE(reg_elda, i);
6068 for (i = 0; i < eld[2]; i++)
6069 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6075 static void g4x_write_eld(struct drm_connector *connector,
6076 struct drm_crtc *crtc)
6078 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6079 uint8_t *eld = connector->eld;
6084 i = I915_READ(G4X_AUD_VID_DID);
6086 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6087 eldv = G4X_ELDV_DEVCL_DEVBLC;
6089 eldv = G4X_ELDV_DEVCTG;
6091 if (intel_eld_uptodate(connector,
6092 G4X_AUD_CNTL_ST, eldv,
6093 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6094 G4X_HDMIW_HDMIEDID))
6097 i = I915_READ(G4X_AUD_CNTL_ST);
6098 i &= ~(eldv | G4X_ELD_ADDR);
6099 len = (i >> 9) & 0x1f; /* ELD buffer size */
6100 I915_WRITE(G4X_AUD_CNTL_ST, i);
6105 len = min_t(uint8_t, eld[2], len);
6106 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6107 for (i = 0; i < len; i++)
6108 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6110 i = I915_READ(G4X_AUD_CNTL_ST);
6112 I915_WRITE(G4X_AUD_CNTL_ST, i);
6115 static void haswell_write_eld(struct drm_connector *connector,
6116 struct drm_crtc *crtc)
6118 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6119 uint8_t *eld = connector->eld;
6120 struct drm_device *dev = crtc->dev;
6121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6125 int pipe = to_intel_crtc(crtc)->pipe;
6128 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6129 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6130 int aud_config = HSW_AUD_CFG(pipe);
6131 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6134 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6136 /* Audio output enable */
6137 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6138 tmp = I915_READ(aud_cntrl_st2);
6139 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6140 I915_WRITE(aud_cntrl_st2, tmp);
6142 /* Wait for 1 vertical blank */
6143 intel_wait_for_vblank(dev, pipe);
6145 /* Set ELD valid state */
6146 tmp = I915_READ(aud_cntrl_st2);
6147 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6148 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6149 I915_WRITE(aud_cntrl_st2, tmp);
6150 tmp = I915_READ(aud_cntrl_st2);
6151 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6153 /* Enable HDMI mode */
6154 tmp = I915_READ(aud_config);
6155 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6156 /* clear N_programing_enable and N_value_index */
6157 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6158 I915_WRITE(aud_config, tmp);
6160 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6162 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6163 intel_crtc->eld_vld = true;
6165 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6166 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6167 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6168 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6170 I915_WRITE(aud_config, 0);
6172 if (intel_eld_uptodate(connector,
6173 aud_cntrl_st2, eldv,
6174 aud_cntl_st, IBX_ELD_ADDRESS,
6178 i = I915_READ(aud_cntrl_st2);
6180 I915_WRITE(aud_cntrl_st2, i);
6185 i = I915_READ(aud_cntl_st);
6186 i &= ~IBX_ELD_ADDRESS;
6187 I915_WRITE(aud_cntl_st, i);
6188 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6189 DRM_DEBUG_DRIVER("port num:%d\n", i);
6191 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6192 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6193 for (i = 0; i < len; i++)
6194 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6196 i = I915_READ(aud_cntrl_st2);
6198 I915_WRITE(aud_cntrl_st2, i);
6202 static void ironlake_write_eld(struct drm_connector *connector,
6203 struct drm_crtc *crtc)
6205 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6206 uint8_t *eld = connector->eld;
6214 int pipe = to_intel_crtc(crtc)->pipe;
6216 if (HAS_PCH_IBX(connector->dev)) {
6217 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6218 aud_config = IBX_AUD_CFG(pipe);
6219 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6220 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6222 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6223 aud_config = CPT_AUD_CFG(pipe);
6224 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6225 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6228 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6230 i = I915_READ(aud_cntl_st);
6231 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6233 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6234 /* operate blindly on all ports */
6235 eldv = IBX_ELD_VALIDB;
6236 eldv |= IBX_ELD_VALIDB << 4;
6237 eldv |= IBX_ELD_VALIDB << 8;
6239 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6240 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6243 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6244 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6245 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6246 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6248 I915_WRITE(aud_config, 0);
6250 if (intel_eld_uptodate(connector,
6251 aud_cntrl_st2, eldv,
6252 aud_cntl_st, IBX_ELD_ADDRESS,
6256 i = I915_READ(aud_cntrl_st2);
6258 I915_WRITE(aud_cntrl_st2, i);
6263 i = I915_READ(aud_cntl_st);
6264 i &= ~IBX_ELD_ADDRESS;
6265 I915_WRITE(aud_cntl_st, i);
6267 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6268 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6269 for (i = 0; i < len; i++)
6270 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6272 i = I915_READ(aud_cntrl_st2);
6274 I915_WRITE(aud_cntrl_st2, i);
6277 void intel_write_eld(struct drm_encoder *encoder,
6278 struct drm_display_mode *mode)
6280 struct drm_crtc *crtc = encoder->crtc;
6281 struct drm_connector *connector;
6282 struct drm_device *dev = encoder->dev;
6283 struct drm_i915_private *dev_priv = dev->dev_private;
6285 connector = drm_select_eld(encoder, mode);
6289 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6291 drm_get_connector_name(connector),
6292 connector->encoder->base.id,
6293 drm_get_encoder_name(connector->encoder));
6295 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6297 if (dev_priv->display.write_eld)
6298 dev_priv->display.write_eld(connector, crtc);
6301 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6302 void intel_crtc_load_lut(struct drm_crtc *crtc)
6304 struct drm_device *dev = crtc->dev;
6305 struct drm_i915_private *dev_priv = dev->dev_private;
6306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6307 int palreg = PALETTE(intel_crtc->pipe);
6310 /* The clocks have to be on to load the palette. */
6311 if (!crtc->enabled || !intel_crtc->active)
6314 /* use legacy palette for Ironlake */
6315 if (HAS_PCH_SPLIT(dev))
6316 palreg = LGC_PALETTE(intel_crtc->pipe);
6318 for (i = 0; i < 256; i++) {
6319 I915_WRITE(palreg + 4 * i,
6320 (intel_crtc->lut_r[i] << 16) |
6321 (intel_crtc->lut_g[i] << 8) |
6322 intel_crtc->lut_b[i]);
6326 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6328 struct drm_device *dev = crtc->dev;
6329 struct drm_i915_private *dev_priv = dev->dev_private;
6330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6331 bool visible = base != 0;
6334 if (intel_crtc->cursor_visible == visible)
6337 cntl = I915_READ(_CURACNTR);
6339 /* On these chipsets we can only modify the base whilst
6340 * the cursor is disabled.
6342 I915_WRITE(_CURABASE, base);
6344 cntl &= ~(CURSOR_FORMAT_MASK);
6345 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6346 cntl |= CURSOR_ENABLE |
6347 CURSOR_GAMMA_ENABLE |
6350 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6351 I915_WRITE(_CURACNTR, cntl);
6353 intel_crtc->cursor_visible = visible;
6356 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6358 struct drm_device *dev = crtc->dev;
6359 struct drm_i915_private *dev_priv = dev->dev_private;
6360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6361 int pipe = intel_crtc->pipe;
6362 bool visible = base != 0;
6364 if (intel_crtc->cursor_visible != visible) {
6365 uint32_t cntl = I915_READ(CURCNTR(pipe));
6367 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6368 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6369 cntl |= pipe << 28; /* Connect to correct pipe */
6371 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6372 cntl |= CURSOR_MODE_DISABLE;
6374 I915_WRITE(CURCNTR(pipe), cntl);
6376 intel_crtc->cursor_visible = visible;
6378 /* and commit changes on next vblank */
6379 I915_WRITE(CURBASE(pipe), base);
6382 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6384 struct drm_device *dev = crtc->dev;
6385 struct drm_i915_private *dev_priv = dev->dev_private;
6386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6387 int pipe = intel_crtc->pipe;
6388 bool visible = base != 0;
6390 if (intel_crtc->cursor_visible != visible) {
6391 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6393 cntl &= ~CURSOR_MODE;
6394 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6396 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6397 cntl |= CURSOR_MODE_DISABLE;
6399 if (IS_HASWELL(dev))
6400 cntl |= CURSOR_PIPE_CSC_ENABLE;
6401 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6403 intel_crtc->cursor_visible = visible;
6405 /* and commit changes on next vblank */
6406 I915_WRITE(CURBASE_IVB(pipe), base);
6409 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6410 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6413 struct drm_device *dev = crtc->dev;
6414 struct drm_i915_private *dev_priv = dev->dev_private;
6415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6416 int pipe = intel_crtc->pipe;
6417 int x = intel_crtc->cursor_x;
6418 int y = intel_crtc->cursor_y;
6424 if (on && crtc->enabled && crtc->fb) {
6425 base = intel_crtc->cursor_addr;
6426 if (x > (int) crtc->fb->width)
6429 if (y > (int) crtc->fb->height)
6435 if (x + intel_crtc->cursor_width < 0)
6438 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6441 pos |= x << CURSOR_X_SHIFT;
6444 if (y + intel_crtc->cursor_height < 0)
6447 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6450 pos |= y << CURSOR_Y_SHIFT;
6452 visible = base != 0;
6453 if (!visible && !intel_crtc->cursor_visible)
6456 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6457 I915_WRITE(CURPOS_IVB(pipe), pos);
6458 ivb_update_cursor(crtc, base);
6460 I915_WRITE(CURPOS(pipe), pos);
6461 if (IS_845G(dev) || IS_I865G(dev))
6462 i845_update_cursor(crtc, base);
6464 i9xx_update_cursor(crtc, base);
6468 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6469 struct drm_file *file,
6471 uint32_t width, uint32_t height)
6473 struct drm_device *dev = crtc->dev;
6474 struct drm_i915_private *dev_priv = dev->dev_private;
6475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6476 struct drm_i915_gem_object *obj;
6480 /* if we want to turn off the cursor ignore width and height */
6482 DRM_DEBUG_KMS("cursor off\n");
6485 mutex_lock(&dev->struct_mutex);
6489 /* Currently we only support 64x64 cursors */
6490 if (width != 64 || height != 64) {
6491 DRM_ERROR("we currently only support 64x64 cursors\n");
6495 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6496 if (&obj->base == NULL)
6499 if (obj->base.size < width * height * 4) {
6500 DRM_ERROR("buffer is to small\n");
6505 /* we only need to pin inside GTT if cursor is non-phy */
6506 mutex_lock(&dev->struct_mutex);
6507 if (!dev_priv->info->cursor_needs_physical) {
6510 if (obj->tiling_mode) {
6511 DRM_ERROR("cursor cannot be tiled\n");
6516 /* Note that the w/a also requires 2 PTE of padding following
6517 * the bo. We currently fill all unused PTE with the shadow
6518 * page and so we should always have valid PTE following the
6519 * cursor preventing the VT-d warning.
6522 if (need_vtd_wa(dev))
6523 alignment = 64*1024;
6525 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6527 DRM_ERROR("failed to move cursor bo into the GTT\n");
6531 ret = i915_gem_object_put_fence(obj);
6533 DRM_ERROR("failed to release fence for cursor");
6537 addr = obj->gtt_offset;
6539 int align = IS_I830(dev) ? 16 * 1024 : 256;
6540 ret = i915_gem_attach_phys_object(dev, obj,
6541 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6544 DRM_ERROR("failed to attach phys object\n");
6547 addr = obj->phys_obj->handle->busaddr;
6551 I915_WRITE(CURSIZE, (height << 12) | width);
6554 if (intel_crtc->cursor_bo) {
6555 if (dev_priv->info->cursor_needs_physical) {
6556 if (intel_crtc->cursor_bo != obj)
6557 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6559 i915_gem_object_unpin(intel_crtc->cursor_bo);
6560 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6563 mutex_unlock(&dev->struct_mutex);
6565 intel_crtc->cursor_addr = addr;
6566 intel_crtc->cursor_bo = obj;
6567 intel_crtc->cursor_width = width;
6568 intel_crtc->cursor_height = height;
6570 intel_crtc_update_cursor(crtc, true);
6574 i915_gem_object_unpin(obj);
6576 mutex_unlock(&dev->struct_mutex);
6578 drm_gem_object_unreference_unlocked(&obj->base);
6582 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6584 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6586 intel_crtc->cursor_x = x;
6587 intel_crtc->cursor_y = y;
6589 intel_crtc_update_cursor(crtc, true);
6594 /** Sets the color ramps on behalf of RandR */
6595 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6596 u16 blue, int regno)
6598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6600 intel_crtc->lut_r[regno] = red >> 8;
6601 intel_crtc->lut_g[regno] = green >> 8;
6602 intel_crtc->lut_b[regno] = blue >> 8;
6605 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6606 u16 *blue, int regno)
6608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6610 *red = intel_crtc->lut_r[regno] << 8;
6611 *green = intel_crtc->lut_g[regno] << 8;
6612 *blue = intel_crtc->lut_b[regno] << 8;
6615 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6616 u16 *blue, uint32_t start, uint32_t size)
6618 int end = (start + size > 256) ? 256 : start + size, i;
6619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6621 for (i = start; i < end; i++) {
6622 intel_crtc->lut_r[i] = red[i] >> 8;
6623 intel_crtc->lut_g[i] = green[i] >> 8;
6624 intel_crtc->lut_b[i] = blue[i] >> 8;
6627 intel_crtc_load_lut(crtc);
6630 /* VESA 640x480x72Hz mode to set on the pipe */
6631 static struct drm_display_mode load_detect_mode = {
6632 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6633 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6636 static struct drm_framebuffer *
6637 intel_framebuffer_create(struct drm_device *dev,
6638 struct drm_mode_fb_cmd2 *mode_cmd,
6639 struct drm_i915_gem_object *obj)
6641 struct intel_framebuffer *intel_fb;
6644 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6646 drm_gem_object_unreference_unlocked(&obj->base);
6647 return ERR_PTR(-ENOMEM);
6650 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6652 drm_gem_object_unreference_unlocked(&obj->base);
6654 return ERR_PTR(ret);
6657 return &intel_fb->base;
6661 intel_framebuffer_pitch_for_width(int width, int bpp)
6663 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6664 return ALIGN(pitch, 64);
6668 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6670 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6671 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6674 static struct drm_framebuffer *
6675 intel_framebuffer_create_for_mode(struct drm_device *dev,
6676 struct drm_display_mode *mode,
6679 struct drm_i915_gem_object *obj;
6680 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6682 obj = i915_gem_alloc_object(dev,
6683 intel_framebuffer_size_for_mode(mode, bpp));
6685 return ERR_PTR(-ENOMEM);
6687 mode_cmd.width = mode->hdisplay;
6688 mode_cmd.height = mode->vdisplay;
6689 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6691 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6693 return intel_framebuffer_create(dev, &mode_cmd, obj);
6696 static struct drm_framebuffer *
6697 mode_fits_in_fbdev(struct drm_device *dev,
6698 struct drm_display_mode *mode)
6700 struct drm_i915_private *dev_priv = dev->dev_private;
6701 struct drm_i915_gem_object *obj;
6702 struct drm_framebuffer *fb;
6704 if (dev_priv->fbdev == NULL)
6707 obj = dev_priv->fbdev->ifb.obj;
6711 fb = &dev_priv->fbdev->ifb.base;
6712 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6713 fb->bits_per_pixel))
6716 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6722 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6723 struct drm_display_mode *mode,
6724 struct intel_load_detect_pipe *old)
6726 struct intel_crtc *intel_crtc;
6727 struct intel_encoder *intel_encoder =
6728 intel_attached_encoder(connector);
6729 struct drm_crtc *possible_crtc;
6730 struct drm_encoder *encoder = &intel_encoder->base;
6731 struct drm_crtc *crtc = NULL;
6732 struct drm_device *dev = encoder->dev;
6733 struct drm_framebuffer *fb;
6736 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6737 connector->base.id, drm_get_connector_name(connector),
6738 encoder->base.id, drm_get_encoder_name(encoder));
6741 * Algorithm gets a little messy:
6743 * - if the connector already has an assigned crtc, use it (but make
6744 * sure it's on first)
6746 * - try to find the first unused crtc that can drive this connector,
6747 * and use that if we find one
6750 /* See if we already have a CRTC for this connector */
6751 if (encoder->crtc) {
6752 crtc = encoder->crtc;
6754 mutex_lock(&crtc->mutex);
6756 old->dpms_mode = connector->dpms;
6757 old->load_detect_temp = false;
6759 /* Make sure the crtc and connector are running */
6760 if (connector->dpms != DRM_MODE_DPMS_ON)
6761 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6766 /* Find an unused one (if possible) */
6767 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6769 if (!(encoder->possible_crtcs & (1 << i)))
6771 if (!possible_crtc->enabled) {
6772 crtc = possible_crtc;
6778 * If we didn't find an unused CRTC, don't use any.
6781 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6785 mutex_lock(&crtc->mutex);
6786 intel_encoder->new_crtc = to_intel_crtc(crtc);
6787 to_intel_connector(connector)->new_encoder = intel_encoder;
6789 intel_crtc = to_intel_crtc(crtc);
6790 old->dpms_mode = connector->dpms;
6791 old->load_detect_temp = true;
6792 old->release_fb = NULL;
6795 mode = &load_detect_mode;
6797 /* We need a framebuffer large enough to accommodate all accesses
6798 * that the plane may generate whilst we perform load detection.
6799 * We can not rely on the fbcon either being present (we get called
6800 * during its initialisation to detect all boot displays, or it may
6801 * not even exist) or that it is large enough to satisfy the
6804 fb = mode_fits_in_fbdev(dev, mode);
6806 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6807 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6808 old->release_fb = fb;
6810 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6812 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6813 mutex_unlock(&crtc->mutex);
6817 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6818 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6819 if (old->release_fb)
6820 old->release_fb->funcs->destroy(old->release_fb);
6821 mutex_unlock(&crtc->mutex);
6825 /* let the connector get through one full cycle before testing */
6826 intel_wait_for_vblank(dev, intel_crtc->pipe);
6830 void intel_release_load_detect_pipe(struct drm_connector *connector,
6831 struct intel_load_detect_pipe *old)
6833 struct intel_encoder *intel_encoder =
6834 intel_attached_encoder(connector);
6835 struct drm_encoder *encoder = &intel_encoder->base;
6836 struct drm_crtc *crtc = encoder->crtc;
6838 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6839 connector->base.id, drm_get_connector_name(connector),
6840 encoder->base.id, drm_get_encoder_name(encoder));
6842 if (old->load_detect_temp) {
6843 to_intel_connector(connector)->new_encoder = NULL;
6844 intel_encoder->new_crtc = NULL;
6845 intel_set_mode(crtc, NULL, 0, 0, NULL);
6847 if (old->release_fb) {
6848 drm_framebuffer_unregister_private(old->release_fb);
6849 drm_framebuffer_unreference(old->release_fb);
6852 mutex_unlock(&crtc->mutex);
6856 /* Switch crtc and encoder back off if necessary */
6857 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6858 connector->funcs->dpms(connector, old->dpms_mode);
6860 mutex_unlock(&crtc->mutex);
6863 /* Returns the clock of the currently programmed mode of the given pipe. */
6864 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6866 struct drm_i915_private *dev_priv = dev->dev_private;
6867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6868 int pipe = intel_crtc->pipe;
6869 u32 dpll = I915_READ(DPLL(pipe));
6871 intel_clock_t clock;
6873 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6874 fp = I915_READ(FP0(pipe));
6876 fp = I915_READ(FP1(pipe));
6878 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6879 if (IS_PINEVIEW(dev)) {
6880 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6881 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6883 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6884 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6887 if (!IS_GEN2(dev)) {
6888 if (IS_PINEVIEW(dev))
6889 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6890 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6892 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6893 DPLL_FPA01_P1_POST_DIV_SHIFT);
6895 switch (dpll & DPLL_MODE_MASK) {
6896 case DPLLB_MODE_DAC_SERIAL:
6897 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6900 case DPLLB_MODE_LVDS:
6901 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6905 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6906 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6910 /* XXX: Handle the 100Mhz refclk */
6911 intel_clock(dev, 96000, &clock);
6913 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6916 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6917 DPLL_FPA01_P1_POST_DIV_SHIFT);
6920 if ((dpll & PLL_REF_INPUT_MASK) ==
6921 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6922 /* XXX: might not be 66MHz */
6923 intel_clock(dev, 66000, &clock);
6925 intel_clock(dev, 48000, &clock);
6927 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6930 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6931 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6933 if (dpll & PLL_P2_DIVIDE_BY_4)
6938 intel_clock(dev, 48000, &clock);
6942 /* XXX: It would be nice to validate the clocks, but we can't reuse
6943 * i830PllIsValid() because it relies on the xf86_config connector
6944 * configuration being accurate, which it isn't necessarily.
6950 /** Returns the currently programmed mode of the given pipe. */
6951 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6952 struct drm_crtc *crtc)
6954 struct drm_i915_private *dev_priv = dev->dev_private;
6955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6956 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6957 struct drm_display_mode *mode;
6958 int htot = I915_READ(HTOTAL(cpu_transcoder));
6959 int hsync = I915_READ(HSYNC(cpu_transcoder));
6960 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6961 int vsync = I915_READ(VSYNC(cpu_transcoder));
6963 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6967 mode->clock = intel_crtc_clock_get(dev, crtc);
6968 mode->hdisplay = (htot & 0xffff) + 1;
6969 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6970 mode->hsync_start = (hsync & 0xffff) + 1;
6971 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6972 mode->vdisplay = (vtot & 0xffff) + 1;
6973 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6974 mode->vsync_start = (vsync & 0xffff) + 1;
6975 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6977 drm_mode_set_name(mode);
6982 static void intel_increase_pllclock(struct drm_crtc *crtc)
6984 struct drm_device *dev = crtc->dev;
6985 drm_i915_private_t *dev_priv = dev->dev_private;
6986 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6987 int pipe = intel_crtc->pipe;
6988 int dpll_reg = DPLL(pipe);
6991 if (HAS_PCH_SPLIT(dev))
6994 if (!dev_priv->lvds_downclock_avail)
6997 dpll = I915_READ(dpll_reg);
6998 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6999 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7001 assert_panel_unlocked(dev_priv, pipe);
7003 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7004 I915_WRITE(dpll_reg, dpll);
7005 intel_wait_for_vblank(dev, pipe);
7007 dpll = I915_READ(dpll_reg);
7008 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7009 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7013 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7015 struct drm_device *dev = crtc->dev;
7016 drm_i915_private_t *dev_priv = dev->dev_private;
7017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7019 if (HAS_PCH_SPLIT(dev))
7022 if (!dev_priv->lvds_downclock_avail)
7026 * Since this is called by a timer, we should never get here in
7029 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7030 int pipe = intel_crtc->pipe;
7031 int dpll_reg = DPLL(pipe);
7034 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7036 assert_panel_unlocked(dev_priv, pipe);
7038 dpll = I915_READ(dpll_reg);
7039 dpll |= DISPLAY_RATE_SELECT_FPA1;
7040 I915_WRITE(dpll_reg, dpll);
7041 intel_wait_for_vblank(dev, pipe);
7042 dpll = I915_READ(dpll_reg);
7043 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7044 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7049 void intel_mark_busy(struct drm_device *dev)
7051 i915_update_gfx_val(dev->dev_private);
7054 void intel_mark_idle(struct drm_device *dev)
7056 struct drm_crtc *crtc;
7058 if (!i915_powersave)
7061 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7065 intel_decrease_pllclock(crtc);
7069 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7071 struct drm_device *dev = obj->base.dev;
7072 struct drm_crtc *crtc;
7074 if (!i915_powersave)
7077 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7081 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7082 intel_increase_pllclock(crtc);
7086 static void intel_crtc_destroy(struct drm_crtc *crtc)
7088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7089 struct drm_device *dev = crtc->dev;
7090 struct intel_unpin_work *work;
7091 unsigned long flags;
7093 spin_lock_irqsave(&dev->event_lock, flags);
7094 work = intel_crtc->unpin_work;
7095 intel_crtc->unpin_work = NULL;
7096 spin_unlock_irqrestore(&dev->event_lock, flags);
7099 cancel_work_sync(&work->work);
7103 drm_crtc_cleanup(crtc);
7108 static void intel_unpin_work_fn(struct work_struct *__work)
7110 struct intel_unpin_work *work =
7111 container_of(__work, struct intel_unpin_work, work);
7112 struct drm_device *dev = work->crtc->dev;
7114 mutex_lock(&dev->struct_mutex);
7115 intel_unpin_fb_obj(work->old_fb_obj);
7116 drm_gem_object_unreference(&work->pending_flip_obj->base);
7117 drm_gem_object_unreference(&work->old_fb_obj->base);
7119 intel_update_fbc(dev);
7120 mutex_unlock(&dev->struct_mutex);
7122 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7123 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7128 static void do_intel_finish_page_flip(struct drm_device *dev,
7129 struct drm_crtc *crtc)
7131 drm_i915_private_t *dev_priv = dev->dev_private;
7132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7133 struct intel_unpin_work *work;
7134 unsigned long flags;
7136 /* Ignore early vblank irqs */
7137 if (intel_crtc == NULL)
7140 spin_lock_irqsave(&dev->event_lock, flags);
7141 work = intel_crtc->unpin_work;
7143 /* Ensure we don't miss a work->pending update ... */
7146 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7147 spin_unlock_irqrestore(&dev->event_lock, flags);
7151 /* and that the unpin work is consistent wrt ->pending. */
7154 intel_crtc->unpin_work = NULL;
7157 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7159 drm_vblank_put(dev, intel_crtc->pipe);
7161 spin_unlock_irqrestore(&dev->event_lock, flags);
7163 wake_up_all(&dev_priv->pending_flip_queue);
7165 queue_work(dev_priv->wq, &work->work);
7167 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7170 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7172 drm_i915_private_t *dev_priv = dev->dev_private;
7173 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7175 do_intel_finish_page_flip(dev, crtc);
7178 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7180 drm_i915_private_t *dev_priv = dev->dev_private;
7181 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7183 do_intel_finish_page_flip(dev, crtc);
7186 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7188 drm_i915_private_t *dev_priv = dev->dev_private;
7189 struct intel_crtc *intel_crtc =
7190 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7191 unsigned long flags;
7193 /* NB: An MMIO update of the plane base pointer will also
7194 * generate a page-flip completion irq, i.e. every modeset
7195 * is also accompanied by a spurious intel_prepare_page_flip().
7197 spin_lock_irqsave(&dev->event_lock, flags);
7198 if (intel_crtc->unpin_work)
7199 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7200 spin_unlock_irqrestore(&dev->event_lock, flags);
7203 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7205 /* Ensure that the work item is consistent when activating it ... */
7207 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7208 /* and that it is marked active as soon as the irq could fire. */
7212 static int intel_gen2_queue_flip(struct drm_device *dev,
7213 struct drm_crtc *crtc,
7214 struct drm_framebuffer *fb,
7215 struct drm_i915_gem_object *obj)
7217 struct drm_i915_private *dev_priv = dev->dev_private;
7218 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7220 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7223 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7227 ret = intel_ring_begin(ring, 6);
7231 /* Can't queue multiple flips, so wait for the previous
7232 * one to finish before executing the next.
7234 if (intel_crtc->plane)
7235 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7237 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7238 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7239 intel_ring_emit(ring, MI_NOOP);
7240 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7241 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7242 intel_ring_emit(ring, fb->pitches[0]);
7243 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7244 intel_ring_emit(ring, 0); /* aux display base address, unused */
7246 intel_mark_page_flip_active(intel_crtc);
7247 intel_ring_advance(ring);
7251 intel_unpin_fb_obj(obj);
7256 static int intel_gen3_queue_flip(struct drm_device *dev,
7257 struct drm_crtc *crtc,
7258 struct drm_framebuffer *fb,
7259 struct drm_i915_gem_object *obj)
7261 struct drm_i915_private *dev_priv = dev->dev_private;
7262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7264 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7267 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7271 ret = intel_ring_begin(ring, 6);
7275 if (intel_crtc->plane)
7276 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7278 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7279 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7280 intel_ring_emit(ring, MI_NOOP);
7281 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7282 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7283 intel_ring_emit(ring, fb->pitches[0]);
7284 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7285 intel_ring_emit(ring, MI_NOOP);
7287 intel_mark_page_flip_active(intel_crtc);
7288 intel_ring_advance(ring);
7292 intel_unpin_fb_obj(obj);
7297 static int intel_gen4_queue_flip(struct drm_device *dev,
7298 struct drm_crtc *crtc,
7299 struct drm_framebuffer *fb,
7300 struct drm_i915_gem_object *obj)
7302 struct drm_i915_private *dev_priv = dev->dev_private;
7303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7304 uint32_t pf, pipesrc;
7305 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7308 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7312 ret = intel_ring_begin(ring, 4);
7316 /* i965+ uses the linear or tiled offsets from the
7317 * Display Registers (which do not change across a page-flip)
7318 * so we need only reprogram the base address.
7320 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7321 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7322 intel_ring_emit(ring, fb->pitches[0]);
7323 intel_ring_emit(ring,
7324 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7327 /* XXX Enabling the panel-fitter across page-flip is so far
7328 * untested on non-native modes, so ignore it for now.
7329 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7332 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7333 intel_ring_emit(ring, pf | pipesrc);
7335 intel_mark_page_flip_active(intel_crtc);
7336 intel_ring_advance(ring);
7340 intel_unpin_fb_obj(obj);
7345 static int intel_gen6_queue_flip(struct drm_device *dev,
7346 struct drm_crtc *crtc,
7347 struct drm_framebuffer *fb,
7348 struct drm_i915_gem_object *obj)
7350 struct drm_i915_private *dev_priv = dev->dev_private;
7351 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7352 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7353 uint32_t pf, pipesrc;
7356 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7360 ret = intel_ring_begin(ring, 4);
7364 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7365 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7366 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7367 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7369 /* Contrary to the suggestions in the documentation,
7370 * "Enable Panel Fitter" does not seem to be required when page
7371 * flipping with a non-native mode, and worse causes a normal
7373 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7376 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7377 intel_ring_emit(ring, pf | pipesrc);
7379 intel_mark_page_flip_active(intel_crtc);
7380 intel_ring_advance(ring);
7384 intel_unpin_fb_obj(obj);
7390 * On gen7 we currently use the blit ring because (in early silicon at least)
7391 * the render ring doesn't give us interrpts for page flip completion, which
7392 * means clients will hang after the first flip is queued. Fortunately the
7393 * blit ring generates interrupts properly, so use it instead.
7395 static int intel_gen7_queue_flip(struct drm_device *dev,
7396 struct drm_crtc *crtc,
7397 struct drm_framebuffer *fb,
7398 struct drm_i915_gem_object *obj)
7400 struct drm_i915_private *dev_priv = dev->dev_private;
7401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7402 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7403 uint32_t plane_bit = 0;
7406 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7410 switch(intel_crtc->plane) {
7412 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7415 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7418 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7421 WARN_ONCE(1, "unknown plane in flip command\n");
7426 ret = intel_ring_begin(ring, 4);
7430 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7431 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7432 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7433 intel_ring_emit(ring, (MI_NOOP));
7435 intel_mark_page_flip_active(intel_crtc);
7436 intel_ring_advance(ring);
7440 intel_unpin_fb_obj(obj);
7445 static int intel_default_queue_flip(struct drm_device *dev,
7446 struct drm_crtc *crtc,
7447 struct drm_framebuffer *fb,
7448 struct drm_i915_gem_object *obj)
7453 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7454 struct drm_framebuffer *fb,
7455 struct drm_pending_vblank_event *event)
7457 struct drm_device *dev = crtc->dev;
7458 struct drm_i915_private *dev_priv = dev->dev_private;
7459 struct drm_framebuffer *old_fb = crtc->fb;
7460 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7462 struct intel_unpin_work *work;
7463 unsigned long flags;
7466 /* Can't change pixel format via MI display flips. */
7467 if (fb->pixel_format != crtc->fb->pixel_format)
7471 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7472 * Note that pitch changes could also affect these register.
7474 if (INTEL_INFO(dev)->gen > 3 &&
7475 (fb->offsets[0] != crtc->fb->offsets[0] ||
7476 fb->pitches[0] != crtc->fb->pitches[0]))
7479 work = kzalloc(sizeof *work, GFP_KERNEL);
7483 work->event = event;
7485 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7486 INIT_WORK(&work->work, intel_unpin_work_fn);
7488 ret = drm_vblank_get(dev, intel_crtc->pipe);
7492 /* We borrow the event spin lock for protecting unpin_work */
7493 spin_lock_irqsave(&dev->event_lock, flags);
7494 if (intel_crtc->unpin_work) {
7495 spin_unlock_irqrestore(&dev->event_lock, flags);
7497 drm_vblank_put(dev, intel_crtc->pipe);
7499 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7502 intel_crtc->unpin_work = work;
7503 spin_unlock_irqrestore(&dev->event_lock, flags);
7505 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7506 flush_workqueue(dev_priv->wq);
7508 ret = i915_mutex_lock_interruptible(dev);
7512 /* Reference the objects for the scheduled work. */
7513 drm_gem_object_reference(&work->old_fb_obj->base);
7514 drm_gem_object_reference(&obj->base);
7518 work->pending_flip_obj = obj;
7520 work->enable_stall_check = true;
7522 atomic_inc(&intel_crtc->unpin_work_count);
7523 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7525 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7527 goto cleanup_pending;
7529 intel_disable_fbc(dev);
7530 intel_mark_fb_busy(obj);
7531 mutex_unlock(&dev->struct_mutex);
7533 trace_i915_flip_request(intel_crtc->plane, obj);
7538 atomic_dec(&intel_crtc->unpin_work_count);
7540 drm_gem_object_unreference(&work->old_fb_obj->base);
7541 drm_gem_object_unreference(&obj->base);
7542 mutex_unlock(&dev->struct_mutex);
7545 spin_lock_irqsave(&dev->event_lock, flags);
7546 intel_crtc->unpin_work = NULL;
7547 spin_unlock_irqrestore(&dev->event_lock, flags);
7549 drm_vblank_put(dev, intel_crtc->pipe);
7556 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7557 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7558 .load_lut = intel_crtc_load_lut,
7561 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7563 struct intel_encoder *other_encoder;
7564 struct drm_crtc *crtc = &encoder->new_crtc->base;
7569 list_for_each_entry(other_encoder,
7570 &crtc->dev->mode_config.encoder_list,
7573 if (&other_encoder->new_crtc->base != crtc ||
7574 encoder == other_encoder)
7583 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7584 struct drm_crtc *crtc)
7586 struct drm_device *dev;
7587 struct drm_crtc *tmp;
7590 WARN(!crtc, "checking null crtc?\n");
7594 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7600 if (encoder->possible_crtcs & crtc_mask)
7606 * intel_modeset_update_staged_output_state
7608 * Updates the staged output configuration state, e.g. after we've read out the
7611 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7613 struct intel_encoder *encoder;
7614 struct intel_connector *connector;
7616 list_for_each_entry(connector, &dev->mode_config.connector_list,
7618 connector->new_encoder =
7619 to_intel_encoder(connector->base.encoder);
7622 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7625 to_intel_crtc(encoder->base.crtc);
7630 * intel_modeset_commit_output_state
7632 * This function copies the stage display pipe configuration to the real one.
7634 static void intel_modeset_commit_output_state(struct drm_device *dev)
7636 struct intel_encoder *encoder;
7637 struct intel_connector *connector;
7639 list_for_each_entry(connector, &dev->mode_config.connector_list,
7641 connector->base.encoder = &connector->new_encoder->base;
7644 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7646 encoder->base.crtc = &encoder->new_crtc->base;
7651 pipe_config_set_bpp(struct drm_crtc *crtc,
7652 struct drm_framebuffer *fb,
7653 struct intel_crtc_config *pipe_config)
7655 struct drm_device *dev = crtc->dev;
7656 struct drm_connector *connector;
7659 switch (fb->pixel_format) {
7661 bpp = 8*3; /* since we go through a colormap */
7663 case DRM_FORMAT_XRGB1555:
7664 case DRM_FORMAT_ARGB1555:
7665 /* checked in intel_framebuffer_init already */
7666 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7668 case DRM_FORMAT_RGB565:
7669 bpp = 6*3; /* min is 18bpp */
7671 case DRM_FORMAT_XBGR8888:
7672 case DRM_FORMAT_ABGR8888:
7673 /* checked in intel_framebuffer_init already */
7674 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7676 case DRM_FORMAT_XRGB8888:
7677 case DRM_FORMAT_ARGB8888:
7680 case DRM_FORMAT_XRGB2101010:
7681 case DRM_FORMAT_ARGB2101010:
7682 case DRM_FORMAT_XBGR2101010:
7683 case DRM_FORMAT_ABGR2101010:
7684 /* checked in intel_framebuffer_init already */
7685 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7689 /* TODO: gen4+ supports 16 bpc floating point, too. */
7691 DRM_DEBUG_KMS("unsupported depth\n");
7695 pipe_config->pipe_bpp = bpp;
7697 /* Clamp display bpp to EDID value */
7698 list_for_each_entry(connector, &dev->mode_config.connector_list,
7700 if (connector->encoder && connector->encoder->crtc != crtc)
7703 /* Don't use an invalid EDID bpc value */
7704 if (connector->display_info.bpc &&
7705 connector->display_info.bpc * 3 < bpp) {
7706 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7707 bpp, connector->display_info.bpc*3);
7708 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7715 static struct intel_crtc_config *
7716 intel_modeset_pipe_config(struct drm_crtc *crtc,
7717 struct drm_framebuffer *fb,
7718 struct drm_display_mode *mode)
7720 struct drm_device *dev = crtc->dev;
7721 struct drm_encoder_helper_funcs *encoder_funcs;
7722 struct intel_encoder *encoder;
7723 struct intel_crtc_config *pipe_config;
7726 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7728 return ERR_PTR(-ENOMEM);
7730 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7731 drm_mode_copy(&pipe_config->requested_mode, mode);
7733 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7737 /* Pass our mode to the connectors and the CRTC to give them a chance to
7738 * adjust it according to limitations or connector properties, and also
7739 * a chance to reject the mode entirely.
7741 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7744 if (&encoder->new_crtc->base != crtc)
7747 if (encoder->compute_config) {
7748 if (!(encoder->compute_config(encoder, pipe_config))) {
7749 DRM_DEBUG_KMS("Encoder config failure\n");
7756 encoder_funcs = encoder->base.helper_private;
7757 if (!(encoder_funcs->mode_fixup(&encoder->base,
7758 &pipe_config->requested_mode,
7759 &pipe_config->adjusted_mode))) {
7760 DRM_DEBUG_KMS("Encoder fixup failed\n");
7765 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7766 DRM_DEBUG_KMS("CRTC fixup failed\n");
7769 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7771 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7772 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7773 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7778 return ERR_PTR(-EINVAL);
7781 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7782 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7784 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7785 unsigned *prepare_pipes, unsigned *disable_pipes)
7787 struct intel_crtc *intel_crtc;
7788 struct drm_device *dev = crtc->dev;
7789 struct intel_encoder *encoder;
7790 struct intel_connector *connector;
7791 struct drm_crtc *tmp_crtc;
7793 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7795 /* Check which crtcs have changed outputs connected to them, these need
7796 * to be part of the prepare_pipes mask. We don't (yet) support global
7797 * modeset across multiple crtcs, so modeset_pipes will only have one
7798 * bit set at most. */
7799 list_for_each_entry(connector, &dev->mode_config.connector_list,
7801 if (connector->base.encoder == &connector->new_encoder->base)
7804 if (connector->base.encoder) {
7805 tmp_crtc = connector->base.encoder->crtc;
7807 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7810 if (connector->new_encoder)
7812 1 << connector->new_encoder->new_crtc->pipe;
7815 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7817 if (encoder->base.crtc == &encoder->new_crtc->base)
7820 if (encoder->base.crtc) {
7821 tmp_crtc = encoder->base.crtc;
7823 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7826 if (encoder->new_crtc)
7827 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7830 /* Check for any pipes that will be fully disabled ... */
7831 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7835 /* Don't try to disable disabled crtcs. */
7836 if (!intel_crtc->base.enabled)
7839 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7841 if (encoder->new_crtc == intel_crtc)
7846 *disable_pipes |= 1 << intel_crtc->pipe;
7850 /* set_mode is also used to update properties on life display pipes. */
7851 intel_crtc = to_intel_crtc(crtc);
7853 *prepare_pipes |= 1 << intel_crtc->pipe;
7856 * For simplicity do a full modeset on any pipe where the output routing
7857 * changed. We could be more clever, but that would require us to be
7858 * more careful with calling the relevant encoder->mode_set functions.
7861 *modeset_pipes = *prepare_pipes;
7863 /* ... and mask these out. */
7864 *modeset_pipes &= ~(*disable_pipes);
7865 *prepare_pipes &= ~(*disable_pipes);
7868 * HACK: We don't (yet) fully support global modesets. intel_set_config
7869 * obies this rule, but the modeset restore mode of
7870 * intel_modeset_setup_hw_state does not.
7872 *modeset_pipes &= 1 << intel_crtc->pipe;
7873 *prepare_pipes &= 1 << intel_crtc->pipe;
7875 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7876 *modeset_pipes, *prepare_pipes, *disable_pipes);
7879 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7881 struct drm_encoder *encoder;
7882 struct drm_device *dev = crtc->dev;
7884 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7885 if (encoder->crtc == crtc)
7892 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7894 struct intel_encoder *intel_encoder;
7895 struct intel_crtc *intel_crtc;
7896 struct drm_connector *connector;
7898 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7900 if (!intel_encoder->base.crtc)
7903 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7905 if (prepare_pipes & (1 << intel_crtc->pipe))
7906 intel_encoder->connectors_active = false;
7909 intel_modeset_commit_output_state(dev);
7911 /* Update computed state. */
7912 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7914 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7917 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7918 if (!connector->encoder || !connector->encoder->crtc)
7921 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7923 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7924 struct drm_property *dpms_property =
7925 dev->mode_config.dpms_property;
7927 connector->dpms = DRM_MODE_DPMS_ON;
7928 drm_object_property_set_value(&connector->base,
7932 intel_encoder = to_intel_encoder(connector->encoder);
7933 intel_encoder->connectors_active = true;
7939 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7940 list_for_each_entry((intel_crtc), \
7941 &(dev)->mode_config.crtc_list, \
7943 if (mask & (1 <<(intel_crtc)->pipe)) \
7946 intel_pipe_config_compare(struct intel_crtc_config *current_config,
7947 struct intel_crtc_config *pipe_config)
7949 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7950 DRM_ERROR("mismatch in has_pch_encoder "
7951 "(expected %i, found %i)\n",
7952 current_config->has_pch_encoder,
7953 pipe_config->has_pch_encoder);
7961 intel_modeset_check_state(struct drm_device *dev)
7963 drm_i915_private_t *dev_priv = dev->dev_private;
7964 struct intel_crtc *crtc;
7965 struct intel_encoder *encoder;
7966 struct intel_connector *connector;
7967 struct intel_crtc_config pipe_config;
7969 list_for_each_entry(connector, &dev->mode_config.connector_list,
7971 /* This also checks the encoder/connector hw state with the
7972 * ->get_hw_state callbacks. */
7973 intel_connector_check_state(connector);
7975 WARN(&connector->new_encoder->base != connector->base.encoder,
7976 "connector's staged encoder doesn't match current encoder\n");
7979 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7981 bool enabled = false;
7982 bool active = false;
7983 enum pipe pipe, tracked_pipe;
7985 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7986 encoder->base.base.id,
7987 drm_get_encoder_name(&encoder->base));
7989 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7990 "encoder's stage crtc doesn't match current crtc\n");
7991 WARN(encoder->connectors_active && !encoder->base.crtc,
7992 "encoder's active_connectors set, but no crtc\n");
7994 list_for_each_entry(connector, &dev->mode_config.connector_list,
7996 if (connector->base.encoder != &encoder->base)
7999 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8002 WARN(!!encoder->base.crtc != enabled,
8003 "encoder's enabled state mismatch "
8004 "(expected %i, found %i)\n",
8005 !!encoder->base.crtc, enabled);
8006 WARN(active && !encoder->base.crtc,
8007 "active encoder with no crtc\n");
8009 WARN(encoder->connectors_active != active,
8010 "encoder's computed active state doesn't match tracked active state "
8011 "(expected %i, found %i)\n", active, encoder->connectors_active);
8013 active = encoder->get_hw_state(encoder, &pipe);
8014 WARN(active != encoder->connectors_active,
8015 "encoder's hw state doesn't match sw tracking "
8016 "(expected %i, found %i)\n",
8017 encoder->connectors_active, active);
8019 if (!encoder->base.crtc)
8022 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8023 WARN(active && pipe != tracked_pipe,
8024 "active encoder's pipe doesn't match"
8025 "(expected %i, found %i)\n",
8026 tracked_pipe, pipe);
8030 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8032 bool enabled = false;
8033 bool active = false;
8035 DRM_DEBUG_KMS("[CRTC:%d]\n",
8036 crtc->base.base.id);
8038 WARN(crtc->active && !crtc->base.enabled,
8039 "active crtc, but not enabled in sw tracking\n");
8041 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8043 if (encoder->base.crtc != &crtc->base)
8046 if (encoder->connectors_active)
8049 WARN(active != crtc->active,
8050 "crtc's computed active state doesn't match tracked active state "
8051 "(expected %i, found %i)\n", active, crtc->active);
8052 WARN(enabled != crtc->base.enabled,
8053 "crtc's computed enabled state doesn't match tracked enabled state "
8054 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8056 memset(&pipe_config, 0, sizeof(pipe_config));
8057 active = dev_priv->display.get_pipe_config(crtc,
8059 WARN(crtc->active != active,
8060 "crtc active state doesn't match with hw state "
8061 "(expected %i, found %i)\n", crtc->active, active);
8064 !intel_pipe_config_compare(&crtc->config, &pipe_config),
8065 "pipe state doesn't match!\n");
8069 static int __intel_set_mode(struct drm_crtc *crtc,
8070 struct drm_display_mode *mode,
8071 int x, int y, struct drm_framebuffer *fb)
8073 struct drm_device *dev = crtc->dev;
8074 drm_i915_private_t *dev_priv = dev->dev_private;
8075 struct drm_display_mode *saved_mode, *saved_hwmode;
8076 struct intel_crtc_config *pipe_config = NULL;
8077 struct intel_crtc *intel_crtc;
8078 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8081 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8084 saved_hwmode = saved_mode + 1;
8086 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8087 &prepare_pipes, &disable_pipes);
8089 *saved_hwmode = crtc->hwmode;
8090 *saved_mode = crtc->mode;
8092 /* Hack: Because we don't (yet) support global modeset on multiple
8093 * crtcs, we don't keep track of the new mode for more than one crtc.
8094 * Hence simply check whether any bit is set in modeset_pipes in all the
8095 * pieces of code that are not yet converted to deal with mutliple crtcs
8096 * changing their mode at the same time. */
8097 if (modeset_pipes) {
8098 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8099 if (IS_ERR(pipe_config)) {
8100 ret = PTR_ERR(pipe_config);
8107 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8108 intel_crtc_disable(&intel_crtc->base);
8110 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8111 if (intel_crtc->base.enabled)
8112 dev_priv->display.crtc_disable(&intel_crtc->base);
8115 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8116 * to set it here already despite that we pass it down the callchain.
8118 if (modeset_pipes) {
8119 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
8121 /* mode_set/enable/disable functions rely on a correct pipe
8123 to_intel_crtc(crtc)->config = *pipe_config;
8124 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
8127 /* Only after disabling all output pipelines that will be changed can we
8128 * update the the output configuration. */
8129 intel_modeset_update_state(dev, prepare_pipes);
8131 if (dev_priv->display.modeset_global_resources)
8132 dev_priv->display.modeset_global_resources(dev);
8134 /* Set up the DPLL and any encoders state that needs to adjust or depend
8137 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8138 ret = intel_crtc_mode_set(&intel_crtc->base,
8144 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8145 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8146 dev_priv->display.crtc_enable(&intel_crtc->base);
8148 if (modeset_pipes) {
8149 /* Store real post-adjustment hardware mode. */
8150 crtc->hwmode = pipe_config->adjusted_mode;
8152 /* Calculate and store various constants which
8153 * are later needed by vblank and swap-completion
8154 * timestamping. They are derived from true hwmode.
8156 drm_calc_timestamping_constants(crtc);
8159 /* FIXME: add subpixel order */
8161 if (ret && crtc->enabled) {
8162 crtc->hwmode = *saved_hwmode;
8163 crtc->mode = *saved_mode;
8172 int intel_set_mode(struct drm_crtc *crtc,
8173 struct drm_display_mode *mode,
8174 int x, int y, struct drm_framebuffer *fb)
8178 ret = __intel_set_mode(crtc, mode, x, y, fb);
8181 intel_modeset_check_state(crtc->dev);
8186 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8188 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8191 #undef for_each_intel_crtc_masked
8193 static void intel_set_config_free(struct intel_set_config *config)
8198 kfree(config->save_connector_encoders);
8199 kfree(config->save_encoder_crtcs);
8203 static int intel_set_config_save_state(struct drm_device *dev,
8204 struct intel_set_config *config)
8206 struct drm_encoder *encoder;
8207 struct drm_connector *connector;
8210 config->save_encoder_crtcs =
8211 kcalloc(dev->mode_config.num_encoder,
8212 sizeof(struct drm_crtc *), GFP_KERNEL);
8213 if (!config->save_encoder_crtcs)
8216 config->save_connector_encoders =
8217 kcalloc(dev->mode_config.num_connector,
8218 sizeof(struct drm_encoder *), GFP_KERNEL);
8219 if (!config->save_connector_encoders)
8222 /* Copy data. Note that driver private data is not affected.
8223 * Should anything bad happen only the expected state is
8224 * restored, not the drivers personal bookkeeping.
8227 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8228 config->save_encoder_crtcs[count++] = encoder->crtc;
8232 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8233 config->save_connector_encoders[count++] = connector->encoder;
8239 static void intel_set_config_restore_state(struct drm_device *dev,
8240 struct intel_set_config *config)
8242 struct intel_encoder *encoder;
8243 struct intel_connector *connector;
8247 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8249 to_intel_crtc(config->save_encoder_crtcs[count++]);
8253 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8254 connector->new_encoder =
8255 to_intel_encoder(config->save_connector_encoders[count++]);
8260 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8261 struct intel_set_config *config)
8264 /* We should be able to check here if the fb has the same properties
8265 * and then just flip_or_move it */
8266 if (set->crtc->fb != set->fb) {
8267 /* If we have no fb then treat it as a full mode set */
8268 if (set->crtc->fb == NULL) {
8269 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8270 config->mode_changed = true;
8271 } else if (set->fb == NULL) {
8272 config->mode_changed = true;
8273 } else if (set->fb->pixel_format !=
8274 set->crtc->fb->pixel_format) {
8275 config->mode_changed = true;
8277 config->fb_changed = true;
8280 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8281 config->fb_changed = true;
8283 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8284 DRM_DEBUG_KMS("modes are different, full mode set\n");
8285 drm_mode_debug_printmodeline(&set->crtc->mode);
8286 drm_mode_debug_printmodeline(set->mode);
8287 config->mode_changed = true;
8292 intel_modeset_stage_output_state(struct drm_device *dev,
8293 struct drm_mode_set *set,
8294 struct intel_set_config *config)
8296 struct drm_crtc *new_crtc;
8297 struct intel_connector *connector;
8298 struct intel_encoder *encoder;
8301 /* The upper layers ensure that we either disable a crtc or have a list
8302 * of connectors. For paranoia, double-check this. */
8303 WARN_ON(!set->fb && (set->num_connectors != 0));
8304 WARN_ON(set->fb && (set->num_connectors == 0));
8307 list_for_each_entry(connector, &dev->mode_config.connector_list,
8309 /* Otherwise traverse passed in connector list and get encoders
8311 for (ro = 0; ro < set->num_connectors; ro++) {
8312 if (set->connectors[ro] == &connector->base) {
8313 connector->new_encoder = connector->encoder;
8318 /* If we disable the crtc, disable all its connectors. Also, if
8319 * the connector is on the changing crtc but not on the new
8320 * connector list, disable it. */
8321 if ((!set->fb || ro == set->num_connectors) &&
8322 connector->base.encoder &&
8323 connector->base.encoder->crtc == set->crtc) {
8324 connector->new_encoder = NULL;
8326 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8327 connector->base.base.id,
8328 drm_get_connector_name(&connector->base));
8332 if (&connector->new_encoder->base != connector->base.encoder) {
8333 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8334 config->mode_changed = true;
8337 /* connector->new_encoder is now updated for all connectors. */
8339 /* Update crtc of enabled connectors. */
8341 list_for_each_entry(connector, &dev->mode_config.connector_list,
8343 if (!connector->new_encoder)
8346 new_crtc = connector->new_encoder->base.crtc;
8348 for (ro = 0; ro < set->num_connectors; ro++) {
8349 if (set->connectors[ro] == &connector->base)
8350 new_crtc = set->crtc;
8353 /* Make sure the new CRTC will work with the encoder */
8354 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8358 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8360 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8361 connector->base.base.id,
8362 drm_get_connector_name(&connector->base),
8366 /* Check for any encoders that needs to be disabled. */
8367 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8369 list_for_each_entry(connector,
8370 &dev->mode_config.connector_list,
8372 if (connector->new_encoder == encoder) {
8373 WARN_ON(!connector->new_encoder->new_crtc);
8378 encoder->new_crtc = NULL;
8380 /* Only now check for crtc changes so we don't miss encoders
8381 * that will be disabled. */
8382 if (&encoder->new_crtc->base != encoder->base.crtc) {
8383 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8384 config->mode_changed = true;
8387 /* Now we've also updated encoder->new_crtc for all encoders. */
8392 static int intel_crtc_set_config(struct drm_mode_set *set)
8394 struct drm_device *dev;
8395 struct drm_mode_set save_set;
8396 struct intel_set_config *config;
8401 BUG_ON(!set->crtc->helper_private);
8403 /* Enforce sane interface api - has been abused by the fb helper. */
8404 BUG_ON(!set->mode && set->fb);
8405 BUG_ON(set->fb && set->num_connectors == 0);
8408 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8409 set->crtc->base.id, set->fb->base.id,
8410 (int)set->num_connectors, set->x, set->y);
8412 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8415 dev = set->crtc->dev;
8418 config = kzalloc(sizeof(*config), GFP_KERNEL);
8422 ret = intel_set_config_save_state(dev, config);
8426 save_set.crtc = set->crtc;
8427 save_set.mode = &set->crtc->mode;
8428 save_set.x = set->crtc->x;
8429 save_set.y = set->crtc->y;
8430 save_set.fb = set->crtc->fb;
8432 /* Compute whether we need a full modeset, only an fb base update or no
8433 * change at all. In the future we might also check whether only the
8434 * mode changed, e.g. for LVDS where we only change the panel fitter in
8436 intel_set_config_compute_mode_changes(set, config);
8438 ret = intel_modeset_stage_output_state(dev, set, config);
8442 if (config->mode_changed) {
8444 DRM_DEBUG_KMS("attempting to set mode from"
8446 drm_mode_debug_printmodeline(set->mode);
8449 ret = intel_set_mode(set->crtc, set->mode,
8450 set->x, set->y, set->fb);
8452 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8453 set->crtc->base.id, ret);
8456 } else if (config->fb_changed) {
8457 intel_crtc_wait_for_pending_flips(set->crtc);
8459 ret = intel_pipe_set_base(set->crtc,
8460 set->x, set->y, set->fb);
8463 intel_set_config_free(config);
8468 intel_set_config_restore_state(dev, config);
8470 /* Try to restore the config */
8471 if (config->mode_changed &&
8472 intel_set_mode(save_set.crtc, save_set.mode,
8473 save_set.x, save_set.y, save_set.fb))
8474 DRM_ERROR("failed to restore config after modeset failure\n");
8477 intel_set_config_free(config);
8481 static const struct drm_crtc_funcs intel_crtc_funcs = {
8482 .cursor_set = intel_crtc_cursor_set,
8483 .cursor_move = intel_crtc_cursor_move,
8484 .gamma_set = intel_crtc_gamma_set,
8485 .set_config = intel_crtc_set_config,
8486 .destroy = intel_crtc_destroy,
8487 .page_flip = intel_crtc_page_flip,
8490 static void intel_cpu_pll_init(struct drm_device *dev)
8493 intel_ddi_pll_init(dev);
8496 static void intel_pch_pll_init(struct drm_device *dev)
8498 drm_i915_private_t *dev_priv = dev->dev_private;
8501 if (dev_priv->num_pch_pll == 0) {
8502 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8506 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8507 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8508 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8509 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8513 static void intel_crtc_init(struct drm_device *dev, int pipe)
8515 drm_i915_private_t *dev_priv = dev->dev_private;
8516 struct intel_crtc *intel_crtc;
8519 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8520 if (intel_crtc == NULL)
8523 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8525 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8526 for (i = 0; i < 256; i++) {
8527 intel_crtc->lut_r[i] = i;
8528 intel_crtc->lut_g[i] = i;
8529 intel_crtc->lut_b[i] = i;
8532 /* Swap pipes & planes for FBC on pre-965 */
8533 intel_crtc->pipe = pipe;
8534 intel_crtc->plane = pipe;
8535 intel_crtc->config.cpu_transcoder = pipe;
8536 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8537 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8538 intel_crtc->plane = !pipe;
8541 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8542 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8543 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8544 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8546 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8549 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8550 struct drm_file *file)
8552 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8553 struct drm_mode_object *drmmode_obj;
8554 struct intel_crtc *crtc;
8556 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8559 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8560 DRM_MODE_OBJECT_CRTC);
8563 DRM_ERROR("no such CRTC id\n");
8567 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8568 pipe_from_crtc_id->pipe = crtc->pipe;
8573 static int intel_encoder_clones(struct intel_encoder *encoder)
8575 struct drm_device *dev = encoder->base.dev;
8576 struct intel_encoder *source_encoder;
8580 list_for_each_entry(source_encoder,
8581 &dev->mode_config.encoder_list, base.head) {
8583 if (encoder == source_encoder)
8584 index_mask |= (1 << entry);
8586 /* Intel hw has only one MUX where enocoders could be cloned. */
8587 if (encoder->cloneable && source_encoder->cloneable)
8588 index_mask |= (1 << entry);
8596 static bool has_edp_a(struct drm_device *dev)
8598 struct drm_i915_private *dev_priv = dev->dev_private;
8600 if (!IS_MOBILE(dev))
8603 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8607 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8613 static void intel_setup_outputs(struct drm_device *dev)
8615 struct drm_i915_private *dev_priv = dev->dev_private;
8616 struct intel_encoder *encoder;
8617 bool dpd_is_edp = false;
8620 has_lvds = intel_lvds_init(dev);
8621 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8622 /* disable the panel fitter on everything but LVDS */
8623 I915_WRITE(PFIT_CONTROL, 0);
8627 intel_crt_init(dev);
8632 /* Haswell uses DDI functions to detect digital outputs */
8633 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8634 /* DDI A only supports eDP */
8636 intel_ddi_init(dev, PORT_A);
8638 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8640 found = I915_READ(SFUSE_STRAP);
8642 if (found & SFUSE_STRAP_DDIB_DETECTED)
8643 intel_ddi_init(dev, PORT_B);
8644 if (found & SFUSE_STRAP_DDIC_DETECTED)
8645 intel_ddi_init(dev, PORT_C);
8646 if (found & SFUSE_STRAP_DDID_DETECTED)
8647 intel_ddi_init(dev, PORT_D);
8648 } else if (HAS_PCH_SPLIT(dev)) {
8650 dpd_is_edp = intel_dpd_is_edp(dev);
8653 intel_dp_init(dev, DP_A, PORT_A);
8655 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8656 /* PCH SDVOB multiplex with HDMIB */
8657 found = intel_sdvo_init(dev, PCH_SDVOB, true);
8659 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8660 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8661 intel_dp_init(dev, PCH_DP_B, PORT_B);
8664 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8665 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8667 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8668 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8670 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8671 intel_dp_init(dev, PCH_DP_C, PORT_C);
8673 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8674 intel_dp_init(dev, PCH_DP_D, PORT_D);
8675 } else if (IS_VALLEYVIEW(dev)) {
8676 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8677 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8678 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8680 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8681 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8683 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8684 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8686 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8689 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8690 DRM_DEBUG_KMS("probing SDVOB\n");
8691 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8692 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8693 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8694 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8697 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8698 DRM_DEBUG_KMS("probing DP_B\n");
8699 intel_dp_init(dev, DP_B, PORT_B);
8703 /* Before G4X SDVOC doesn't have its own detect register */
8705 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8706 DRM_DEBUG_KMS("probing SDVOC\n");
8707 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8710 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8712 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8713 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8714 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8716 if (SUPPORTS_INTEGRATED_DP(dev)) {
8717 DRM_DEBUG_KMS("probing DP_C\n");
8718 intel_dp_init(dev, DP_C, PORT_C);
8722 if (SUPPORTS_INTEGRATED_DP(dev) &&
8723 (I915_READ(DP_D) & DP_DETECTED)) {
8724 DRM_DEBUG_KMS("probing DP_D\n");
8725 intel_dp_init(dev, DP_D, PORT_D);
8727 } else if (IS_GEN2(dev))
8728 intel_dvo_init(dev);
8730 if (SUPPORTS_TV(dev))
8733 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8734 encoder->base.possible_crtcs = encoder->crtc_mask;
8735 encoder->base.possible_clones =
8736 intel_encoder_clones(encoder);
8739 intel_init_pch_refclk(dev);
8741 drm_helper_move_panel_connectors_to_head(dev);
8744 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8746 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8748 drm_framebuffer_cleanup(fb);
8749 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8754 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8755 struct drm_file *file,
8756 unsigned int *handle)
8758 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8759 struct drm_i915_gem_object *obj = intel_fb->obj;
8761 return drm_gem_handle_create(file, &obj->base, handle);
8764 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8765 .destroy = intel_user_framebuffer_destroy,
8766 .create_handle = intel_user_framebuffer_create_handle,
8769 int intel_framebuffer_init(struct drm_device *dev,
8770 struct intel_framebuffer *intel_fb,
8771 struct drm_mode_fb_cmd2 *mode_cmd,
8772 struct drm_i915_gem_object *obj)
8776 if (obj->tiling_mode == I915_TILING_Y) {
8777 DRM_DEBUG("hardware does not support tiling Y\n");
8781 if (mode_cmd->pitches[0] & 63) {
8782 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8783 mode_cmd->pitches[0]);
8787 /* FIXME <= Gen4 stride limits are bit unclear */
8788 if (mode_cmd->pitches[0] > 32768) {
8789 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8790 mode_cmd->pitches[0]);
8794 if (obj->tiling_mode != I915_TILING_NONE &&
8795 mode_cmd->pitches[0] != obj->stride) {
8796 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8797 mode_cmd->pitches[0], obj->stride);
8801 /* Reject formats not supported by any plane early. */
8802 switch (mode_cmd->pixel_format) {
8804 case DRM_FORMAT_RGB565:
8805 case DRM_FORMAT_XRGB8888:
8806 case DRM_FORMAT_ARGB8888:
8808 case DRM_FORMAT_XRGB1555:
8809 case DRM_FORMAT_ARGB1555:
8810 if (INTEL_INFO(dev)->gen > 3) {
8811 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8815 case DRM_FORMAT_XBGR8888:
8816 case DRM_FORMAT_ABGR8888:
8817 case DRM_FORMAT_XRGB2101010:
8818 case DRM_FORMAT_ARGB2101010:
8819 case DRM_FORMAT_XBGR2101010:
8820 case DRM_FORMAT_ABGR2101010:
8821 if (INTEL_INFO(dev)->gen < 4) {
8822 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8826 case DRM_FORMAT_YUYV:
8827 case DRM_FORMAT_UYVY:
8828 case DRM_FORMAT_YVYU:
8829 case DRM_FORMAT_VYUY:
8830 if (INTEL_INFO(dev)->gen < 5) {
8831 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8836 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8840 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8841 if (mode_cmd->offsets[0] != 0)
8844 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8845 intel_fb->obj = obj;
8847 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8849 DRM_ERROR("framebuffer init failed %d\n", ret);
8856 static struct drm_framebuffer *
8857 intel_user_framebuffer_create(struct drm_device *dev,
8858 struct drm_file *filp,
8859 struct drm_mode_fb_cmd2 *mode_cmd)
8861 struct drm_i915_gem_object *obj;
8863 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8864 mode_cmd->handles[0]));
8865 if (&obj->base == NULL)
8866 return ERR_PTR(-ENOENT);
8868 return intel_framebuffer_create(dev, mode_cmd, obj);
8871 static const struct drm_mode_config_funcs intel_mode_funcs = {
8872 .fb_create = intel_user_framebuffer_create,
8873 .output_poll_changed = intel_fb_output_poll_changed,
8876 /* Set up chip specific display functions */
8877 static void intel_init_display(struct drm_device *dev)
8879 struct drm_i915_private *dev_priv = dev->dev_private;
8882 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
8883 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8884 dev_priv->display.crtc_enable = haswell_crtc_enable;
8885 dev_priv->display.crtc_disable = haswell_crtc_disable;
8886 dev_priv->display.off = haswell_crtc_off;
8887 dev_priv->display.update_plane = ironlake_update_plane;
8888 } else if (HAS_PCH_SPLIT(dev)) {
8889 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
8890 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8891 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8892 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8893 dev_priv->display.off = ironlake_crtc_off;
8894 dev_priv->display.update_plane = ironlake_update_plane;
8895 } else if (IS_VALLEYVIEW(dev)) {
8896 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8897 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8898 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8899 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8900 dev_priv->display.off = i9xx_crtc_off;
8901 dev_priv->display.update_plane = i9xx_update_plane;
8903 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8904 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8905 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8906 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8907 dev_priv->display.off = i9xx_crtc_off;
8908 dev_priv->display.update_plane = i9xx_update_plane;
8911 /* Returns the core display clock speed */
8912 if (IS_VALLEYVIEW(dev))
8913 dev_priv->display.get_display_clock_speed =
8914 valleyview_get_display_clock_speed;
8915 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8916 dev_priv->display.get_display_clock_speed =
8917 i945_get_display_clock_speed;
8918 else if (IS_I915G(dev))
8919 dev_priv->display.get_display_clock_speed =
8920 i915_get_display_clock_speed;
8921 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8922 dev_priv->display.get_display_clock_speed =
8923 i9xx_misc_get_display_clock_speed;
8924 else if (IS_I915GM(dev))
8925 dev_priv->display.get_display_clock_speed =
8926 i915gm_get_display_clock_speed;
8927 else if (IS_I865G(dev))
8928 dev_priv->display.get_display_clock_speed =
8929 i865_get_display_clock_speed;
8930 else if (IS_I85X(dev))
8931 dev_priv->display.get_display_clock_speed =
8932 i855_get_display_clock_speed;
8934 dev_priv->display.get_display_clock_speed =
8935 i830_get_display_clock_speed;
8937 if (HAS_PCH_SPLIT(dev)) {
8939 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8940 dev_priv->display.write_eld = ironlake_write_eld;
8941 } else if (IS_GEN6(dev)) {
8942 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8943 dev_priv->display.write_eld = ironlake_write_eld;
8944 } else if (IS_IVYBRIDGE(dev)) {
8945 /* FIXME: detect B0+ stepping and use auto training */
8946 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8947 dev_priv->display.write_eld = ironlake_write_eld;
8948 dev_priv->display.modeset_global_resources =
8949 ivb_modeset_global_resources;
8950 } else if (IS_HASWELL(dev)) {
8951 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8952 dev_priv->display.write_eld = haswell_write_eld;
8953 dev_priv->display.modeset_global_resources =
8954 haswell_modeset_global_resources;
8956 } else if (IS_G4X(dev)) {
8957 dev_priv->display.write_eld = g4x_write_eld;
8960 /* Default just returns -ENODEV to indicate unsupported */
8961 dev_priv->display.queue_flip = intel_default_queue_flip;
8963 switch (INTEL_INFO(dev)->gen) {
8965 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8969 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8974 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8978 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8981 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8987 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8988 * resume, or other times. This quirk makes sure that's the case for
8991 static void quirk_pipea_force(struct drm_device *dev)
8993 struct drm_i915_private *dev_priv = dev->dev_private;
8995 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8996 DRM_INFO("applying pipe a force quirk\n");
9000 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9002 static void quirk_ssc_force_disable(struct drm_device *dev)
9004 struct drm_i915_private *dev_priv = dev->dev_private;
9005 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9006 DRM_INFO("applying lvds SSC disable quirk\n");
9010 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9013 static void quirk_invert_brightness(struct drm_device *dev)
9015 struct drm_i915_private *dev_priv = dev->dev_private;
9016 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9017 DRM_INFO("applying inverted panel brightness quirk\n");
9020 struct intel_quirk {
9022 int subsystem_vendor;
9023 int subsystem_device;
9024 void (*hook)(struct drm_device *dev);
9027 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9028 struct intel_dmi_quirk {
9029 void (*hook)(struct drm_device *dev);
9030 const struct dmi_system_id (*dmi_id_list)[];
9033 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9035 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9039 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9041 .dmi_id_list = &(const struct dmi_system_id[]) {
9043 .callback = intel_dmi_reverse_brightness,
9044 .ident = "NCR Corporation",
9045 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9046 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9049 { } /* terminating entry */
9051 .hook = quirk_invert_brightness,
9055 static struct intel_quirk intel_quirks[] = {
9056 /* HP Mini needs pipe A force quirk (LP: #322104) */
9057 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9059 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9060 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9062 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9063 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9065 /* 830/845 need to leave pipe A & dpll A up */
9066 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9067 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9069 /* Lenovo U160 cannot use SSC on LVDS */
9070 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9072 /* Sony Vaio Y cannot use SSC on LVDS */
9073 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9075 /* Acer Aspire 5734Z must invert backlight brightness */
9076 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9078 /* Acer/eMachines G725 */
9079 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9081 /* Acer/eMachines e725 */
9082 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9084 /* Acer/Packard Bell NCL20 */
9085 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9087 /* Acer Aspire 4736Z */
9088 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9091 static void intel_init_quirks(struct drm_device *dev)
9093 struct pci_dev *d = dev->pdev;
9096 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9097 struct intel_quirk *q = &intel_quirks[i];
9099 if (d->device == q->device &&
9100 (d->subsystem_vendor == q->subsystem_vendor ||
9101 q->subsystem_vendor == PCI_ANY_ID) &&
9102 (d->subsystem_device == q->subsystem_device ||
9103 q->subsystem_device == PCI_ANY_ID))
9106 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9107 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9108 intel_dmi_quirks[i].hook(dev);
9112 /* Disable the VGA plane that we never use */
9113 static void i915_disable_vga(struct drm_device *dev)
9115 struct drm_i915_private *dev_priv = dev->dev_private;
9117 u32 vga_reg = i915_vgacntrl_reg(dev);
9119 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9120 outb(SR01, VGA_SR_INDEX);
9121 sr1 = inb(VGA_SR_DATA);
9122 outb(sr1 | 1<<5, VGA_SR_DATA);
9123 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9126 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9127 POSTING_READ(vga_reg);
9130 void intel_modeset_init_hw(struct drm_device *dev)
9132 intel_init_power_well(dev);
9134 intel_prepare_ddi(dev);
9136 intel_init_clock_gating(dev);
9138 mutex_lock(&dev->struct_mutex);
9139 intel_enable_gt_powersave(dev);
9140 mutex_unlock(&dev->struct_mutex);
9143 void intel_modeset_init(struct drm_device *dev)
9145 struct drm_i915_private *dev_priv = dev->dev_private;
9148 drm_mode_config_init(dev);
9150 dev->mode_config.min_width = 0;
9151 dev->mode_config.min_height = 0;
9153 dev->mode_config.preferred_depth = 24;
9154 dev->mode_config.prefer_shadow = 1;
9156 dev->mode_config.funcs = &intel_mode_funcs;
9158 intel_init_quirks(dev);
9162 if (INTEL_INFO(dev)->num_pipes == 0)
9165 intel_init_display(dev);
9168 dev->mode_config.max_width = 2048;
9169 dev->mode_config.max_height = 2048;
9170 } else if (IS_GEN3(dev)) {
9171 dev->mode_config.max_width = 4096;
9172 dev->mode_config.max_height = 4096;
9174 dev->mode_config.max_width = 8192;
9175 dev->mode_config.max_height = 8192;
9177 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9179 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9180 INTEL_INFO(dev)->num_pipes,
9181 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9183 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9184 intel_crtc_init(dev, i);
9185 for (j = 0; j < dev_priv->num_plane; j++) {
9186 ret = intel_plane_init(dev, i, j);
9188 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9189 pipe_name(i), sprite_name(i, j), ret);
9193 intel_cpu_pll_init(dev);
9194 intel_pch_pll_init(dev);
9196 /* Just disable it once at startup */
9197 i915_disable_vga(dev);
9198 intel_setup_outputs(dev);
9200 /* Just in case the BIOS is doing something questionable. */
9201 intel_disable_fbc(dev);
9205 intel_connector_break_all_links(struct intel_connector *connector)
9207 connector->base.dpms = DRM_MODE_DPMS_OFF;
9208 connector->base.encoder = NULL;
9209 connector->encoder->connectors_active = false;
9210 connector->encoder->base.crtc = NULL;
9213 static void intel_enable_pipe_a(struct drm_device *dev)
9215 struct intel_connector *connector;
9216 struct drm_connector *crt = NULL;
9217 struct intel_load_detect_pipe load_detect_temp;
9219 /* We can't just switch on the pipe A, we need to set things up with a
9220 * proper mode and output configuration. As a gross hack, enable pipe A
9221 * by enabling the load detect pipe once. */
9222 list_for_each_entry(connector,
9223 &dev->mode_config.connector_list,
9225 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9226 crt = &connector->base;
9234 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9235 intel_release_load_detect_pipe(crt, &load_detect_temp);
9241 intel_check_plane_mapping(struct intel_crtc *crtc)
9243 struct drm_device *dev = crtc->base.dev;
9244 struct drm_i915_private *dev_priv = dev->dev_private;
9247 if (INTEL_INFO(dev)->num_pipes == 1)
9250 reg = DSPCNTR(!crtc->plane);
9251 val = I915_READ(reg);
9253 if ((val & DISPLAY_PLANE_ENABLE) &&
9254 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9260 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9262 struct drm_device *dev = crtc->base.dev;
9263 struct drm_i915_private *dev_priv = dev->dev_private;
9266 /* Clear any frame start delays used for debugging left by the BIOS */
9267 reg = PIPECONF(crtc->config.cpu_transcoder);
9268 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9270 /* We need to sanitize the plane -> pipe mapping first because this will
9271 * disable the crtc (and hence change the state) if it is wrong. Note
9272 * that gen4+ has a fixed plane -> pipe mapping. */
9273 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9274 struct intel_connector *connector;
9277 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9278 crtc->base.base.id);
9280 /* Pipe has the wrong plane attached and the plane is active.
9281 * Temporarily change the plane mapping and disable everything
9283 plane = crtc->plane;
9284 crtc->plane = !plane;
9285 dev_priv->display.crtc_disable(&crtc->base);
9286 crtc->plane = plane;
9288 /* ... and break all links. */
9289 list_for_each_entry(connector, &dev->mode_config.connector_list,
9291 if (connector->encoder->base.crtc != &crtc->base)
9294 intel_connector_break_all_links(connector);
9297 WARN_ON(crtc->active);
9298 crtc->base.enabled = false;
9301 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9302 crtc->pipe == PIPE_A && !crtc->active) {
9303 /* BIOS forgot to enable pipe A, this mostly happens after
9304 * resume. Force-enable the pipe to fix this, the update_dpms
9305 * call below we restore the pipe to the right state, but leave
9306 * the required bits on. */
9307 intel_enable_pipe_a(dev);
9310 /* Adjust the state of the output pipe according to whether we
9311 * have active connectors/encoders. */
9312 intel_crtc_update_dpms(&crtc->base);
9314 if (crtc->active != crtc->base.enabled) {
9315 struct intel_encoder *encoder;
9317 /* This can happen either due to bugs in the get_hw_state
9318 * functions or because the pipe is force-enabled due to the
9320 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9322 crtc->base.enabled ? "enabled" : "disabled",
9323 crtc->active ? "enabled" : "disabled");
9325 crtc->base.enabled = crtc->active;
9327 /* Because we only establish the connector -> encoder ->
9328 * crtc links if something is active, this means the
9329 * crtc is now deactivated. Break the links. connector
9330 * -> encoder links are only establish when things are
9331 * actually up, hence no need to break them. */
9332 WARN_ON(crtc->active);
9334 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9335 WARN_ON(encoder->connectors_active);
9336 encoder->base.crtc = NULL;
9341 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9343 struct intel_connector *connector;
9344 struct drm_device *dev = encoder->base.dev;
9346 /* We need to check both for a crtc link (meaning that the
9347 * encoder is active and trying to read from a pipe) and the
9348 * pipe itself being active. */
9349 bool has_active_crtc = encoder->base.crtc &&
9350 to_intel_crtc(encoder->base.crtc)->active;
9352 if (encoder->connectors_active && !has_active_crtc) {
9353 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9354 encoder->base.base.id,
9355 drm_get_encoder_name(&encoder->base));
9357 /* Connector is active, but has no active pipe. This is
9358 * fallout from our resume register restoring. Disable
9359 * the encoder manually again. */
9360 if (encoder->base.crtc) {
9361 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9362 encoder->base.base.id,
9363 drm_get_encoder_name(&encoder->base));
9364 encoder->disable(encoder);
9367 /* Inconsistent output/port/pipe state happens presumably due to
9368 * a bug in one of the get_hw_state functions. Or someplace else
9369 * in our code, like the register restore mess on resume. Clamp
9370 * things to off as a safer default. */
9371 list_for_each_entry(connector,
9372 &dev->mode_config.connector_list,
9374 if (connector->encoder != encoder)
9377 intel_connector_break_all_links(connector);
9380 /* Enabled encoders without active connectors will be fixed in
9381 * the crtc fixup. */
9384 void i915_redisable_vga(struct drm_device *dev)
9386 struct drm_i915_private *dev_priv = dev->dev_private;
9387 u32 vga_reg = i915_vgacntrl_reg(dev);
9389 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9390 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9391 i915_disable_vga(dev);
9395 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9396 * and i915 state tracking structures. */
9397 void intel_modeset_setup_hw_state(struct drm_device *dev,
9400 struct drm_i915_private *dev_priv = dev->dev_private;
9403 struct drm_plane *plane;
9404 struct intel_crtc *crtc;
9405 struct intel_encoder *encoder;
9406 struct intel_connector *connector;
9409 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9411 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9412 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9413 case TRANS_DDI_EDP_INPUT_A_ON:
9414 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9417 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9420 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9424 /* A bogus value has been programmed, disable
9426 WARN(1, "Bogus eDP source %08x\n", tmp);
9427 intel_ddi_disable_transcoder_func(dev_priv,
9432 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9433 crtc->config.cpu_transcoder = TRANSCODER_EDP;
9435 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9441 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9443 enum transcoder tmp = crtc->config.cpu_transcoder;
9444 memset(&crtc->config, 0, sizeof(crtc->config));
9445 crtc->config.cpu_transcoder = tmp;
9447 crtc->active = dev_priv->display.get_pipe_config(crtc,
9450 crtc->base.enabled = crtc->active;
9452 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9454 crtc->active ? "enabled" : "disabled");
9458 intel_ddi_setup_hw_pll_state(dev);
9460 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9464 if (encoder->get_hw_state(encoder, &pipe)) {
9465 encoder->base.crtc =
9466 dev_priv->pipe_to_crtc_mapping[pipe];
9468 encoder->base.crtc = NULL;
9471 encoder->connectors_active = false;
9472 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9473 encoder->base.base.id,
9474 drm_get_encoder_name(&encoder->base),
9475 encoder->base.crtc ? "enabled" : "disabled",
9479 list_for_each_entry(connector, &dev->mode_config.connector_list,
9481 if (connector->get_hw_state(connector)) {
9482 connector->base.dpms = DRM_MODE_DPMS_ON;
9483 connector->encoder->connectors_active = true;
9484 connector->base.encoder = &connector->encoder->base;
9486 connector->base.dpms = DRM_MODE_DPMS_OFF;
9487 connector->base.encoder = NULL;
9489 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9490 connector->base.base.id,
9491 drm_get_connector_name(&connector->base),
9492 connector->base.encoder ? "enabled" : "disabled");
9495 /* HW state is read out, now we need to sanitize this mess. */
9496 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9498 intel_sanitize_encoder(encoder);
9501 for_each_pipe(pipe) {
9502 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9503 intel_sanitize_crtc(crtc);
9506 if (force_restore) {
9508 * We need to use raw interfaces for restoring state to avoid
9509 * checking (bogus) intermediate states.
9511 for_each_pipe(pipe) {
9512 struct drm_crtc *crtc =
9513 dev_priv->pipe_to_crtc_mapping[pipe];
9515 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9518 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9519 intel_plane_restore(plane);
9521 i915_redisable_vga(dev);
9523 intel_modeset_update_staged_output_state(dev);
9526 intel_modeset_check_state(dev);
9528 drm_mode_config_reset(dev);
9531 void intel_modeset_gem_init(struct drm_device *dev)
9533 intel_modeset_init_hw(dev);
9535 intel_setup_overlay(dev);
9537 intel_modeset_setup_hw_state(dev, false);
9540 void intel_modeset_cleanup(struct drm_device *dev)
9542 struct drm_i915_private *dev_priv = dev->dev_private;
9543 struct drm_crtc *crtc;
9544 struct intel_crtc *intel_crtc;
9546 drm_kms_helper_poll_fini(dev);
9547 mutex_lock(&dev->struct_mutex);
9549 intel_unregister_dsm_handler();
9552 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9553 /* Skip inactive CRTCs */
9557 intel_crtc = to_intel_crtc(crtc);
9558 intel_increase_pllclock(crtc);
9561 intel_disable_fbc(dev);
9563 intel_disable_gt_powersave(dev);
9565 ironlake_teardown_rc6(dev);
9567 mutex_unlock(&dev->struct_mutex);
9569 /* Disable the irq before mode object teardown, for the irq might
9570 * enqueue unpin/hotplug work. */
9571 drm_irq_uninstall(dev);
9572 cancel_work_sync(&dev_priv->hotplug_work);
9573 cancel_work_sync(&dev_priv->rps.work);
9575 /* flush any delayed tasks or pending work */
9576 flush_scheduled_work();
9578 /* destroy backlight, if any, before the connectors */
9579 intel_panel_destroy_backlight(dev);
9581 drm_mode_config_cleanup(dev);
9583 intel_cleanup_overlay(dev);
9587 * Return which encoder is currently attached for connector.
9589 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9591 return &intel_attached_encoder(connector)->base;
9594 void intel_connector_attach_encoder(struct intel_connector *connector,
9595 struct intel_encoder *encoder)
9597 connector->encoder = encoder;
9598 drm_mode_connector_attach_encoder(&connector->base,
9603 * set vga decode state - true == enable VGA decode
9605 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9607 struct drm_i915_private *dev_priv = dev->dev_private;
9610 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9612 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9614 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9615 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9619 #ifdef CONFIG_DEBUG_FS
9620 #include <linux/seq_file.h>
9622 struct intel_display_error_state {
9623 struct intel_cursor_error_state {
9628 } cursor[I915_MAX_PIPES];
9630 struct intel_pipe_error_state {
9640 } pipe[I915_MAX_PIPES];
9642 struct intel_plane_error_state {
9650 } plane[I915_MAX_PIPES];
9653 struct intel_display_error_state *
9654 intel_display_capture_error_state(struct drm_device *dev)
9656 drm_i915_private_t *dev_priv = dev->dev_private;
9657 struct intel_display_error_state *error;
9658 enum transcoder cpu_transcoder;
9661 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9666 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9668 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9669 error->cursor[i].control = I915_READ(CURCNTR(i));
9670 error->cursor[i].position = I915_READ(CURPOS(i));
9671 error->cursor[i].base = I915_READ(CURBASE(i));
9673 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9674 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9675 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9678 error->plane[i].control = I915_READ(DSPCNTR(i));
9679 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9680 if (INTEL_INFO(dev)->gen <= 3) {
9681 error->plane[i].size = I915_READ(DSPSIZE(i));
9682 error->plane[i].pos = I915_READ(DSPPOS(i));
9684 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9685 error->plane[i].addr = I915_READ(DSPADDR(i));
9686 if (INTEL_INFO(dev)->gen >= 4) {
9687 error->plane[i].surface = I915_READ(DSPSURF(i));
9688 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9691 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9692 error->pipe[i].source = I915_READ(PIPESRC(i));
9693 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9694 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9695 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9696 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9697 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9698 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9705 intel_display_print_error_state(struct seq_file *m,
9706 struct drm_device *dev,
9707 struct intel_display_error_state *error)
9711 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9713 seq_printf(m, "Pipe [%d]:\n", i);
9714 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9715 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9716 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9717 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9718 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9719 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9720 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9721 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9723 seq_printf(m, "Plane [%d]:\n", i);
9724 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9725 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9726 if (INTEL_INFO(dev)->gen <= 3) {
9727 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9728 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9730 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9731 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9732 if (INTEL_INFO(dev)->gen >= 4) {
9733 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9734 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9737 seq_printf(m, "Cursor [%d]:\n", i);
9738 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9739 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9740 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);