drivers/gpu/drm/radeon/rv770.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/firmware.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/slab.h>
  31 #include <drm/drmP.h>
  32 #include "radeon.h"
  33 #include "radeon_asic.h"
  34 #include <drm/radeon_drm.h>
  35 #include "rv770d.h"
  36 #include "atom.h"
  37 #include "avivod.h"
  38
  39 #define R700_PFP_UCODE_SIZE 848
  40 #define R700_PM4_UCODE_SIZE 1360
  41
  42 static void rv770_gpu_init(struct radeon_device *rdev);
  43 void rv770_fini(struct radeon_device *rdev);
  44 static void rv770_pcie_gen2_enable(struct radeon_device *rdev);
  45 int evergreen_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk);
  46
  47 int rv770_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk)
  48 {
  49         unsigned fb_div = 0, vclk_div = 0, dclk_div = 0;
  50         int r;
  51
  52         /* RV740 uses evergreen uvd clk programming */
  53         if (rdev->family == CHIP_RV740)
  54                 return evergreen_set_uvd_clocks(rdev, vclk, dclk);
  55
  56         /* bypass vclk and dclk with bclk */
  57         WREG32_P(CG_UPLL_FUNC_CNTL_2,
  58                  VCLK_SRC_SEL(1) | DCLK_SRC_SEL(1),
  59                  ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
  60
  61         if (!vclk || !dclk) {
  62                 /* keep the Bypass mode, put PLL to sleep */
  63                 WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_SLEEP_MASK, ~UPLL_SLEEP_MASK);
  64                 return 0;
  65         }
  66
  67         r = radeon_uvd_calc_upll_dividers(rdev, vclk, dclk, 50000, 160000,
  68                                           43663, 0x03FFFFFE, 1, 30, ~0,
  69                                           &fb_div, &vclk_div, &dclk_div);
  70         if (r)
  71                 return r;
  72
  73         fb_div |= 1;
  74         vclk_div -= 1;
  75         dclk_div -= 1;
  76
  77         /* set UPLL_FB_DIV to 0x50000 */
  78         WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(0x50000), ~UPLL_FB_DIV_MASK);
  79
  80         /* deassert UPLL_RESET and UPLL_SLEEP */
  81         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~(UPLL_RESET_MASK | UPLL_SLEEP_MASK));
  82
  83         /* assert BYPASS EN and FB_DIV[0] <- ??? why? */
  84         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_BYPASS_EN_MASK, ~UPLL_BYPASS_EN_MASK);
  85         WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(1), ~UPLL_FB_DIV(1));
  86
  87         r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
  88         if (r)
  89                 return r;
  90
  91         /* assert PLL_RESET */
  92         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_RESET_MASK, ~UPLL_RESET_MASK);
  93
  94         /* set the required FB_DIV, REF_DIV, Post divder values */
  95         WREG32_P(CG_UPLL_FUNC_CNTL, UPLL_REF_DIV(1), ~UPLL_REF_DIV_MASK);
  96         WREG32_P(CG_UPLL_FUNC_CNTL_2,
  97                  UPLL_SW_HILEN(vclk_div >> 1) |
  98                  UPLL_SW_LOLEN((vclk_div >> 1) + (vclk_div & 1)) |
  99                  UPLL_SW_HILEN2(dclk_div >> 1) |
 100                  UPLL_SW_LOLEN2((dclk_div >> 1) + (dclk_div & 1)),
 101                  ~UPLL_SW_MASK);
 102
 103         WREG32_P(CG_UPLL_FUNC_CNTL_3, UPLL_FB_DIV(fb_div),
 104                  ~UPLL_FB_DIV_MASK);
 105
 106         /* give the PLL some time to settle */
 107         mdelay(15);
 108
 109         /* deassert PLL_RESET */
 110         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_RESET_MASK);
 111
 112         mdelay(15);
 113
 114         /* deassert BYPASS EN and FB_DIV[0] <- ??? why? */
 115         WREG32_P(CG_UPLL_FUNC_CNTL, 0, ~UPLL_BYPASS_EN_MASK);
 116         WREG32_P(CG_UPLL_FUNC_CNTL_3, 0, ~UPLL_FB_DIV(1));
 117
 118         r = radeon_uvd_send_upll_ctlreq(rdev, CG_UPLL_FUNC_CNTL);
 119         if (r)
 120                 return r;
 121
 122         /* switch VCLK and DCLK selection */
 123         WREG32_P(CG_UPLL_FUNC_CNTL_2,
 124                  VCLK_SRC_SEL(2) | DCLK_SRC_SEL(2),
 125                  ~(VCLK_SRC_SEL_MASK | DCLK_SRC_SEL_MASK));
 126
 127         mdelay(100);
 128
 129         return 0;
 130 }
 131
 132 static const u32 r7xx_golden_registers[] =
 133 {
 134         0x8d00, 0xffffffff, 0x0e0e0074,
 135         0x8d04, 0xffffffff, 0x013a2b34,
 136         0x9508, 0xffffffff, 0x00000002,
 137         0x8b20, 0xffffffff, 0,
 138         0x88c4, 0xffffffff, 0x000000c2,
 139         0x28350, 0xffffffff, 0,
 140         0x9058, 0xffffffff, 0x0fffc40f,
 141         0x240c, 0xffffffff, 0x00000380,
 142         0x733c, 0xffffffff, 0x00000002,
 143         0x2650, 0x00040000, 0,
 144         0x20bc, 0x00040000, 0,
 145         0x7300, 0xffffffff, 0x001000f0
 146 };
 147
 148 static const u32 r7xx_golden_dyn_gpr_registers[] =
 149 {
 150         0x8db0, 0xffffffff, 0x98989898,
 151         0x8db4, 0xffffffff, 0x98989898,
 152         0x8db8, 0xffffffff, 0x98989898,
 153         0x8dbc, 0xffffffff, 0x98989898,
 154         0x8dc0, 0xffffffff, 0x98989898,
 155         0x8dc4, 0xffffffff, 0x98989898,
 156         0x8dc8, 0xffffffff, 0x98989898,
 157         0x8dcc, 0xffffffff, 0x98989898,
 158         0x88c4, 0xffffffff, 0x00000082
 159 };
 160
 161 static const u32 rv770_golden_registers[] =
 162 {
 163         0x562c, 0xffffffff, 0,
 164         0x3f90, 0xffffffff, 0,
 165         0x9148, 0xffffffff, 0,
 166         0x3f94, 0xffffffff, 0,
 167         0x914c, 0xffffffff, 0,
 168         0x9698, 0x18000000, 0x18000000
 169 };
 170
 171 static const u32 rv770ce_golden_registers[] =
 172 {
 173         0x562c, 0xffffffff, 0,
 174         0x3f90, 0xffffffff, 0x00cc0000,
 175         0x9148, 0xffffffff, 0x00cc0000,
 176         0x3f94, 0xffffffff, 0x00cc0000,
 177         0x914c, 0xffffffff, 0x00cc0000,
 178         0x9b7c, 0xffffffff, 0x00fa0000,
 179         0x3f8c, 0xffffffff, 0x00fa0000,
 180         0x9698, 0x18000000, 0x18000000
 181 };
 182
 183 static const u32 rv770_mgcg_init[] =
 184 {
 185         0x8bcc, 0xffffffff, 0x130300f9,
 186         0x5448, 0xffffffff, 0x100,
 187         0x55e4, 0xffffffff, 0x100,
 188         0x160c, 0xffffffff, 0x100,
 189         0x5644, 0xffffffff, 0x100,
 190         0xc164, 0xffffffff, 0x100,
 191         0x8a18, 0xffffffff, 0x100,
 192         0x897c, 0xffffffff, 0x8000100,
 193         0x8b28, 0xffffffff, 0x3c000100,
 194         0x9144, 0xffffffff, 0x100,
 195         0x9a1c, 0xffffffff, 0x10000,
 196         0x9a50, 0xffffffff, 0x100,
 197         0x9a1c, 0xffffffff, 0x10001,
 198         0x9a50, 0xffffffff, 0x100,
 199         0x9a1c, 0xffffffff, 0x10002,
 200         0x9a50, 0xffffffff, 0x100,
 201         0x9a1c, 0xffffffff, 0x10003,
 202         0x9a50, 0xffffffff, 0x100,
 203         0x9a1c, 0xffffffff, 0x0,
 204         0x9870, 0xffffffff, 0x100,
 205         0x8d58, 0xffffffff, 0x100,
 206         0x9500, 0xffffffff, 0x0,
 207         0x9510, 0xffffffff, 0x100,
 208         0x9500, 0xffffffff, 0x1,
 209         0x9510, 0xffffffff, 0x100,
 210         0x9500, 0xffffffff, 0x2,
 211         0x9510, 0xffffffff, 0x100,
 212         0x9500, 0xffffffff, 0x3,
 213         0x9510, 0xffffffff, 0x100,
 214         0x9500, 0xffffffff, 0x4,
 215         0x9510, 0xffffffff, 0x100,
 216         0x9500, 0xffffffff, 0x5,
 217         0x9510, 0xffffffff, 0x100,
 218         0x9500, 0xffffffff, 0x6,
 219         0x9510, 0xffffffff, 0x100,
 220         0x9500, 0xffffffff, 0x7,
 221         0x9510, 0xffffffff, 0x100,
 222         0x9500, 0xffffffff, 0x8,
 223         0x9510, 0xffffffff, 0x100,
 224         0x9500, 0xffffffff, 0x9,
 225         0x9510, 0xffffffff, 0x100,
 226         0x9500, 0xffffffff, 0x8000,
 227         0x9490, 0xffffffff, 0x0,
 228         0x949c, 0xffffffff, 0x100,
 229         0x9490, 0xffffffff, 0x1,
 230         0x949c, 0xffffffff, 0x100,
 231         0x9490, 0xffffffff, 0x2,
 232         0x949c, 0xffffffff, 0x100,
 233         0x9490, 0xffffffff, 0x3,
 234         0x949c, 0xffffffff, 0x100,
 235         0x9490, 0xffffffff, 0x4,
 236         0x949c, 0xffffffff, 0x100,
 237         0x9490, 0xffffffff, 0x5,
 238         0x949c, 0xffffffff, 0x100,
 239         0x9490, 0xffffffff, 0x6,
 240         0x949c, 0xffffffff, 0x100,
 241         0x9490, 0xffffffff, 0x7,
 242         0x949c, 0xffffffff, 0x100,
 243         0x9490, 0xffffffff, 0x8,
 244         0x949c, 0xffffffff, 0x100,
 245         0x9490, 0xffffffff, 0x9,
 246         0x949c, 0xffffffff, 0x100,
 247         0x9490, 0xffffffff, 0x8000,
 248         0x9604, 0xffffffff, 0x0,
 249         0x9654, 0xffffffff, 0x100,
 250         0x9604, 0xffffffff, 0x1,
 251         0x9654, 0xffffffff, 0x100,
 252         0x9604, 0xffffffff, 0x2,
 253         0x9654, 0xffffffff, 0x100,
 254         0x9604, 0xffffffff, 0x3,
 255         0x9654, 0xffffffff, 0x100,
 256         0x9604, 0xffffffff, 0x4,
 257         0x9654, 0xffffffff, 0x100,
 258         0x9604, 0xffffffff, 0x5,
 259         0x9654, 0xffffffff, 0x100,
 260         0x9604, 0xffffffff, 0x6,
 261         0x9654, 0xffffffff, 0x100,
 262         0x9604, 0xffffffff, 0x7,
 263         0x9654, 0xffffffff, 0x100,
 264         0x9604, 0xffffffff, 0x8,
 265         0x9654, 0xffffffff, 0x100,
 266         0x9604, 0xffffffff, 0x9,
 267         0x9654, 0xffffffff, 0x100,
 268         0x9604, 0xffffffff, 0x80000000,
 269         0x9030, 0xffffffff, 0x100,
 270         0x9034, 0xffffffff, 0x100,
 271         0x9038, 0xffffffff, 0x100,
 272         0x903c, 0xffffffff, 0x100,
 273         0x9040, 0xffffffff, 0x100,
 274         0xa200, 0xffffffff, 0x100,
 275         0xa204, 0xffffffff, 0x100,
 276         0xa208, 0xffffffff, 0x100,
 277         0xa20c, 0xffffffff, 0x100,
 278         0x971c, 0xffffffff, 0x100,
 279         0x915c, 0xffffffff, 0x00020001,
 280         0x9160, 0xffffffff, 0x00040003,
 281         0x916c, 0xffffffff, 0x00060005,
 282         0x9170, 0xffffffff, 0x00080007,
 283         0x9174, 0xffffffff, 0x000a0009,
 284         0x9178, 0xffffffff, 0x000c000b,
 285         0x917c, 0xffffffff, 0x000e000d,
 286         0x9180, 0xffffffff, 0x0010000f,
 287         0x918c, 0xffffffff, 0x00120011,
 288         0x9190, 0xffffffff, 0x00140013,
 289         0x9194, 0xffffffff, 0x00020001,
 290         0x9198, 0xffffffff, 0x00040003,
 291         0x919c, 0xffffffff, 0x00060005,
 292         0x91a8, 0xffffffff, 0x00080007,
 293         0x91ac, 0xffffffff, 0x000a0009,
 294         0x91b0, 0xffffffff, 0x000c000b,
 295         0x91b4, 0xffffffff, 0x000e000d,
 296         0x91b8, 0xffffffff, 0x0010000f,
 297         0x91c4, 0xffffffff, 0x00120011,
 298         0x91c8, 0xffffffff, 0x00140013,
 299         0x91cc, 0xffffffff, 0x00020001,
 300         0x91d0, 0xffffffff, 0x00040003,
 301         0x91d4, 0xffffffff, 0x00060005,
 302         0x91e0, 0xffffffff, 0x00080007,
 303         0x91e4, 0xffffffff, 0x000a0009,
 304         0x91e8, 0xffffffff, 0x000c000b,
 305         0x91ec, 0xffffffff, 0x00020001,
 306         0x91f0, 0xffffffff, 0x00040003,
 307         0x91f4, 0xffffffff, 0x00060005,
 308         0x9200, 0xffffffff, 0x00080007,
 309         0x9204, 0xffffffff, 0x000a0009,
 310         0x9208, 0xffffffff, 0x000c000b,
 311         0x920c, 0xffffffff, 0x000e000d,
 312         0x9210, 0xffffffff, 0x0010000f,
 313         0x921c, 0xffffffff, 0x00120011,
 314         0x9220, 0xffffffff, 0x00140013,
 315         0x9224, 0xffffffff, 0x00020001,
 316         0x9228, 0xffffffff, 0x00040003,
 317         0x922c, 0xffffffff, 0x00060005,
 318         0x9238, 0xffffffff, 0x00080007,
 319         0x923c, 0xffffffff, 0x000a0009,
 320         0x9240, 0xffffffff, 0x000c000b,
 321         0x9244, 0xffffffff, 0x000e000d,
 322         0x9248, 0xffffffff, 0x0010000f,
 323         0x9254, 0xffffffff, 0x00120011,
 324         0x9258, 0xffffffff, 0x00140013,
 325         0x925c, 0xffffffff, 0x00020001,
 326         0x9260, 0xffffffff, 0x00040003,
 327         0x9264, 0xffffffff, 0x00060005,
 328         0x9270, 0xffffffff, 0x00080007,
 329         0x9274, 0xffffffff, 0x000a0009,
 330         0x9278, 0xffffffff, 0x000c000b,
 331         0x927c, 0xffffffff, 0x000e000d,
 332         0x9280, 0xffffffff, 0x0010000f,
 333         0x928c, 0xffffffff, 0x00120011,
 334         0x9290, 0xffffffff, 0x00140013,
 335         0x9294, 0xffffffff, 0x00020001,
 336         0x929c, 0xffffffff, 0x00040003,
 337         0x92a0, 0xffffffff, 0x00060005,
 338         0x92a4, 0xffffffff, 0x00080007
 339 };
 340
 341 static const u32 rv710_golden_registers[] =
 342 {
 343         0x3f90, 0x00ff0000, 0x00fc0000,
 344         0x9148, 0x00ff0000, 0x00fc0000,
 345         0x3f94, 0x00ff0000, 0x00fc0000,
 346         0x914c, 0x00ff0000, 0x00fc0000,
 347         0xb4c, 0x00000020, 0x00000020,
 348         0xa180, 0xffffffff, 0x00003f3f
 349 };
 350
 351 static const u32 rv710_mgcg_init[] =
 352 {
 353         0x8bcc, 0xffffffff, 0x13030040,
 354         0x5448, 0xffffffff, 0x100,
 355         0x55e4, 0xffffffff, 0x100,
 356         0x160c, 0xffffffff, 0x100,
 357         0x5644, 0xffffffff, 0x100,
 358         0xc164, 0xffffffff, 0x100,
 359         0x8a18, 0xffffffff, 0x100,
 360         0x897c, 0xffffffff, 0x8000100,
 361         0x8b28, 0xffffffff, 0x3c000100,
 362         0x9144, 0xffffffff, 0x100,
 363         0x9a1c, 0xffffffff, 0x10000,
 364         0x9a50, 0xffffffff, 0x100,
 365         0x9a1c, 0xffffffff, 0x0,
 366         0x9870, 0xffffffff, 0x100,
 367         0x8d58, 0xffffffff, 0x100,
 368         0x9500, 0xffffffff, 0x0,
 369         0x9510, 0xffffffff, 0x100,
 370         0x9500, 0xffffffff, 0x1,
 371         0x9510, 0xffffffff, 0x100,
 372         0x9500, 0xffffffff, 0x8000,
 373         0x9490, 0xffffffff, 0x0,
 374         0x949c, 0xffffffff, 0x100,
 375         0x9490, 0xffffffff, 0x1,
 376         0x949c, 0xffffffff, 0x100,
 377         0x9490, 0xffffffff, 0x8000,
 378         0x9604, 0xffffffff, 0x0,
 379         0x9654, 0xffffffff, 0x100,
 380         0x9604, 0xffffffff, 0x1,
 381         0x9654, 0xffffffff, 0x100,
 382         0x9604, 0xffffffff, 0x80000000,
 383         0x9030, 0xffffffff, 0x100,
 384         0x9034, 0xffffffff, 0x100,
 385         0x9038, 0xffffffff, 0x100,
 386         0x903c, 0xffffffff, 0x100,
 387         0x9040, 0xffffffff, 0x100,
 388         0xa200, 0xffffffff, 0x100,
 389         0xa204, 0xffffffff, 0x100,
 390         0xa208, 0xffffffff, 0x100,
 391         0xa20c, 0xffffffff, 0x100,
 392         0x971c, 0xffffffff, 0x100,
 393         0x915c, 0xffffffff, 0x00020001,
 394         0x9174, 0xffffffff, 0x00000003,
 395         0x9178, 0xffffffff, 0x00050001,
 396         0x917c, 0xffffffff, 0x00030002,
 397         0x918c, 0xffffffff, 0x00000004,
 398         0x9190, 0xffffffff, 0x00070006,
 399         0x9194, 0xffffffff, 0x00050001,
 400         0x9198, 0xffffffff, 0x00030002,
 401         0x91a8, 0xffffffff, 0x00000004,
 402         0x91ac, 0xffffffff, 0x00070006,
 403         0x91e8, 0xffffffff, 0x00000001,
 404         0x9294, 0xffffffff, 0x00000001,
 405         0x929c, 0xffffffff, 0x00000002,
 406         0x92a0, 0xffffffff, 0x00040003,
 407         0x9150, 0xffffffff, 0x4d940000
 408 };
 409
 410 static const u32 rv730_golden_registers[] =
 411 {
 412         0x3f90, 0x00ff0000, 0x00f00000,
 413         0x9148, 0x00ff0000, 0x00f00000,
 414         0x3f94, 0x00ff0000, 0x00f00000,
 415         0x914c, 0x00ff0000, 0x00f00000,
 416         0x900c, 0xffffffff, 0x003b033f,
 417         0xb4c, 0x00000020, 0x00000020,
 418         0xa180, 0xffffffff, 0x00003f3f
 419 };
 420
 421 static const u32 rv730_mgcg_init[] =
 422 {
 423         0x8bcc, 0xffffffff, 0x130300f9,
 424         0x5448, 0xffffffff, 0x100,
 425         0x55e4, 0xffffffff, 0x100,
 426         0x160c, 0xffffffff, 0x100,
 427         0x5644, 0xffffffff, 0x100,
 428         0xc164, 0xffffffff, 0x100,
 429         0x8a18, 0xffffffff, 0x100,
 430         0x897c, 0xffffffff, 0x8000100,
 431         0x8b28, 0xffffffff, 0x3c000100,
 432         0x9144, 0xffffffff, 0x100,
 433         0x9a1c, 0xffffffff, 0x10000,
 434         0x9a50, 0xffffffff, 0x100,
 435         0x9a1c, 0xffffffff, 0x10001,
 436         0x9a50, 0xffffffff, 0x100,
 437         0x9a1c, 0xffffffff, 0x0,
 438         0x9870, 0xffffffff, 0x100,
 439         0x8d58, 0xffffffff, 0x100,
 440         0x9500, 0xffffffff, 0x0,
 441         0x9510, 0xffffffff, 0x100,
 442         0x9500, 0xffffffff, 0x1,
 443         0x9510, 0xffffffff, 0x100,
 444         0x9500, 0xffffffff, 0x2,
 445         0x9510, 0xffffffff, 0x100,
 446         0x9500, 0xffffffff, 0x3,
 447         0x9510, 0xffffffff, 0x100,
 448         0x9500, 0xffffffff, 0x4,
 449         0x9510, 0xffffffff, 0x100,
 450         0x9500, 0xffffffff, 0x5,
 451         0x9510, 0xffffffff, 0x100,
 452         0x9500, 0xffffffff, 0x6,
 453         0x9510, 0xffffffff, 0x100,
 454         0x9500, 0xffffffff, 0x7,
 455         0x9510, 0xffffffff, 0x100,
 456         0x9500, 0xffffffff, 0x8000,
 457         0x9490, 0xffffffff, 0x0,
 458         0x949c, 0xffffffff, 0x100,
 459         0x9490, 0xffffffff, 0x1,
 460         0x949c, 0xffffffff, 0x100,
 461         0x9490, 0xffffffff, 0x2,
 462         0x949c, 0xffffffff, 0x100,
 463         0x9490, 0xffffffff, 0x3,
 464         0x949c, 0xffffffff, 0x100,
 465         0x9490, 0xffffffff, 0x4,
 466         0x949c, 0xffffffff, 0x100,
 467         0x9490, 0xffffffff, 0x5,
 468         0x949c, 0xffffffff, 0x100,
 469         0x9490, 0xffffffff, 0x6,
 470         0x949c, 0xffffffff, 0x100,
 471         0x9490, 0xffffffff, 0x7,
 472         0x949c, 0xffffffff, 0x100,
 473         0x9490, 0xffffffff, 0x8000,
 474         0x9604, 0xffffffff, 0x0,
 475         0x9654, 0xffffffff, 0x100,
 476         0x9604, 0xffffffff, 0x1,
 477         0x9654, 0xffffffff, 0x100,
 478         0x9604, 0xffffffff, 0x2,
 479         0x9654, 0xffffffff, 0x100,
 480         0x9604, 0xffffffff, 0x3,
 481         0x9654, 0xffffffff, 0x100,
 482         0x9604, 0xffffffff, 0x4,
 483         0x9654, 0xffffffff, 0x100,
 484         0x9604, 0xffffffff, 0x5,
 485         0x9654, 0xffffffff, 0x100,
 486         0x9604, 0xffffffff, 0x6,
 487         0x9654, 0xffffffff, 0x100,
 488         0x9604, 0xffffffff, 0x7,
 489         0x9654, 0xffffffff, 0x100,
 490         0x9604, 0xffffffff, 0x80000000,
 491         0x9030, 0xffffffff, 0x100,
 492         0x9034, 0xffffffff, 0x100,
 493         0x9038, 0xffffffff, 0x100,
 494         0x903c, 0xffffffff, 0x100,
 495         0x9040, 0xffffffff, 0x100,
 496         0xa200, 0xffffffff, 0x100,
 497         0xa204, 0xffffffff, 0x100,
 498         0xa208, 0xffffffff, 0x100,
 499         0xa20c, 0xffffffff, 0x100,
 500         0x971c, 0xffffffff, 0x100,
 501         0x915c, 0xffffffff, 0x00020001,
 502         0x916c, 0xffffffff, 0x00040003,
 503         0x9170, 0xffffffff, 0x00000005,
 504         0x9178, 0xffffffff, 0x00050001,
 505         0x917c, 0xffffffff, 0x00030002,
 506         0x918c, 0xffffffff, 0x00000004,
 507         0x9190, 0xffffffff, 0x00070006,
 508         0x9194, 0xffffffff, 0x00050001,
 509         0x9198, 0xffffffff, 0x00030002,
 510         0x91a8, 0xffffffff, 0x00000004,
 511         0x91ac, 0xffffffff, 0x00070006,
 512         0x91b0, 0xffffffff, 0x00050001,
 513         0x91b4, 0xffffffff, 0x00030002,
 514         0x91c4, 0xffffffff, 0x00000004,
 515         0x91c8, 0xffffffff, 0x00070006,
 516         0x91cc, 0xffffffff, 0x00050001,
 517         0x91d0, 0xffffffff, 0x00030002,
 518         0x91e0, 0xffffffff, 0x00000004,
 519         0x91e4, 0xffffffff, 0x00070006,
 520         0x91e8, 0xffffffff, 0x00000001,
 521         0x91ec, 0xffffffff, 0x00050001,
 522         0x91f0, 0xffffffff, 0x00030002,
 523         0x9200, 0xffffffff, 0x00000004,
 524         0x9204, 0xffffffff, 0x00070006,
 525         0x9208, 0xffffffff, 0x00050001,
 526         0x920c, 0xffffffff, 0x00030002,
 527         0x921c, 0xffffffff, 0x00000004,
 528         0x9220, 0xffffffff, 0x00070006,
 529         0x9224, 0xffffffff, 0x00050001,
 530         0x9228, 0xffffffff, 0x00030002,
 531         0x9238, 0xffffffff, 0x00000004,
 532         0x923c, 0xffffffff, 0x00070006,
 533         0x9240, 0xffffffff, 0x00050001,
 534         0x9244, 0xffffffff, 0x00030002,
 535         0x9254, 0xffffffff, 0x00000004,
 536         0x9258, 0xffffffff, 0x00070006,
 537         0x9294, 0xffffffff, 0x00000001,
 538         0x929c, 0xffffffff, 0x00000002,
 539         0x92a0, 0xffffffff, 0x00040003,
 540         0x92a4, 0xffffffff, 0x00000005
 541 };
 542
 543 static const u32 rv740_golden_registers[] =
 544 {
 545         0x88c4, 0xffffffff, 0x00000082,
 546         0x28a50, 0xfffffffc, 0x00000004,
 547         0x2650, 0x00040000, 0,
 548         0x20bc, 0x00040000, 0,
 549         0x733c, 0xffffffff, 0x00000002,
 550         0x7300, 0xffffffff, 0x001000f0,
 551         0x3f90, 0x00ff0000, 0,
 552         0x9148, 0x00ff0000, 0,
 553         0x3f94, 0x00ff0000, 0,
 554         0x914c, 0x00ff0000, 0,
 555         0x240c, 0xffffffff, 0x00000380,
 556         0x8a14, 0x00000007, 0x00000007,
 557         0x8b24, 0xffffffff, 0x00ff0fff,
 558         0x28a4c, 0xffffffff, 0x00004000,
 559         0xa180, 0xffffffff, 0x00003f3f,
 560         0x8d00, 0xffffffff, 0x0e0e003a,
 561         0x8d04, 0xffffffff, 0x013a0e2a,
 562         0x8c00, 0xffffffff, 0xe400000f,
 563         0x8db0, 0xffffffff, 0x98989898,
 564         0x8db4, 0xffffffff, 0x98989898,
 565         0x8db8, 0xffffffff, 0x98989898,
 566         0x8dbc, 0xffffffff, 0x98989898,
 567         0x8dc0, 0xffffffff, 0x98989898,
 568         0x8dc4, 0xffffffff, 0x98989898,
 569         0x8dc8, 0xffffffff, 0x98989898,
 570         0x8dcc, 0xffffffff, 0x98989898,
 571         0x9058, 0xffffffff, 0x0fffc40f,
 572         0x900c, 0xffffffff, 0x003b033f,
 573         0x28350, 0xffffffff, 0,
 574         0x8cf0, 0x1fffffff, 0x08e00420,
 575         0x9508, 0xffffffff, 0x00000002,
 576         0x88c4, 0xffffffff, 0x000000c2,
 577         0x9698, 0x18000000, 0x18000000
 578 };
 579
 580 static const u32 rv740_mgcg_init[] =
 581 {
 582         0x8bcc, 0xffffffff, 0x13030100,
 583         0x5448, 0xffffffff, 0x100,
 584         0x55e4, 0xffffffff, 0x100,
 585         0x160c, 0xffffffff, 0x100,
 586         0x5644, 0xffffffff, 0x100,
 587         0xc164, 0xffffffff, 0x100,
 588         0x8a18, 0xffffffff, 0x100,
 589         0x897c, 0xffffffff, 0x100,
 590         0x8b28, 0xffffffff, 0x100,
 591         0x9144, 0xffffffff, 0x100,
 592         0x9a1c, 0xffffffff, 0x10000,
 593         0x9a50, 0xffffffff, 0x100,
 594         0x9a1c, 0xffffffff, 0x10001,
 595         0x9a50, 0xffffffff, 0x100,
 596         0x9a1c, 0xffffffff, 0x10002,
 597         0x9a50, 0xffffffff, 0x100,
 598         0x9a1c, 0xffffffff, 0x10003,
 599         0x9a50, 0xffffffff, 0x100,
 600         0x9a1c, 0xffffffff, 0x0,
 601         0x9870, 0xffffffff, 0x100,
 602         0x8d58, 0xffffffff, 0x100,
 603         0x9500, 0xffffffff, 0x0,
 604         0x9510, 0xffffffff, 0x100,
 605         0x9500, 0xffffffff, 0x1,
 606         0x9510, 0xffffffff, 0x100,
 607         0x9500, 0xffffffff, 0x2,
 608         0x9510, 0xffffffff, 0x100,
 609         0x9500, 0xffffffff, 0x3,
 610         0x9510, 0xffffffff, 0x100,
 611         0x9500, 0xffffffff, 0x4,
 612         0x9510, 0xffffffff, 0x100,
 613         0x9500, 0xffffffff, 0x5,
 614         0x9510, 0xffffffff, 0x100,
 615         0x9500, 0xffffffff, 0x6,
 616         0x9510, 0xffffffff, 0x100,
 617         0x9500, 0xffffffff, 0x7,
 618         0x9510, 0xffffffff, 0x100,
 619         0x9500, 0xffffffff, 0x8000,
 620         0x9490, 0xffffffff, 0x0,
 621         0x949c, 0xffffffff, 0x100,
 622         0x9490, 0xffffffff, 0x1,
 623         0x949c, 0xffffffff, 0x100,
 624         0x9490, 0xffffffff, 0x2,
 625         0x949c, 0xffffffff, 0x100,
 626         0x9490, 0xffffffff, 0x3,
 627         0x949c, 0xffffffff, 0x100,
 628         0x9490, 0xffffffff, 0x4,
 629         0x949c, 0xffffffff, 0x100,
 630         0x9490, 0xffffffff, 0x5,
 631         0x949c, 0xffffffff, 0x100,
 632         0x9490, 0xffffffff, 0x6,
 633         0x949c, 0xffffffff, 0x100,
 634         0x9490, 0xffffffff, 0x7,
 635         0x949c, 0xffffffff, 0x100,
 636         0x9490, 0xffffffff, 0x8000,
 637         0x9604, 0xffffffff, 0x0,
 638         0x9654, 0xffffffff, 0x100,
 639         0x9604, 0xffffffff, 0x1,
 640         0x9654, 0xffffffff, 0x100,
 641         0x9604, 0xffffffff, 0x2,
 642         0x9654, 0xffffffff, 0x100,
 643         0x9604, 0xffffffff, 0x3,
 644         0x9654, 0xffffffff, 0x100,
 645         0x9604, 0xffffffff, 0x4,
 646         0x9654, 0xffffffff, 0x100,
 647         0x9604, 0xffffffff, 0x5,
 648         0x9654, 0xffffffff, 0x100,
 649         0x9604, 0xffffffff, 0x6,
 650         0x9654, 0xffffffff, 0x100,
 651         0x9604, 0xffffffff, 0x7,
 652         0x9654, 0xffffffff, 0x100,
 653         0x9604, 0xffffffff, 0x80000000,
 654         0x9030, 0xffffffff, 0x100,
 655         0x9034, 0xffffffff, 0x100,
 656         0x9038, 0xffffffff, 0x100,
 657         0x903c, 0xffffffff, 0x100,
 658         0x9040, 0xffffffff, 0x100,
 659         0xa200, 0xffffffff, 0x100,
 660         0xa204, 0xffffffff, 0x100,
 661         0xa208, 0xffffffff, 0x100,
 662         0xa20c, 0xffffffff, 0x100,
 663         0x971c, 0xffffffff, 0x100,
 664         0x915c, 0xffffffff, 0x00020001,
 665         0x9160, 0xffffffff, 0x00040003,
 666         0x916c, 0xffffffff, 0x00060005,
 667         0x9170, 0xffffffff, 0x00080007,
 668         0x9174, 0xffffffff, 0x000a0009,
 669         0x9178, 0xffffffff, 0x000c000b,
 670         0x917c, 0xffffffff, 0x000e000d,
 671         0x9180, 0xffffffff, 0x0010000f,
 672         0x918c, 0xffffffff, 0x00120011,
 673         0x9190, 0xffffffff, 0x00140013,
 674         0x9194, 0xffffffff, 0x00020001,
 675         0x9198, 0xffffffff, 0x00040003,
 676         0x919c, 0xffffffff, 0x00060005,
 677         0x91a8, 0xffffffff, 0x00080007,
 678         0x91ac, 0xffffffff, 0x000a0009,
 679         0x91b0, 0xffffffff, 0x000c000b,
 680         0x91b4, 0xffffffff, 0x000e000d,
 681         0x91b8, 0xffffffff, 0x0010000f,
 682         0x91c4, 0xffffffff, 0x00120011,
 683         0x91c8, 0xffffffff, 0x00140013,
 684         0x91cc, 0xffffffff, 0x00020001,
 685         0x91d0, 0xffffffff, 0x00040003,
 686         0x91d4, 0xffffffff, 0x00060005,
 687         0x91e0, 0xffffffff, 0x00080007,
 688         0x91e4, 0xffffffff, 0x000a0009,
 689         0x91e8, 0xffffffff, 0x000c000b,
 690         0x91ec, 0xffffffff, 0x00020001,
 691         0x91f0, 0xffffffff, 0x00040003,
 692         0x91f4, 0xffffffff, 0x00060005,
 693         0x9200, 0xffffffff, 0x00080007,
 694         0x9204, 0xffffffff, 0x000a0009,
 695         0x9208, 0xffffffff, 0x000c000b,
 696         0x920c, 0xffffffff, 0x000e000d,
 697         0x9210, 0xffffffff, 0x0010000f,
 698         0x921c, 0xffffffff, 0x00120011,
 699         0x9220, 0xffffffff, 0x00140013,
 700         0x9224, 0xffffffff, 0x00020001,
 701         0x9228, 0xffffffff, 0x00040003,
 702         0x922c, 0xffffffff, 0x00060005,
 703         0x9238, 0xffffffff, 0x00080007,
 704         0x923c, 0xffffffff, 0x000a0009,
 705         0x9240, 0xffffffff, 0x000c000b,
 706         0x9244, 0xffffffff, 0x000e000d,
 707         0x9248, 0xffffffff, 0x0010000f,
 708         0x9254, 0xffffffff, 0x00120011,
 709         0x9258, 0xffffffff, 0x00140013,
 710         0x9294, 0xffffffff, 0x00020001,
 711         0x929c, 0xffffffff, 0x00040003,
 712         0x92a0, 0xffffffff, 0x00060005,
 713         0x92a4, 0xffffffff, 0x00080007
 714 };
 715
 716 static void rv770_init_golden_registers(struct radeon_device *rdev)
 717 {
 718         switch (rdev->family) {
 719         case CHIP_RV770:
 720                 radeon_program_register_sequence(rdev,
 721                                                  r7xx_golden_registers,
 722                                                  (const u32)ARRAY_SIZE(r7xx_golden_registers));
 723                 radeon_program_register_sequence(rdev,
 724                                                  r7xx_golden_dyn_gpr_registers,
 725                                                  (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
 726                 if (rdev->pdev->device == 0x994e)
 727                         radeon_program_register_sequence(rdev,
 728                                                          rv770ce_golden_registers,
 729                                                          (const u32)ARRAY_SIZE(rv770ce_golden_registers));
 730                 else
 731                         radeon_program_register_sequence(rdev,
 732                                                          rv770_golden_registers,
 733                                                          (const u32)ARRAY_SIZE(rv770_golden_registers));
 734                 radeon_program_register_sequence(rdev,
 735                                                  rv770_mgcg_init,
 736                                                  (const u32)ARRAY_SIZE(rv770_mgcg_init));
 737                 break;
 738         case CHIP_RV730:
 739                 radeon_program_register_sequence(rdev,
 740                                                  r7xx_golden_registers,
 741                                                  (const u32)ARRAY_SIZE(r7xx_golden_registers));
 742                 radeon_program_register_sequence(rdev,
 743                                                  r7xx_golden_dyn_gpr_registers,
 744                                                  (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
 745                 radeon_program_register_sequence(rdev,
 746                                                  rv730_golden_registers,
 747                                                  (const u32)ARRAY_SIZE(rv770_golden_registers));
 748                 radeon_program_register_sequence(rdev,
 749                                                  rv730_mgcg_init,
 750                                                  (const u32)ARRAY_SIZE(rv770_mgcg_init));
 751                 break;
 752         case CHIP_RV710:
 753                 radeon_program_register_sequence(rdev,
 754                                                  r7xx_golden_registers,
 755                                                  (const u32)ARRAY_SIZE(r7xx_golden_registers));
 756                 radeon_program_register_sequence(rdev,
 757                                                  r7xx_golden_dyn_gpr_registers,
 758                                                  (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers));
 759                 radeon_program_register_sequence(rdev,
 760                                                  rv710_golden_registers,
 761                                                  (const u32)ARRAY_SIZE(rv770_golden_registers));
 762                 radeon_program_register_sequence(rdev,
 763                                                  rv710_mgcg_init,
 764                                                  (const u32)ARRAY_SIZE(rv770_mgcg_init));
 765                 break;
 766         case CHIP_RV740:
 767                 radeon_program_register_sequence(rdev,
 768                                                  rv740_golden_registers,
 769                                                  (const u32)ARRAY_SIZE(rv770_golden_registers));
 770                 radeon_program_register_sequence(rdev,
 771                                                  rv740_mgcg_init,
 772                                                  (const u32)ARRAY_SIZE(rv770_mgcg_init));
 773                 break;
 774         default:
 775                 break;
 776         }
 777 }
 778
 779 #define PCIE_BUS_CLK                10000
 780 #define TCLK                        (PCIE_BUS_CLK / 10)
 781
 782 /**
 783  * rv770_get_xclk - get the xclk
 784  *
 785  * @rdev: radeon_device pointer
 786  *
 787  * Returns the reference clock used by the gfx engine
 788  * (r7xx-cayman).
 789  */
 790 u32 rv770_get_xclk(struct radeon_device *rdev)
 791 {
 792         u32 reference_clock = rdev->clock.spll.reference_freq;
 793         u32 tmp = RREG32(CG_CLKPIN_CNTL);
 794
 795         if (tmp & MUX_TCLK_TO_XCLK)
 796                 return TCLK;
 797
 798         if (tmp & XTALIN_DIVIDE)
 799                 return reference_clock / 4;
 800
 801         return reference_clock;
 802 }
 803
 804 int rv770_uvd_resume(struct radeon_device *rdev)
 805 {
 806         uint64_t addr;
 807         uint32_t chip_id, size;
 808         int r;
 809
 810         r = radeon_uvd_resume(rdev);
 811         if (r)
 812                 return r;
 813
 814         /* programm the VCPU memory controller bits 0-27 */
 815         addr = rdev->uvd.gpu_addr >> 3;
 816         size = RADEON_GPU_PAGE_ALIGN(rdev->uvd.fw_size + 4) >> 3;
 817         WREG32(UVD_VCPU_CACHE_OFFSET0, addr);
 818         WREG32(UVD_VCPU_CACHE_SIZE0, size);
 819
 820         addr += size;
 821         size = RADEON_UVD_STACK_SIZE >> 3;
 822         WREG32(UVD_VCPU_CACHE_OFFSET1, addr);
 823         WREG32(UVD_VCPU_CACHE_SIZE1, size);
 824
 825         addr += size;
 826         size = RADEON_UVD_HEAP_SIZE >> 3;
 827         WREG32(UVD_VCPU_CACHE_OFFSET2, addr);
 828         WREG32(UVD_VCPU_CACHE_SIZE2, size);
 829
 830         /* bits 28-31 */
 831         addr = (rdev->uvd.gpu_addr >> 28) & 0xF;
 832         WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0));
 833
 834         /* bits 32-39 */
 835         addr = (rdev->uvd.gpu_addr >> 32) & 0xFF;
 836         WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31));
 837
 838         /* tell firmware which hardware it is running on */
 839         switch (rdev->family) {
 840         default:
 841                 return -EINVAL;
 842         case CHIP_RV710:
 843                 chip_id = 0x01000005;
 844                 break;
 845         case CHIP_RV730:
 846                 chip_id = 0x01000006;
 847                 break;
 848         case CHIP_RV740:
 849                 chip_id = 0x01000007;
 850                 break;
 851         case CHIP_CYPRESS:
 852         case CHIP_HEMLOCK:
 853                 chip_id = 0x01000008;
 854                 break;
 855         case CHIP_JUNIPER:
 856                 chip_id = 0x01000009;
 857                 break;
 858         case CHIP_REDWOOD:
 859                 chip_id = 0x0100000a;
 860                 break;
 861         case CHIP_CEDAR:
 862                 chip_id = 0x0100000b;
 863                 break;
 864         case CHIP_SUMO:
 865         case CHIP_SUMO2:
 866                 chip_id = 0x0100000c;
 867                 break;
 868         case CHIP_PALM:
 869                 chip_id = 0x0100000e;
 870                 break;
 871         case CHIP_CAYMAN:
 872                 chip_id = 0x0100000f;
 873                 break;
 874         case CHIP_BARTS:
 875                 chip_id = 0x01000010;
 876                 break;
 877         case CHIP_TURKS:
 878                 chip_id = 0x01000011;
 879                 break;
 880         case CHIP_CAICOS:
 881                 chip_id = 0x01000012;
 882                 break;
 883         case CHIP_TAHITI:
 884                 chip_id = 0x01000014;
 885                 break;
 886         case CHIP_VERDE:
 887                 chip_id = 0x01000015;
 888                 break;
 889         case CHIP_PITCAIRN:
 890                 chip_id = 0x01000016;
 891                 break;
 892         case CHIP_ARUBA:
 893                 chip_id = 0x01000017;
 894                 break;
 895         }
 896         WREG32(UVD_VCPU_CHIP_ID, chip_id);
 897
 898         return 0;
 899 }
 900
 901 u32 rv770_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
 902 {
 903         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
 904         u32 tmp = RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset);
 905         int i;
 906
 907         /* Lock the graphics update lock */
 908         tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
 909         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 910
 911         /* update the scanout addresses */
 912         if (radeon_crtc->crtc_id) {
 913                 WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
 914                 WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
 915         } else {
 916                 WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
 917                 WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(crtc_base));
 918         }
 919         WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 920                (u32)crtc_base);
 921         WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
 922                (u32)crtc_base);
 923
 924         /* Wait for update_pending to go high. */
 925         for (i = 0; i < rdev->usec_timeout; i++) {
 926                 if (RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING)
 927                         break;
 928                 udelay(1);
 929         }
 930         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
 931
 932         /* Unlock the lock, so double-buffering can take place inside vblank */
 933         tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
 934         WREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
 935
 936         /* Return current update_pending status: */
 937         return RREG32(AVIVO_D1GRPH_UPDATE + radeon_crtc->crtc_offset) & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING;
 938 }
 939
 940 /* get temperature in millidegrees */
 941 int rv770_get_temp(struct radeon_device *rdev)
 942 {
 943         u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
 944                 ASIC_T_SHIFT;
 945         int actual_temp;
 946
 947         if (temp & 0x400)
 948                 actual_temp = -256;
 949         else if (temp & 0x200)
 950                 actual_temp = 255;
 951         else if (temp & 0x100) {
 952                 actual_temp = temp & 0x1ff;
 953                 actual_temp |= ~0x1ff;
 954         } else
 955                 actual_temp = temp & 0xff;
 956
 957         return (actual_temp * 1000) / 2;
 958 }
 959
 960 void rv770_pm_misc(struct radeon_device *rdev)
 961 {
 962         int req_ps_idx = rdev->pm.requested_power_state_index;
 963         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 964         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 965         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 966
 967         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 968                 /* 0xff01 is a flag rather then an actual voltage */
 969                 if (voltage->voltage == 0xff01)
 970                         return;
 971                 if (voltage->voltage != rdev->pm.current_vddc) {
 972                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
 973                         rdev->pm.current_vddc = voltage->voltage;
 974                         DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
 975                 }
 976         }
 977 }
 978
 979 /*
 980  * GART
 981  */
 982 static int rv770_pcie_gart_enable(struct radeon_device *rdev)
 983 {
 984         u32 tmp;
 985         int r, i;
 986
 987         if (rdev->gart.robj == NULL) {
 988                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 989                 return -EINVAL;
 990         }
 991         r = radeon_gart_table_vram_pin(rdev);
 992         if (r)
 993                 return r;
 994         radeon_gart_restore(rdev);
 995         /* Setup L2 cache */
 996         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 997                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 998                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 999         WREG32(VM_L2_CNTL2, 0);
1000         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1001         /* Setup TLB control */
1002         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1003                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1004                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1005                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1006         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1007         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1008         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1009         if (rdev->family == CHIP_RV740)
1010                 WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
1011         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1012         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1013         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1014         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1015         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1016         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1017         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1018         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1019                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1020         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1021                         (u32)(rdev->dummy_page.addr >> 12));
1022         for (i = 1; i < 7; i++)
1023                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1024
1025         r600_pcie_gart_tlb_flush(rdev);
1026         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1027                  (unsigned)(rdev->mc.gtt_size >> 20),
1028                  (unsigned long long)rdev->gart.table_addr);
1029         rdev->gart.ready = true;
1030         return 0;
1031 }
1032
1033 static void rv770_pcie_gart_disable(struct radeon_device *rdev)
1034 {
1035         u32 tmp;
1036         int i;
1037
1038         /* Disable all tables */
1039         for (i = 0; i < 7; i++)
1040                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1041
1042         /* Setup L2 cache */
1043         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1044                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1045         WREG32(VM_L2_CNTL2, 0);
1046         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1047         /* Setup TLB control */
1048         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1049         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1050         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1051         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1052         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1053         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1054         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1055         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1056         radeon_gart_table_vram_unpin(rdev);
1057 }
1058
1059 static void rv770_pcie_gart_fini(struct radeon_device *rdev)
1060 {
1061         radeon_gart_fini(rdev);
1062         rv770_pcie_gart_disable(rdev);
1063         radeon_gart_table_vram_free(rdev);
1064 }
1065
1066
1067 static void rv770_agp_enable(struct radeon_device *rdev)
1068 {
1069         u32 tmp;
1070         int i;
1071
1072         /* Setup L2 cache */
1073         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1074                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1075                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1076         WREG32(VM_L2_CNTL2, 0);
1077         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1078         /* Setup TLB control */
1079         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1080                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1081                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1082                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1083         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1084         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1085         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1086         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1087         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1088         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1089         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1090         for (i = 0; i < 7; i++)
1091                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1092 }
1093
1094 static void rv770_mc_program(struct radeon_device *rdev)
1095 {
1096         struct rv515_mc_save save;
1097         u32 tmp;
1098         int i, j;
1099
1100         /* Initialize HDP */
1101         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1102                 WREG32((0x2c14 + j), 0x00000000);
1103                 WREG32((0x2c18 + j), 0x00000000);
1104                 WREG32((0x2c1c + j), 0x00000000);
1105                 WREG32((0x2c20 + j), 0x00000000);
1106                 WREG32((0x2c24 + j), 0x00000000);
1107         }
1108         /* r7xx hw bug.  Read from HDP_DEBUG1 rather
1109          * than writing to HDP_REG_COHERENCY_FLUSH_CNTL
1110          */
1111         tmp = RREG32(HDP_DEBUG1);
1112
1113         rv515_mc_stop(rdev, &save);
1114         if (r600_mc_wait_for_idle(rdev)) {
1115                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1116         }
1117         /* Lockout access through VGA aperture*/
1118         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1119         /* Update configuration */
1120         if (rdev->flags & RADEON_IS_AGP) {
1121                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1122                         /* VRAM before AGP */
1123                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1124                                 rdev->mc.vram_start >> 12);
1125                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1126                                 rdev->mc.gtt_end >> 12);
1127                 } else {
1128                         /* VRAM after AGP */
1129                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1130                                 rdev->mc.gtt_start >> 12);
1131                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1132                                 rdev->mc.vram_end >> 12);
1133                 }
1134         } else {
1135                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1136                         rdev->mc.vram_start >> 12);
1137                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1138                         rdev->mc.vram_end >> 12);
1139         }
1140         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1141         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1142         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1143         WREG32(MC_VM_FB_LOCATION, tmp);
1144         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1145         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1146         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1147         if (rdev->flags & RADEON_IS_AGP) {
1148                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1149                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1150                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1151         } else {
1152                 WREG32(MC_VM_AGP_BASE, 0);
1153                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1154                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1155         }
1156         if (r600_mc_wait_for_idle(rdev)) {
1157                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1158         }
1159         rv515_mc_resume(rdev, &save);
1160         /* we need to own VRAM, so turn off the VGA renderer here
1161          * to stop it overwriting our objects */
1162         rv515_vga_render_disable(rdev);
1163 }
1164
1165
1166 /*
1167  * CP.
1168  */
1169 void r700_cp_stop(struct radeon_device *rdev)
1170 {
1171         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
1172         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
1173         WREG32(SCRATCH_UMSK, 0);
1174         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1175 }
1176
1177 static int rv770_cp_load_microcode(struct radeon_device *rdev)
1178 {
1179         const __be32 *fw_data;
1180         int i;
1181
1182         if (!rdev->me_fw || !rdev->pfp_fw)
1183                 return -EINVAL;
1184
1185         r700_cp_stop(rdev);
1186         WREG32(CP_RB_CNTL,
1187 #ifdef __BIG_ENDIAN
1188                BUF_SWAP_32BIT |
1189 #endif
1190                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1191
1192         /* Reset cp */
1193         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1194         RREG32(GRBM_SOFT_RESET);
1195         mdelay(15);
1196         WREG32(GRBM_SOFT_RESET, 0);
1197
1198         fw_data = (const __be32 *)rdev->pfp_fw->data;
1199         WREG32(CP_PFP_UCODE_ADDR, 0);
1200         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
1201                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1202         WREG32(CP_PFP_UCODE_ADDR, 0);
1203
1204         fw_data = (const __be32 *)rdev->me_fw->data;
1205         WREG32(CP_ME_RAM_WADDR, 0);
1206         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
1207                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1208
1209         WREG32(CP_PFP_UCODE_ADDR, 0);
1210         WREG32(CP_ME_RAM_WADDR, 0);
1211         WREG32(CP_ME_RAM_RADDR, 0);
1212         return 0;
1213 }
1214
1215 void r700_cp_fini(struct radeon_device *rdev)
1216 {
1217         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1218         r700_cp_stop(rdev);
1219         radeon_ring_fini(rdev, ring);
1220         radeon_scratch_free(rdev, ring->rptr_save_reg);
1221 }
1222
1223 /*
1224  * Core functions
1225  */
1226 static void rv770_gpu_init(struct radeon_device *rdev)
1227 {
1228         int i, j, num_qd_pipes;
1229         u32 ta_aux_cntl;
1230         u32 sx_debug_1;
1231         u32 smx_dc_ctl0;
1232         u32 db_debug3;
1233         u32 num_gs_verts_per_thread;
1234         u32 vgt_gs_per_es;
1235         u32 gs_prim_buffer_depth = 0;
1236         u32 sq_ms_fifo_sizes;
1237         u32 sq_config;
1238         u32 sq_thread_resource_mgmt;
1239         u32 hdp_host_path_cntl;
1240         u32 sq_dyn_gpr_size_simd_ab_0;
1241         u32 gb_tiling_config = 0;
1242         u32 cc_rb_backend_disable = 0;
1243         u32 cc_gc_shader_pipe_config = 0;
1244         u32 mc_arb_ramcfg;
1245         u32 db_debug4, tmp;
1246         u32 inactive_pipes, shader_pipe_config;
1247         u32 disabled_rb_mask;
1248         unsigned active_number;
1249
1250         /* setup chip specs */
1251         rdev->config.rv770.tiling_group_size = 256;
1252         switch (rdev->family) {
1253         case CHIP_RV770:
1254                 rdev->config.rv770.max_pipes = 4;
1255                 rdev->config.rv770.max_tile_pipes = 8;
1256                 rdev->config.rv770.max_simds = 10;
1257                 rdev->config.rv770.max_backends = 4;
1258                 rdev->config.rv770.max_gprs = 256;
1259                 rdev->config.rv770.max_threads = 248;
1260                 rdev->config.rv770.max_stack_entries = 512;
1261                 rdev->config.rv770.max_hw_contexts = 8;
1262                 rdev->config.rv770.max_gs_threads = 16 * 2;
1263                 rdev->config.rv770.sx_max_export_size = 128;
1264                 rdev->config.rv770.sx_max_export_pos_size = 16;
1265                 rdev->config.rv770.sx_max_export_smx_size = 112;
1266                 rdev->config.rv770.sq_num_cf_insts = 2;
1267
1268                 rdev->config.rv770.sx_num_of_sets = 7;
1269                 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
1270                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1271                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1272                 break;
1273         case CHIP_RV730:
1274                 rdev->config.rv770.max_pipes = 2;
1275                 rdev->config.rv770.max_tile_pipes = 4;
1276                 rdev->config.rv770.max_simds = 8;
1277                 rdev->config.rv770.max_backends = 2;
1278                 rdev->config.rv770.max_gprs = 128;
1279                 rdev->config.rv770.max_threads = 248;
1280                 rdev->config.rv770.max_stack_entries = 256;
1281                 rdev->config.rv770.max_hw_contexts = 8;
1282                 rdev->config.rv770.max_gs_threads = 16 * 2;
1283                 rdev->config.rv770.sx_max_export_size = 256;
1284                 rdev->config.rv770.sx_max_export_pos_size = 32;
1285                 rdev->config.rv770.sx_max_export_smx_size = 224;
1286                 rdev->config.rv770.sq_num_cf_insts = 2;
1287
1288                 rdev->config.rv770.sx_num_of_sets = 7;
1289                 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
1290                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1291                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1292                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
1293                         rdev->config.rv770.sx_max_export_pos_size -= 16;
1294                         rdev->config.rv770.sx_max_export_smx_size += 16;
1295                 }
1296                 break;
1297         case CHIP_RV710:
1298                 rdev->config.rv770.max_pipes = 2;
1299                 rdev->config.rv770.max_tile_pipes = 2;
1300                 rdev->config.rv770.max_simds = 2;
1301                 rdev->config.rv770.max_backends = 1;
1302                 rdev->config.rv770.max_gprs = 256;
1303                 rdev->config.rv770.max_threads = 192;
1304                 rdev->config.rv770.max_stack_entries = 256;
1305                 rdev->config.rv770.max_hw_contexts = 4;
1306                 rdev->config.rv770.max_gs_threads = 8 * 2;
1307                 rdev->config.rv770.sx_max_export_size = 128;
1308                 rdev->config.rv770.sx_max_export_pos_size = 16;
1309                 rdev->config.rv770.sx_max_export_smx_size = 112;
1310                 rdev->config.rv770.sq_num_cf_insts = 1;
1311
1312                 rdev->config.rv770.sx_num_of_sets = 7;
1313                 rdev->config.rv770.sc_prim_fifo_size = 0x40;
1314                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1315                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1316                 break;
1317         case CHIP_RV740:
1318                 rdev->config.rv770.max_pipes = 4;
1319                 rdev->config.rv770.max_tile_pipes = 4;
1320                 rdev->config.rv770.max_simds = 8;
1321                 rdev->config.rv770.max_backends = 4;
1322                 rdev->config.rv770.max_gprs = 256;
1323                 rdev->config.rv770.max_threads = 248;
1324                 rdev->config.rv770.max_stack_entries = 512;
1325                 rdev->config.rv770.max_hw_contexts = 8;
1326                 rdev->config.rv770.max_gs_threads = 16 * 2;
1327                 rdev->config.rv770.sx_max_export_size = 256;
1328                 rdev->config.rv770.sx_max_export_pos_size = 32;
1329                 rdev->config.rv770.sx_max_export_smx_size = 224;
1330                 rdev->config.rv770.sq_num_cf_insts = 2;
1331
1332                 rdev->config.rv770.sx_num_of_sets = 7;
1333                 rdev->config.rv770.sc_prim_fifo_size = 0x100;
1334                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
1335                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
1336
1337                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
1338                         rdev->config.rv770.sx_max_export_pos_size -= 16;
1339                         rdev->config.rv770.sx_max_export_smx_size += 16;
1340                 }
1341                 break;
1342         default:
1343                 break;
1344         }
1345
1346         /* Initialize HDP */
1347         j = 0;
1348         for (i = 0; i < 32; i++) {
1349                 WREG32((0x2c14 + j), 0x00000000);
1350                 WREG32((0x2c18 + j), 0x00000000);
1351                 WREG32((0x2c1c + j), 0x00000000);
1352                 WREG32((0x2c20 + j), 0x00000000);
1353                 WREG32((0x2c24 + j), 0x00000000);
1354                 j += 0x18;
1355         }
1356
1357         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1358
1359         /* setup tiling, simd, pipe config */
1360         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1361
1362         shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG);
1363         inactive_pipes = (shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> INACTIVE_QD_PIPES_SHIFT;
1364         for (i = 0, tmp = 1, active_number = 0; i < R7XX_MAX_PIPES; i++) {
1365                 if (!(inactive_pipes & tmp)) {
1366                         active_number++;
1367                 }
1368                 tmp <<= 1;
1369         }
1370         if (active_number == 1) {
1371                 WREG32(SPI_CONFIG_CNTL, DISABLE_INTERP_1);
1372         } else {
1373                 WREG32(SPI_CONFIG_CNTL, 0);
1374         }
1375
1376         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1377         tmp = R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_rb_backend_disable >> 16);
1378         if (tmp < rdev->config.rv770.max_backends) {
1379                 rdev->config.rv770.max_backends = tmp;
1380         }
1381
1382         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1383         tmp = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 8) & R7XX_MAX_PIPES_MASK);
1384         if (tmp < rdev->config.rv770.max_pipes) {
1385                 rdev->config.rv770.max_pipes = tmp;
1386         }
1387         tmp = R7XX_MAX_SIMDS - r600_count_pipe_bits((cc_gc_shader_pipe_config >> 16) & R7XX_MAX_SIMDS_MASK);
1388         if (tmp < rdev->config.rv770.max_simds) {
1389                 rdev->config.rv770.max_simds = tmp;
1390         }
1391
1392         switch (rdev->config.rv770.max_tile_pipes) {
1393         case 1:
1394         default:
1395                 gb_tiling_config = PIPE_TILING(0);
1396                 break;
1397         case 2:
1398                 gb_tiling_config = PIPE_TILING(1);
1399                 break;
1400         case 4:
1401                 gb_tiling_config = PIPE_TILING(2);
1402                 break;
1403         case 8:
1404                 gb_tiling_config = PIPE_TILING(3);
1405                 break;
1406         }
1407         rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes;
1408
1409         disabled_rb_mask = (RREG32(CC_RB_BACKEND_DISABLE) >> 16) & R7XX_MAX_BACKENDS_MASK;
1410         tmp = (gb_tiling_config & PIPE_TILING__MASK) >> PIPE_TILING__SHIFT;
1411         tmp = r6xx_remap_render_backend(rdev, tmp, rdev->config.rv770.max_backends,
1412                                         R7XX_MAX_BACKENDS, disabled_rb_mask);
1413         gb_tiling_config |= tmp << 16;
1414         rdev->config.rv770.backend_map = tmp;
1415
1416         if (rdev->family == CHIP_RV770)
1417                 gb_tiling_config |= BANK_TILING(1);
1418         else {
1419                 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1420                         gb_tiling_config |= BANK_TILING(1);
1421                 else
1422                         gb_tiling_config |= BANK_TILING(0);
1423         }
1424         rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
1425         gb_tiling_config |= GROUP_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1426         if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
1427                 gb_tiling_config |= ROW_TILING(3);
1428                 gb_tiling_config |= SAMPLE_SPLIT(3);
1429         } else {
1430                 gb_tiling_config |=
1431                         ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
1432                 gb_tiling_config |=
1433                         SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
1434         }
1435
1436         gb_tiling_config |= BANK_SWAPS(1);
1437         rdev->config.rv770.tile_config = gb_tiling_config;
1438
1439         WREG32(GB_TILING_CONFIG, gb_tiling_config);
1440         WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1441         WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1442         WREG32(DMA_TILING_CONFIG, (gb_tiling_config & 0xffff));
1443         WREG32(DMA_TILING_CONFIG2, (gb_tiling_config & 0xffff));
1444         if (rdev->family == CHIP_RV730) {
1445                 WREG32(UVD_UDEC_DB_TILING_CONFIG, (gb_tiling_config & 0xffff));
1446                 WREG32(UVD_UDEC_DBW_TILING_CONFIG, (gb_tiling_config & 0xffff));
1447                 WREG32(UVD_UDEC_TILING_CONFIG, (gb_tiling_config & 0xffff));
1448         }
1449
1450         WREG32(CGTS_SYS_TCC_DISABLE, 0);
1451         WREG32(CGTS_TCC_DISABLE, 0);
1452         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1453         WREG32(CGTS_USER_TCC_DISABLE, 0);
1454
1455
1456         num_qd_pipes = R7XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1457         WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
1458         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1459
1460         /* set HW defaults for 3D engine */
1461         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1462                                      ROQ_IB2_START(0x2b)));
1463
1464         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1465
1466         ta_aux_cntl = RREG32(TA_CNTL_AUX);
1467         WREG32(TA_CNTL_AUX, ta_aux_cntl | DISABLE_CUBE_ANISO);
1468
1469         sx_debug_1 = RREG32(SX_DEBUG_1);
1470         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1471         WREG32(SX_DEBUG_1, sx_debug_1);
1472
1473         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1474         smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
1475         smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
1476         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1477
1478         if (rdev->family != CHIP_RV740)
1479                 WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
1480                                        GS_FLUSH_CTL(4) |
1481                                        ACK_FLUSH_CTL(3) |
1482                                        SYNC_FLUSH_CTL));
1483
1484         if (rdev->family != CHIP_RV770)
1485                 WREG32(SMX_SAR_CTL0, 0x00003f3f);
1486
1487         db_debug3 = RREG32(DB_DEBUG3);
1488         db_debug3 &= ~DB_CLK_OFF_DELAY(0x1f);
1489         switch (rdev->family) {
1490         case CHIP_RV770:
1491         case CHIP_RV740:
1492                 db_debug3 |= DB_CLK_OFF_DELAY(0x1f);
1493                 break;
1494         case CHIP_RV710:
1495         case CHIP_RV730:
1496         default:
1497                 db_debug3 |= DB_CLK_OFF_DELAY(2);
1498                 break;
1499         }
1500         WREG32(DB_DEBUG3, db_debug3);
1501
1502         if (rdev->family != CHIP_RV770) {
1503                 db_debug4 = RREG32(DB_DEBUG4);
1504                 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
1505                 WREG32(DB_DEBUG4, db_debug4);
1506         }
1507
1508         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
1509                                         POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
1510                                         SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
1511
1512         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
1513                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
1514                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
1515
1516         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1517
1518         WREG32(VGT_NUM_INSTANCES, 1);
1519
1520         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1521
1522         WREG32(CP_PERFMON_CNTL, 0);
1523
1524         sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
1525                             DONE_FIFO_HIWATER(0xe0) |
1526                             ALU_UPDATE_FIFO_HIWATER(0x8));
1527         switch (rdev->family) {
1528         case CHIP_RV770:
1529         case CHIP_RV730:
1530         case CHIP_RV710:
1531                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
1532                 break;
1533         case CHIP_RV740:
1534         default:
1535                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
1536                 break;
1537         }
1538         WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1539
1540         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1541          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1542          */
1543         sq_config = RREG32(SQ_CONFIG);
1544         sq_config &= ~(PS_PRIO(3) |
1545                        VS_PRIO(3) |
1546                        GS_PRIO(3) |
1547                        ES_PRIO(3));
1548         sq_config |= (DX9_CONSTS |
1549                       VC_ENABLE |
1550                       EXPORT_SRC_C |
1551                       PS_PRIO(0) |
1552                       VS_PRIO(1) |
1553                       GS_PRIO(2) |
1554                       ES_PRIO(3));
1555         if (rdev->family == CHIP_RV710)
1556                 /* no vertex cache */
1557                 sq_config &= ~VC_ENABLE;
1558
1559         WREG32(SQ_CONFIG, sq_config);
1560
1561         WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
1562                                          NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
1563                                          NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
1564
1565         WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
1566                                          NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
1567
1568         sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
1569                                    NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
1570                                    NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
1571         if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
1572                 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
1573         else
1574                 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
1575         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1576
1577         WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
1578                                                      NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
1579
1580         WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
1581                                                      NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
1582
1583         sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
1584                                      SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
1585                                      SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
1586                                      SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
1587
1588         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1589         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1590         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1591         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1592         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1593         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1594         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1595         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1596
1597         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1598                                           FORCE_EOV_MAX_REZ_CNT(255)));
1599
1600         if (rdev->family == CHIP_RV710)
1601                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
1602                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
1603         else
1604                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
1605                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
1606
1607         switch (rdev->family) {
1608         case CHIP_RV770:
1609         case CHIP_RV730:
1610         case CHIP_RV740:
1611                 gs_prim_buffer_depth = 384;
1612                 break;
1613         case CHIP_RV710:
1614                 gs_prim_buffer_depth = 128;
1615                 break;
1616         default:
1617                 break;
1618         }
1619
1620         num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
1621         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1622         /* Max value for this is 256 */
1623         if (vgt_gs_per_es > 256)
1624                 vgt_gs_per_es = 256;
1625
1626         WREG32(VGT_ES_PER_GS, 128);
1627         WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
1628         WREG32(VGT_GS_PER_VS, 2);
1629
1630         /* more default values. 2D/3D driver should adjust as needed */
1631         WREG32(VGT_GS_VERTEX_REUSE, 16);
1632         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1633         WREG32(VGT_STRMOUT_EN, 0);
1634         WREG32(SX_MISC, 0);
1635         WREG32(PA_SC_MODE_CNTL, 0);
1636         WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
1637         WREG32(PA_SC_AA_CONFIG, 0);
1638         WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
1639         WREG32(PA_SC_LINE_STIPPLE, 0);
1640         WREG32(SPI_INPUT_Z, 0);
1641         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1642         WREG32(CB_COLOR7_FRAG, 0);
1643
1644         /* clear render buffer base addresses */
1645         WREG32(CB_COLOR0_BASE, 0);
1646         WREG32(CB_COLOR1_BASE, 0);
1647         WREG32(CB_COLOR2_BASE, 0);
1648         WREG32(CB_COLOR3_BASE, 0);
1649         WREG32(CB_COLOR4_BASE, 0);
1650         WREG32(CB_COLOR5_BASE, 0);
1651         WREG32(CB_COLOR6_BASE, 0);
1652         WREG32(CB_COLOR7_BASE, 0);
1653
1654         WREG32(TCP_CNTL, 0);
1655
1656         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1657         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1658
1659         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1660
1661         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1662                                           NUM_CLIP_SEQ(3)));
1663         WREG32(VC_ENHANCE, 0);
1664 }
1665
1666 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1667 {
1668         u64 size_bf, size_af;
1669
1670         if (mc->mc_vram_size > 0xE0000000) {
1671                 /* leave room for at least 512M GTT */
1672                 dev_warn(rdev->dev, "limiting VRAM\n");
1673                 mc->real_vram_size = 0xE0000000;
1674                 mc->mc_vram_size = 0xE0000000;
1675         }
1676         if (rdev->flags & RADEON_IS_AGP) {
1677                 size_bf = mc->gtt_start;
1678                 size_af = mc->mc_mask - mc->gtt_end;
1679                 if (size_bf > size_af) {
1680                         if (mc->mc_vram_size > size_bf) {
1681                                 dev_warn(rdev->dev, "limiting VRAM\n");
1682                                 mc->real_vram_size = size_bf;
1683                                 mc->mc_vram_size = size_bf;
1684                         }
1685                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1686                 } else {
1687                         if (mc->mc_vram_size > size_af) {
1688                                 dev_warn(rdev->dev, "limiting VRAM\n");
1689                                 mc->real_vram_size = size_af;
1690                                 mc->mc_vram_size = size_af;
1691                         }
1692                         mc->vram_start = mc->gtt_end + 1;
1693                 }
1694                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1695                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1696                                 mc->mc_vram_size >> 20, mc->vram_start,
1697                                 mc->vram_end, mc->real_vram_size >> 20);
1698         } else {
1699                 radeon_vram_location(rdev, &rdev->mc, 0);
1700                 rdev->mc.gtt_base_align = 0;
1701                 radeon_gtt_location(rdev, mc);
1702         }
1703 }
1704
1705 static int rv770_mc_init(struct radeon_device *rdev)
1706 {
1707         u32 tmp;
1708         int chansize, numchan;
1709
1710         /* Get VRAM informations */
1711         rdev->mc.vram_is_ddr = true;
1712         tmp = RREG32(MC_ARB_RAMCFG);
1713         if (tmp & CHANSIZE_OVERRIDE) {
1714                 chansize = 16;
1715         } else if (tmp & CHANSIZE_MASK) {
1716                 chansize = 64;
1717         } else {
1718                 chansize = 32;
1719         }
1720         tmp = RREG32(MC_SHARED_CHMAP);
1721         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1722         case 0:
1723         default:
1724                 numchan = 1;
1725                 break;
1726         case 1:
1727                 numchan = 2;
1728                 break;
1729         case 2:
1730                 numchan = 4;
1731                 break;
1732         case 3:
1733                 numchan = 8;
1734                 break;
1735         }
1736         rdev->mc.vram_width = numchan * chansize;
1737         /* Could aper size report 0 ? */
1738         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1739         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1740         /* Setup GPU memory space */
1741         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1742         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1743         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1744         r700_vram_gtt_location(rdev, &rdev->mc);
1745         radeon_update_bandwidth_info(rdev);
1746
1747         return 0;
1748 }
1749
1750 /**
1751  * rv770_copy_dma - copy pages using the DMA engine
1752  *
1753  * @rdev: radeon_device pointer
1754  * @src_offset: src GPU address
1755  * @dst_offset: dst GPU address
1756  * @num_gpu_pages: number of GPU pages to xfer
1757  * @fence: radeon fence object
1758  *
1759  * Copy GPU paging using the DMA engine (r7xx).
1760  * Used by the radeon ttm implementation to move pages if
1761  * registered as the asic copy callback.
1762  */
1763 int rv770_copy_dma(struct radeon_device *rdev,
1764                   uint64_t src_offset, uint64_t dst_offset,
1765                   unsigned num_gpu_pages,
1766                   struct radeon_fence **fence)
1767 {
1768         struct radeon_semaphore *sem = NULL;
1769         int ring_index = rdev->asic->copy.dma_ring_index;
1770         struct radeon_ring *ring = &rdev->ring[ring_index];
1771         u32 size_in_dw, cur_size_in_dw;
1772         int i, num_loops;
1773         int r = 0;
1774
1775         r = radeon_semaphore_create(rdev, &sem);
1776         if (r) {
1777                 DRM_ERROR("radeon: moving bo (%d).\n", r);
1778                 return r;
1779         }
1780
1781         size_in_dw = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT) / 4;
1782         num_loops = DIV_ROUND_UP(size_in_dw, 0xFFFF);
1783         r = radeon_ring_lock(rdev, ring, num_loops * 5 + 8);
1784         if (r) {
1785                 DRM_ERROR("radeon: moving bo (%d).\n", r);
1786                 radeon_semaphore_free(rdev, &sem, NULL);
1787                 return r;
1788         }
1789
1790         if (radeon_fence_need_sync(*fence, ring->idx)) {
1791                 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
1792                                             ring->idx);
1793                 radeon_fence_note_sync(*fence, ring->idx);
1794         } else {
1795                 radeon_semaphore_free(rdev, &sem, NULL);
1796         }
1797
1798         for (i = 0; i < num_loops; i++) {
1799                 cur_size_in_dw = size_in_dw;
1800                 if (cur_size_in_dw > 0xFFFF)
1801                         cur_size_in_dw = 0xFFFF;
1802                 size_in_dw -= cur_size_in_dw;
1803                 radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_COPY, 0, 0, cur_size_in_dw));
1804                 radeon_ring_write(ring, dst_offset & 0xfffffffc);
1805                 radeon_ring_write(ring, src_offset & 0xfffffffc);
1806                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff);
1807                 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff);
1808                 src_offset += cur_size_in_dw * 4;
1809                 dst_offset += cur_size_in_dw * 4;
1810         }
1811
1812         r = radeon_fence_emit(rdev, fence, ring->idx);
1813         if (r) {
1814                 radeon_ring_unlock_undo(rdev, ring);
1815                 return r;
1816         }
1817
1818         radeon_ring_unlock_commit(rdev, ring);
1819         radeon_semaphore_free(rdev, &sem, *fence);
1820
1821         return r;
1822 }
1823
1824 static int rv770_startup(struct radeon_device *rdev)
1825 {
1826         struct radeon_ring *ring;
1827         int r;
1828
1829         /* enable pcie gen2 link */
1830         rv770_pcie_gen2_enable(rdev);
1831
1832         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1833                 r = r600_init_microcode(rdev);
1834                 if (r) {
1835                         DRM_ERROR("Failed to load firmware!\n");
1836                         return r;
1837                 }
1838         }
1839
1840         r = r600_vram_scratch_init(rdev);
1841         if (r)
1842                 return r;
1843
1844         rv770_mc_program(rdev);
1845         if (rdev->flags & RADEON_IS_AGP) {
1846                 rv770_agp_enable(rdev);
1847         } else {
1848                 r = rv770_pcie_gart_enable(rdev);
1849                 if (r)
1850                         return r;
1851         }
1852
1853         rv770_gpu_init(rdev);
1854         r = r600_blit_init(rdev);
1855         if (r) {
1856                 r600_blit_fini(rdev);
1857                 rdev->asic->copy.copy = NULL;
1858                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1859         }
1860
1861         /* allocate wb buffer */
1862         r = radeon_wb_init(rdev);
1863         if (r)
1864                 return r;
1865
1866         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
1867         if (r) {
1868                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
1869                 return r;
1870         }
1871
1872         r = radeon_fence_driver_start_ring(rdev, R600_RING_TYPE_DMA_INDEX);
1873         if (r) {
1874                 dev_err(rdev->dev, "failed initializing DMA fences (%d).\n", r);
1875                 return r;
1876         }
1877
1878         r = rv770_uvd_resume(rdev);
1879         if (!r) {
1880                 r = radeon_fence_driver_start_ring(rdev,
1881                                                    R600_RING_TYPE_UVD_INDEX);
1882                 if (r)
1883                         dev_err(rdev->dev, "UVD fences init error (%d).\n", r);
1884         }
1885
1886         if (r)
1887                 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
1888
1889         /* Enable IRQ */
1890         if (!rdev->irq.installed) {
1891                 r = radeon_irq_kms_init(rdev);
1892                 if (r)
1893                         return r;
1894         }
1895
1896         r = r600_irq_init(rdev);
1897         if (r) {
1898                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1899                 radeon_irq_kms_fini(rdev);
1900                 return r;
1901         }
1902         r600_irq_set(rdev);
1903
1904         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1905         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
1906                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
1907                              0, 0xfffff, RADEON_CP_PACKET2);
1908         if (r)
1909                 return r;
1910
1911         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
1912         r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
1913                              DMA_RB_RPTR, DMA_RB_WPTR,
1914                              2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
1915         if (r)
1916                 return r;
1917
1918         r = rv770_cp_load_microcode(rdev);
1919         if (r)
1920                 return r;
1921         r = r600_cp_resume(rdev);
1922         if (r)
1923                 return r;
1924
1925         r = r600_dma_resume(rdev);
1926         if (r)
1927                 return r;
1928
1929         ring = &rdev->ring[R600_RING_TYPE_UVD_INDEX];
1930         if (ring->ring_size) {
1931                 r = radeon_ring_init(rdev, ring, ring->ring_size,
1932                                      R600_WB_UVD_RPTR_OFFSET,
1933                                      UVD_RBC_RB_RPTR, UVD_RBC_RB_WPTR,
1934                                      0, 0xfffff, RADEON_CP_PACKET2);
1935                 if (!r)
1936                         r = r600_uvd_init(rdev);
1937
1938                 if (r)
1939                         DRM_ERROR("radeon: failed initializing UVD (%d).\n", r);
1940         }
1941
1942         r = radeon_ib_pool_init(rdev);
1943         if (r) {
1944                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1945                 return r;
1946         }
1947
1948         r = r600_audio_init(rdev);
1949         if (r) {
1950                 DRM_ERROR("radeon: audio init failed\n");
1951                 return r;
1952         }
1953
1954         return 0;
1955 }
1956
1957 int rv770_resume(struct radeon_device *rdev)
1958 {
1959         int r;
1960
1961         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
1962          * posting will perform necessary task to bring back GPU into good
1963          * shape.
1964          */
1965         /* post card */
1966         atom_asic_init(rdev->mode_info.atom_context);
1967
1968         /* init golden registers */
1969         rv770_init_golden_registers(rdev);
1970
1971         rdev->accel_working = true;
1972         r = rv770_startup(rdev);
1973         if (r) {
1974                 DRM_ERROR("r600 startup failed on resume\n");
1975                 rdev->accel_working = false;
1976                 return r;
1977         }
1978
1979         return r;
1980
1981 }
1982
1983 int rv770_suspend(struct radeon_device *rdev)
1984 {
1985         r600_audio_fini(rdev);
1986         r600_uvd_stop(rdev);
1987         radeon_uvd_suspend(rdev);
1988         r700_cp_stop(rdev);
1989         r600_dma_stop(rdev);
1990         r600_irq_suspend(rdev);
1991         radeon_wb_disable(rdev);
1992         rv770_pcie_gart_disable(rdev);
1993
1994         return 0;
1995 }
1996
1997 /* Plan is to move initialization in that function and use
1998  * helper function so that radeon_device_init pretty much
1999  * do nothing more than calling asic specific function. This
2000  * should also allow to remove a bunch of callback function
2001  * like vram_info.
2002  */
2003 int rv770_init(struct radeon_device *rdev)
2004 {
2005         int r;
2006
2007         /* Read BIOS */
2008         if (!radeon_get_bios(rdev)) {
2009                 if (ASIC_IS_AVIVO(rdev))
2010                         return -EINVAL;
2011         }
2012         /* Must be an ATOMBIOS */
2013         if (!rdev->is_atom_bios) {
2014                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2015                 return -EINVAL;
2016         }
2017         r = radeon_atombios_init(rdev);
2018         if (r)
2019                 return r;
2020         /* Post card if necessary */
2021         if (!radeon_card_posted(rdev)) {
2022                 if (!rdev->bios) {
2023                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2024                         return -EINVAL;
2025                 }
2026                 DRM_INFO("GPU not posted. posting now...\n");
2027                 atom_asic_init(rdev->mode_info.atom_context);
2028         }
2029         /* init golden registers */
2030         rv770_init_golden_registers(rdev);
2031         /* Initialize scratch registers */
2032         r600_scratch_init(rdev);
2033         /* Initialize surface registers */
2034         radeon_surface_init(rdev);
2035         /* Initialize clocks */
2036         radeon_get_clock_info(rdev->ddev);
2037         /* Fence driver */
2038         r = radeon_fence_driver_init(rdev);
2039         if (r)
2040                 return r;
2041         /* initialize AGP */
2042         if (rdev->flags & RADEON_IS_AGP) {
2043                 r = radeon_agp_init(rdev);
2044                 if (r)
2045                         radeon_agp_disable(rdev);
2046         }
2047         r = rv770_mc_init(rdev);
2048         if (r)
2049                 return r;
2050         /* Memory manager */
2051         r = radeon_bo_init(rdev);
2052         if (r)
2053                 return r;
2054
2055         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
2056         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
2057
2058         rdev->ring[R600_RING_TYPE_DMA_INDEX].ring_obj = NULL;
2059         r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX], 64 * 1024);
2060
2061         r = radeon_uvd_init(rdev);
2062         if (!r) {
2063                 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_obj = NULL;
2064                 r600_ring_init(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX],
2065                                4096);
2066         }
2067
2068         rdev->ih.ring_obj = NULL;
2069         r600_ih_ring_init(rdev, 64 * 1024);
2070
2071         r = r600_pcie_gart_init(rdev);
2072         if (r)
2073                 return r;
2074
2075         rdev->accel_working = true;
2076         r = rv770_startup(rdev);
2077         if (r) {
2078                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2079                 r700_cp_fini(rdev);
2080                 r600_dma_fini(rdev);
2081                 r600_irq_fini(rdev);
2082                 radeon_wb_fini(rdev);
2083                 radeon_ib_pool_fini(rdev);
2084                 radeon_irq_kms_fini(rdev);
2085                 rv770_pcie_gart_fini(rdev);
2086                 rdev->accel_working = false;
2087         }
2088
2089         return 0;
2090 }
2091
2092 void rv770_fini(struct radeon_device *rdev)
2093 {
2094         r600_blit_fini(rdev);
2095         r700_cp_fini(rdev);
2096         r600_dma_fini(rdev);
2097         r600_irq_fini(rdev);
2098         radeon_wb_fini(rdev);
2099         radeon_ib_pool_fini(rdev);
2100         radeon_irq_kms_fini(rdev);
2101         rv770_pcie_gart_fini(rdev);
2102         r600_uvd_stop(rdev);
2103         radeon_uvd_fini(rdev);
2104         r600_vram_scratch_fini(rdev);
2105         radeon_gem_fini(rdev);
2106         radeon_fence_driver_fini(rdev);
2107         radeon_agp_fini(rdev);
2108         radeon_bo_fini(rdev);
2109         radeon_atombios_fini(rdev);
2110         kfree(rdev->bios);
2111         rdev->bios = NULL;
2112 }
2113
2114 static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
2115 {
2116         u32 link_width_cntl, lanes, speed_cntl, tmp;
2117         u16 link_cntl2;
2118
2119         if (radeon_pcie_gen2 == 0)
2120                 return;
2121
2122         if (rdev->flags & RADEON_IS_IGP)
2123                 return;
2124
2125         if (!(rdev->flags & RADEON_IS_PCIE))
2126                 return;
2127
2128         /* x2 cards have a special sequence */
2129         if (ASIC_IS_X2(rdev))
2130                 return;
2131
2132         if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
2133                 (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
2134                 return;
2135
2136         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
2137
2138         /* advertise upconfig capability */
2139         link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2140         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
2141         WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2142         link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2143         if (link_width_cntl & LC_RENEGOTIATION_SUPPORT) {
2144                 lanes = (link_width_cntl & LC_LINK_WIDTH_RD_MASK) >> LC_LINK_WIDTH_RD_SHIFT;
2145                 link_width_cntl &= ~(LC_LINK_WIDTH_MASK |
2146                                      LC_RECONFIG_ARC_MISSING_ESCAPE);
2147                 link_width_cntl |= lanes | LC_RECONFIG_NOW |
2148                         LC_RENEGOTIATE_EN | LC_UPCONFIGURE_SUPPORT;
2149                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2150         } else {
2151                 link_width_cntl |= LC_UPCONFIGURE_DIS;
2152                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2153         }
2154
2155         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2156         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) &&
2157             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
2158
2159                 tmp = RREG32(0x541c);
2160                 WREG32(0x541c, tmp | 0x8);
2161                 WREG32(MM_CFGREGS_CNTL, MM_WR_TO_CFG_EN);
2162                 link_cntl2 = RREG16(0x4088);
2163                 link_cntl2 &= ~TARGET_LINK_SPEED_MASK;
2164                 link_cntl2 |= 0x2;
2165                 WREG16(0x4088, link_cntl2);
2166                 WREG32(MM_CFGREGS_CNTL, 0);
2167
2168                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2169                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
2170                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2171
2172                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2173                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
2174                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2175
2176                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2177                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
2178                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2179
2180                 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
2181                 speed_cntl |= LC_GEN2_EN_STRAP;
2182                 WREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL, speed_cntl);
2183
2184         } else {
2185                 link_width_cntl = RREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL);
2186                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
2187                 if (1)
2188                         link_width_cntl |= LC_UPCONFIGURE_DIS;
2189                 else
2190                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
2191                 WREG32_PCIE_PORT(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
2192         }
2193 }