drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         int     min, max;
  50 } intel_range_t;
  51
  52 typedef struct {
  53         int     dot_limit;
  54         int     p2_slow, p2_fast;
  55 } intel_p2_t;
  56
  57 #define INTEL_P2_NUM                  2
  58 typedef struct intel_limit intel_limit_t;
  59 struct intel_limit {
  60         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  61         intel_p2_t          p2;
  62         /**
  63          * find_pll() - Find the best values for the PLL
  64          * @limit: limits for the PLL
  65          * @crtc: current CRTC
  66          * @target: target frequency in kHz
  67          * @refclk: reference clock frequency in kHz
  68          * @match_clock: if provided, @best_clock P divider must
  69          *               match the P divider from @match_clock
  70          *               used for LVDS downclocking
  71          * @best_clock: best PLL values found
  72          *
  73          * Returns true on success, false on failure.
  74          */
  75         bool (*find_pll)(const intel_limit_t *limit,
  76                          struct drm_crtc *crtc,
  77                          int target, int refclk,
  78                          intel_clock_t *match_clock,
  79                          intel_clock_t *best_clock);
  80 };
  81
  82 /* FDI */
  83 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  84
  85 int
  86 intel_pch_rawclk(struct drm_device *dev)
  87 {
  88         struct drm_i915_private *dev_priv = dev->dev_private;
  89
  90         WARN_ON(!HAS_PCH_SPLIT(dev));
  91
  92         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  93 }
  94
  95 static bool
  96 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  97                     int target, int refclk, intel_clock_t *match_clock,
  98                     intel_clock_t *best_clock);
  99 static bool
 100 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 101                         int target, int refclk, intel_clock_t *match_clock,
 102                         intel_clock_t *best_clock);
 103
 104 static bool
 105 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 106                         int target, int refclk, intel_clock_t *match_clock,
 107                         intel_clock_t *best_clock);
 108
 109 static inline u32 /* units of 100MHz */
 110 intel_fdi_link_freq(struct drm_device *dev)
 111 {
 112         if (IS_GEN5(dev)) {
 113                 struct drm_i915_private *dev_priv = dev->dev_private;
 114                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 115         } else
 116                 return 27;
 117 }
 118
 119 static const intel_limit_t intel_limits_i8xx_dvo = {
 120         .dot = { .min = 25000, .max = 350000 },
 121         .vco = { .min = 930000, .max = 1400000 },
 122         .n = { .min = 3, .max = 16 },
 123         .m = { .min = 96, .max = 140 },
 124         .m1 = { .min = 18, .max = 26 },
 125         .m2 = { .min = 6, .max = 16 },
 126         .p = { .min = 4, .max = 128 },
 127         .p1 = { .min = 2, .max = 33 },
 128         .p2 = { .dot_limit = 165000,
 129                 .p2_slow = 4, .p2_fast = 2 },
 130         .find_pll = intel_find_best_PLL,
 131 };
 132
 133 static const intel_limit_t intel_limits_i8xx_lvds = {
 134         .dot = { .min = 25000, .max = 350000 },
 135         .vco = { .min = 930000, .max = 1400000 },
 136         .n = { .min = 3, .max = 16 },
 137         .m = { .min = 96, .max = 140 },
 138         .m1 = { .min = 18, .max = 26 },
 139         .m2 = { .min = 6, .max = 16 },
 140         .p = { .min = 4, .max = 128 },
 141         .p1 = { .min = 1, .max = 6 },
 142         .p2 = { .dot_limit = 165000,
 143                 .p2_slow = 14, .p2_fast = 7 },
 144         .find_pll = intel_find_best_PLL,
 145 };
 146
 147 static const intel_limit_t intel_limits_i9xx_sdvo = {
 148         .dot = { .min = 20000, .max = 400000 },
 149         .vco = { .min = 1400000, .max = 2800000 },
 150         .n = { .min = 1, .max = 6 },
 151         .m = { .min = 70, .max = 120 },
 152         .m1 = { .min = 8, .max = 18 },
 153         .m2 = { .min = 3, .max = 7 },
 154         .p = { .min = 5, .max = 80 },
 155         .p1 = { .min = 1, .max = 8 },
 156         .p2 = { .dot_limit = 200000,
 157                 .p2_slow = 10, .p2_fast = 5 },
 158         .find_pll = intel_find_best_PLL,
 159 };
 160
 161 static const intel_limit_t intel_limits_i9xx_lvds = {
 162         .dot = { .min = 20000, .max = 400000 },
 163         .vco = { .min = 1400000, .max = 2800000 },
 164         .n = { .min = 1, .max = 6 },
 165         .m = { .min = 70, .max = 120 },
 166         .m1 = { .min = 8, .max = 18 },
 167         .m2 = { .min = 3, .max = 7 },
 168         .p = { .min = 7, .max = 98 },
 169         .p1 = { .min = 1, .max = 8 },
 170         .p2 = { .dot_limit = 112000,
 171                 .p2_slow = 14, .p2_fast = 7 },
 172         .find_pll = intel_find_best_PLL,
 173 };
 174
 175
 176 static const intel_limit_t intel_limits_g4x_sdvo = {
 177         .dot = { .min = 25000, .max = 270000 },
 178         .vco = { .min = 1750000, .max = 3500000},
 179         .n = { .min = 1, .max = 4 },
 180         .m = { .min = 104, .max = 138 },
 181         .m1 = { .min = 17, .max = 23 },
 182         .m2 = { .min = 5, .max = 11 },
 183         .p = { .min = 10, .max = 30 },
 184         .p1 = { .min = 1, .max = 3},
 185         .p2 = { .dot_limit = 270000,
 186                 .p2_slow = 10,
 187                 .p2_fast = 10
 188         },
 189         .find_pll = intel_g4x_find_best_PLL,
 190 };
 191
 192 static const intel_limit_t intel_limits_g4x_hdmi = {
 193         .dot = { .min = 22000, .max = 400000 },
 194         .vco = { .min = 1750000, .max = 3500000},
 195         .n = { .min = 1, .max = 4 },
 196         .m = { .min = 104, .max = 138 },
 197         .m1 = { .min = 16, .max = 23 },
 198         .m2 = { .min = 5, .max = 11 },
 199         .p = { .min = 5, .max = 80 },
 200         .p1 = { .min = 1, .max = 8},
 201         .p2 = { .dot_limit = 165000,
 202                 .p2_slow = 10, .p2_fast = 5 },
 203         .find_pll = intel_g4x_find_best_PLL,
 204 };
 205
 206 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 207         .dot = { .min = 20000, .max = 115000 },
 208         .vco = { .min = 1750000, .max = 3500000 },
 209         .n = { .min = 1, .max = 3 },
 210         .m = { .min = 104, .max = 138 },
 211         .m1 = { .min = 17, .max = 23 },
 212         .m2 = { .min = 5, .max = 11 },
 213         .p = { .min = 28, .max = 112 },
 214         .p1 = { .min = 2, .max = 8 },
 215         .p2 = { .dot_limit = 0,
 216                 .p2_slow = 14, .p2_fast = 14
 217         },
 218         .find_pll = intel_g4x_find_best_PLL,
 219 };
 220
 221 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 222         .dot = { .min = 80000, .max = 224000 },
 223         .vco = { .min = 1750000, .max = 3500000 },
 224         .n = { .min = 1, .max = 3 },
 225         .m = { .min = 104, .max = 138 },
 226         .m1 = { .min = 17, .max = 23 },
 227         .m2 = { .min = 5, .max = 11 },
 228         .p = { .min = 14, .max = 42 },
 229         .p1 = { .min = 2, .max = 6 },
 230         .p2 = { .dot_limit = 0,
 231                 .p2_slow = 7, .p2_fast = 7
 232         },
 233         .find_pll = intel_g4x_find_best_PLL,
 234 };
 235
 236 static const intel_limit_t intel_limits_pineview_sdvo = {
 237         .dot = { .min = 20000, .max = 400000},
 238         .vco = { .min = 1700000, .max = 3500000 },
 239         /* Pineview's Ncounter is a ring counter */
 240         .n = { .min = 3, .max = 6 },
 241         .m = { .min = 2, .max = 256 },
 242         /* Pineview only has one combined m divider, which we treat as m2. */
 243         .m1 = { .min = 0, .max = 0 },
 244         .m2 = { .min = 0, .max = 254 },
 245         .p = { .min = 5, .max = 80 },
 246         .p1 = { .min = 1, .max = 8 },
 247         .p2 = { .dot_limit = 200000,
 248                 .p2_slow = 10, .p2_fast = 5 },
 249         .find_pll = intel_find_best_PLL,
 250 };
 251
 252 static const intel_limit_t intel_limits_pineview_lvds = {
 253         .dot = { .min = 20000, .max = 400000 },
 254         .vco = { .min = 1700000, .max = 3500000 },
 255         .n = { .min = 3, .max = 6 },
 256         .m = { .min = 2, .max = 256 },
 257         .m1 = { .min = 0, .max = 0 },
 258         .m2 = { .min = 0, .max = 254 },
 259         .p = { .min = 7, .max = 112 },
 260         .p1 = { .min = 1, .max = 8 },
 261         .p2 = { .dot_limit = 112000,
 262                 .p2_slow = 14, .p2_fast = 14 },
 263         .find_pll = intel_find_best_PLL,
 264 };
 265
 266 /* Ironlake / Sandybridge
 267  *
 268  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 269  * the range value for them is (actual_value - 2).
 270  */
 271 static const intel_limit_t intel_limits_ironlake_dac = {
 272         .dot = { .min = 25000, .max = 350000 },
 273         .vco = { .min = 1760000, .max = 3510000 },
 274         .n = { .min = 1, .max = 5 },
 275         .m = { .min = 79, .max = 127 },
 276         .m1 = { .min = 12, .max = 22 },
 277         .m2 = { .min = 5, .max = 9 },
 278         .p = { .min = 5, .max = 80 },
 279         .p1 = { .min = 1, .max = 8 },
 280         .p2 = { .dot_limit = 225000,
 281                 .p2_slow = 10, .p2_fast = 5 },
 282         .find_pll = intel_g4x_find_best_PLL,
 283 };
 284
 285 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 286         .dot = { .min = 25000, .max = 350000 },
 287         .vco = { .min = 1760000, .max = 3510000 },
 288         .n = { .min = 1, .max = 3 },
 289         .m = { .min = 79, .max = 118 },
 290         .m1 = { .min = 12, .max = 22 },
 291         .m2 = { .min = 5, .max = 9 },
 292         .p = { .min = 28, .max = 112 },
 293         .p1 = { .min = 2, .max = 8 },
 294         .p2 = { .dot_limit = 225000,
 295                 .p2_slow = 14, .p2_fast = 14 },
 296         .find_pll = intel_g4x_find_best_PLL,
 297 };
 298
 299 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 300         .dot = { .min = 25000, .max = 350000 },
 301         .vco = { .min = 1760000, .max = 3510000 },
 302         .n = { .min = 1, .max = 3 },
 303         .m = { .min = 79, .max = 127 },
 304         .m1 = { .min = 12, .max = 22 },
 305         .m2 = { .min = 5, .max = 9 },
 306         .p = { .min = 14, .max = 56 },
 307         .p1 = { .min = 2, .max = 8 },
 308         .p2 = { .dot_limit = 225000,
 309                 .p2_slow = 7, .p2_fast = 7 },
 310         .find_pll = intel_g4x_find_best_PLL,
 311 };
 312
 313 /* LVDS 100mhz refclk limits. */
 314 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 315         .dot = { .min = 25000, .max = 350000 },
 316         .vco = { .min = 1760000, .max = 3510000 },
 317         .n = { .min = 1, .max = 2 },
 318         .m = { .min = 79, .max = 126 },
 319         .m1 = { .min = 12, .max = 22 },
 320         .m2 = { .min = 5, .max = 9 },
 321         .p = { .min = 28, .max = 112 },
 322         .p1 = { .min = 2, .max = 8 },
 323         .p2 = { .dot_limit = 225000,
 324                 .p2_slow = 14, .p2_fast = 14 },
 325         .find_pll = intel_g4x_find_best_PLL,
 326 };
 327
 328 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 329         .dot = { .min = 25000, .max = 350000 },
 330         .vco = { .min = 1760000, .max = 3510000 },
 331         .n = { .min = 1, .max = 3 },
 332         .m = { .min = 79, .max = 126 },
 333         .m1 = { .min = 12, .max = 22 },
 334         .m2 = { .min = 5, .max = 9 },
 335         .p = { .min = 14, .max = 42 },
 336         .p1 = { .min = 2, .max = 6 },
 337         .p2 = { .dot_limit = 225000,
 338                 .p2_slow = 7, .p2_fast = 7 },
 339         .find_pll = intel_g4x_find_best_PLL,
 340 };
 341
 342 static const intel_limit_t intel_limits_vlv_dac = {
 343         .dot = { .min = 25000, .max = 270000 },
 344         .vco = { .min = 4000000, .max = 6000000 },
 345         .n = { .min = 1, .max = 7 },
 346         .m = { .min = 22, .max = 450 }, /* guess */
 347         .m1 = { .min = 2, .max = 3 },
 348         .m2 = { .min = 11, .max = 156 },
 349         .p = { .min = 10, .max = 30 },
 350         .p1 = { .min = 1, .max = 3 },
 351         .p2 = { .dot_limit = 270000,
 352                 .p2_slow = 2, .p2_fast = 20 },
 353         .find_pll = intel_vlv_find_best_pll,
 354 };
 355
 356 static const intel_limit_t intel_limits_vlv_hdmi = {
 357         .dot = { .min = 25000, .max = 270000 },
 358         .vco = { .min = 4000000, .max = 6000000 },
 359         .n = { .min = 1, .max = 7 },
 360         .m = { .min = 60, .max = 300 }, /* guess */
 361         .m1 = { .min = 2, .max = 3 },
 362         .m2 = { .min = 11, .max = 156 },
 363         .p = { .min = 10, .max = 30 },
 364         .p1 = { .min = 2, .max = 3 },
 365         .p2 = { .dot_limit = 270000,
 366                 .p2_slow = 2, .p2_fast = 20 },
 367         .find_pll = intel_vlv_find_best_pll,
 368 };
 369
 370 static const intel_limit_t intel_limits_vlv_dp = {
 371         .dot = { .min = 25000, .max = 270000 },
 372         .vco = { .min = 4000000, .max = 6000000 },
 373         .n = { .min = 1, .max = 7 },
 374         .m = { .min = 22, .max = 450 },
 375         .m1 = { .min = 2, .max = 3 },
 376         .m2 = { .min = 11, .max = 156 },
 377         .p = { .min = 10, .max = 30 },
 378         .p1 = { .min = 1, .max = 3 },
 379         .p2 = { .dot_limit = 270000,
 380                 .p2_slow = 2, .p2_fast = 20 },
 381         .find_pll = intel_vlv_find_best_pll,
 382 };
 383
 384 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 385 {
 386         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 387
 388         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 389                 DRM_ERROR("DPIO idle wait timed out\n");
 390                 return 0;
 391         }
 392
 393         I915_WRITE(DPIO_REG, reg);
 394         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 395                    DPIO_BYTE);
 396         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 397                 DRM_ERROR("DPIO read wait timed out\n");
 398                 return 0;
 399         }
 400
 401         return I915_READ(DPIO_DATA);
 402 }
 403
 404 void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
 405 {
 406         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
 407
 408         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 409                 DRM_ERROR("DPIO idle wait timed out\n");
 410                 return;
 411         }
 412
 413         I915_WRITE(DPIO_DATA, val);
 414         I915_WRITE(DPIO_REG, reg);
 415         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 416                    DPIO_BYTE);
 417         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 418                 DRM_ERROR("DPIO write wait timed out\n");
 419 }
 420
 421 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 422                                                 int refclk)
 423 {
 424         struct drm_device *dev = crtc->dev;
 425         const intel_limit_t *limit;
 426
 427         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 428                 if (intel_is_dual_link_lvds(dev)) {
 429                         if (refclk == 100000)
 430                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 431                         else
 432                                 limit = &intel_limits_ironlake_dual_lvds;
 433                 } else {
 434                         if (refclk == 100000)
 435                                 limit = &intel_limits_ironlake_single_lvds_100m;
 436                         else
 437                                 limit = &intel_limits_ironlake_single_lvds;
 438                 }
 439         } else
 440                 limit = &intel_limits_ironlake_dac;
 441
 442         return limit;
 443 }
 444
 445 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 446 {
 447         struct drm_device *dev = crtc->dev;
 448         const intel_limit_t *limit;
 449
 450         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 451                 if (intel_is_dual_link_lvds(dev))
 452                         limit = &intel_limits_g4x_dual_channel_lvds;
 453                 else
 454                         limit = &intel_limits_g4x_single_channel_lvds;
 455         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 456                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 457                 limit = &intel_limits_g4x_hdmi;
 458         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 459                 limit = &intel_limits_g4x_sdvo;
 460         } else /* The option is for other outputs */
 461                 limit = &intel_limits_i9xx_sdvo;
 462
 463         return limit;
 464 }
 465
 466 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 467 {
 468         struct drm_device *dev = crtc->dev;
 469         const intel_limit_t *limit;
 470
 471         if (HAS_PCH_SPLIT(dev))
 472                 limit = intel_ironlake_limit(crtc, refclk);
 473         else if (IS_G4X(dev)) {
 474                 limit = intel_g4x_limit(crtc);
 475         } else if (IS_PINEVIEW(dev)) {
 476                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 477                         limit = &intel_limits_pineview_lvds;
 478                 else
 479                         limit = &intel_limits_pineview_sdvo;
 480         } else if (IS_VALLEYVIEW(dev)) {
 481                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 482                         limit = &intel_limits_vlv_dac;
 483                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 484                         limit = &intel_limits_vlv_hdmi;
 485                 else
 486                         limit = &intel_limits_vlv_dp;
 487         } else if (!IS_GEN2(dev)) {
 488                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 489                         limit = &intel_limits_i9xx_lvds;
 490                 else
 491                         limit = &intel_limits_i9xx_sdvo;
 492         } else {
 493                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 494                         limit = &intel_limits_i8xx_lvds;
 495                 else
 496                         limit = &intel_limits_i8xx_dvo;
 497         }
 498         return limit;
 499 }
 500
 501 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 502 static void pineview_clock(int refclk, intel_clock_t *clock)
 503 {
 504         clock->m = clock->m2 + 2;
 505         clock->p = clock->p1 * clock->p2;
 506         clock->vco = refclk * clock->m / clock->n;
 507         clock->dot = clock->vco / clock->p;
 508 }
 509
 510 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
 511 {
 512         return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
 513 }
 514
 515 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 516 {
 517         if (IS_PINEVIEW(dev)) {
 518                 pineview_clock(refclk, clock);
 519                 return;
 520         }
 521         clock->m = i9xx_dpll_compute_m(clock);
 522         clock->p = clock->p1 * clock->p2;
 523         clock->vco = refclk * clock->m / (clock->n + 2);
 524         clock->dot = clock->vco / clock->p;
 525 }
 526
 527 /**
 528  * Returns whether any output on the specified pipe is of the specified type
 529  */
 530 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 531 {
 532         struct drm_device *dev = crtc->dev;
 533         struct intel_encoder *encoder;
 534
 535         for_each_encoder_on_crtc(dev, crtc, encoder)
 536                 if (encoder->type == type)
 537                         return true;
 538
 539         return false;
 540 }
 541
 542 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 543 /**
 544  * Returns whether the given set of divisors are valid for a given refclk with
 545  * the given connectors.
 546  */
 547
 548 static bool intel_PLL_is_valid(struct drm_device *dev,
 549                                const intel_limit_t *limit,
 550                                const intel_clock_t *clock)
 551 {
 552         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 553                 INTELPllInvalid("p1 out of range\n");
 554         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 555                 INTELPllInvalid("p out of range\n");
 556         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 557                 INTELPllInvalid("m2 out of range\n");
 558         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 559                 INTELPllInvalid("m1 out of range\n");
 560         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 561                 INTELPllInvalid("m1 <= m2\n");
 562         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 563                 INTELPllInvalid("m out of range\n");
 564         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 565                 INTELPllInvalid("n out of range\n");
 566         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 567                 INTELPllInvalid("vco out of range\n");
 568         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 569          * connector, etc., rather than just a single range.
 570          */
 571         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 572                 INTELPllInvalid("dot out of range\n");
 573
 574         return true;
 575 }
 576
 577 static bool
 578 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 579                     int target, int refclk, intel_clock_t *match_clock,
 580                     intel_clock_t *best_clock)
 581
 582 {
 583         struct drm_device *dev = crtc->dev;
 584         intel_clock_t clock;
 585         int err = target;
 586
 587         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 588                 /*
 589                  * For LVDS just rely on its current settings for dual-channel.
 590                  * We haven't figured out how to reliably set up different
 591                  * single/dual channel state, if we even can.
 592                  */
 593                 if (intel_is_dual_link_lvds(dev))
 594                         clock.p2 = limit->p2.p2_fast;
 595                 else
 596                         clock.p2 = limit->p2.p2_slow;
 597         } else {
 598                 if (target < limit->p2.dot_limit)
 599                         clock.p2 = limit->p2.p2_slow;
 600                 else
 601                         clock.p2 = limit->p2.p2_fast;
 602         }
 603
 604         memset(best_clock, 0, sizeof(*best_clock));
 605
 606         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 607              clock.m1++) {
 608                 for (clock.m2 = limit->m2.min;
 609                      clock.m2 <= limit->m2.max; clock.m2++) {
 610                         /* m1 is always 0 in Pineview */
 611                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 612                                 break;
 613                         for (clock.n = limit->n.min;
 614                              clock.n <= limit->n.max; clock.n++) {
 615                                 for (clock.p1 = limit->p1.min;
 616                                         clock.p1 <= limit->p1.max; clock.p1++) {
 617                                         int this_err;
 618
 619                                         intel_clock(dev, refclk, &clock);
 620                                         if (!intel_PLL_is_valid(dev, limit,
 621                                                                 &clock))
 622                                                 continue;
 623                                         if (match_clock &&
 624                                             clock.p != match_clock->p)
 625                                                 continue;
 626
 627                                         this_err = abs(clock.dot - target);
 628                                         if (this_err < err) {
 629                                                 *best_clock = clock;
 630                                                 err = this_err;
 631                                         }
 632                                 }
 633                         }
 634                 }
 635         }
 636
 637         return (err != target);
 638 }
 639
 640 static bool
 641 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 642                         int target, int refclk, intel_clock_t *match_clock,
 643                         intel_clock_t *best_clock)
 644 {
 645         struct drm_device *dev = crtc->dev;
 646         intel_clock_t clock;
 647         int max_n;
 648         bool found;
 649         /* approximately equals target * 0.00585 */
 650         int err_most = (target >> 8) + (target >> 9);
 651         found = false;
 652
 653         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 654                 int lvds_reg;
 655
 656                 if (HAS_PCH_SPLIT(dev))
 657                         lvds_reg = PCH_LVDS;
 658                 else
 659                         lvds_reg = LVDS;
 660                 if (intel_is_dual_link_lvds(dev))
 661                         clock.p2 = limit->p2.p2_fast;
 662                 else
 663                         clock.p2 = limit->p2.p2_slow;
 664         } else {
 665                 if (target < limit->p2.dot_limit)
 666                         clock.p2 = limit->p2.p2_slow;
 667                 else
 668                         clock.p2 = limit->p2.p2_fast;
 669         }
 670
 671         memset(best_clock, 0, sizeof(*best_clock));
 672         max_n = limit->n.max;
 673         /* based on hardware requirement, prefer smaller n to precision */
 674         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 675                 /* based on hardware requirement, prefere larger m1,m2 */
 676                 for (clock.m1 = limit->m1.max;
 677                      clock.m1 >= limit->m1.min; clock.m1--) {
 678                         for (clock.m2 = limit->m2.max;
 679                              clock.m2 >= limit->m2.min; clock.m2--) {
 680                                 for (clock.p1 = limit->p1.max;
 681                                      clock.p1 >= limit->p1.min; clock.p1--) {
 682                                         int this_err;
 683
 684                                         intel_clock(dev, refclk, &clock);
 685                                         if (!intel_PLL_is_valid(dev, limit,
 686                                                                 &clock))
 687                                                 continue;
 688
 689                                         this_err = abs(clock.dot - target);
 690                                         if (this_err < err_most) {
 691                                                 *best_clock = clock;
 692                                                 err_most = this_err;
 693                                                 max_n = clock.n;
 694                                                 found = true;
 695                                         }
 696                                 }
 697                         }
 698                 }
 699         }
 700         return found;
 701 }
 702
 703 static bool
 704 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 705                         int target, int refclk, intel_clock_t *match_clock,
 706                         intel_clock_t *best_clock)
 707 {
 708         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 709         u32 m, n, fastclk;
 710         u32 updrate, minupdate, fracbits, p;
 711         unsigned long bestppm, ppm, absppm;
 712         int dotclk, flag;
 713
 714         flag = 0;
 715         dotclk = target * 1000;
 716         bestppm = 1000000;
 717         ppm = absppm = 0;
 718         fastclk = dotclk / (2*100);
 719         updrate = 0;
 720         minupdate = 19200;
 721         fracbits = 1;
 722         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 723         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 724
 725         /* based on hardware requirement, prefer smaller n to precision */
 726         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 727                 updrate = refclk / n;
 728                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 729                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 730                                 if (p2 > 10)
 731                                         p2 = p2 - 1;
 732                                 p = p1 * p2;
 733                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 734                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 735                                         m2 = (((2*(fastclk * p * n / m1 )) +
 736                                                refclk) / (2*refclk));
 737                                         m = m1 * m2;
 738                                         vco = updrate * m;
 739                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 740                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 741                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 742                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 743                                                         bestppm = 0;
 744                                                         flag = 1;
 745                                                 }
 746                                                 if (absppm < bestppm - 10) {
 747                                                         bestppm = absppm;
 748                                                         flag = 1;
 749                                                 }
 750                                                 if (flag) {
 751                                                         bestn = n;
 752                                                         bestm1 = m1;
 753                                                         bestm2 = m2;
 754                                                         bestp1 = p1;
 755                                                         bestp2 = p2;
 756                                                         flag = 0;
 757                                                 }
 758                                         }
 759                                 }
 760                         }
 761                 }
 762         }
 763         best_clock->n = bestn;
 764         best_clock->m1 = bestm1;
 765         best_clock->m2 = bestm2;
 766         best_clock->p1 = bestp1;
 767         best_clock->p2 = bestp2;
 768
 769         return true;
 770 }
 771
 772 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 773                                              enum pipe pipe)
 774 {
 775         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 776         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 777
 778         return intel_crtc->config.cpu_transcoder;
 779 }
 780
 781 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 782 {
 783         struct drm_i915_private *dev_priv = dev->dev_private;
 784         u32 frame, frame_reg = PIPEFRAME(pipe);
 785
 786         frame = I915_READ(frame_reg);
 787
 788         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 789                 DRM_DEBUG_KMS("vblank wait timed out\n");
 790 }
 791
 792 /**
 793  * intel_wait_for_vblank - wait for vblank on a given pipe
 794  * @dev: drm device
 795  * @pipe: pipe to wait for
 796  *
 797  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 798  * mode setting code.
 799  */
 800 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 801 {
 802         struct drm_i915_private *dev_priv = dev->dev_private;
 803         int pipestat_reg = PIPESTAT(pipe);
 804
 805         if (INTEL_INFO(dev)->gen >= 5) {
 806                 ironlake_wait_for_vblank(dev, pipe);
 807                 return;
 808         }
 809
 810         /* Clear existing vblank status. Note this will clear any other
 811          * sticky status fields as well.
 812          *
 813          * This races with i915_driver_irq_handler() with the result
 814          * that either function could miss a vblank event.  Here it is not
 815          * fatal, as we will either wait upon the next vblank interrupt or
 816          * timeout.  Generally speaking intel_wait_for_vblank() is only
 817          * called during modeset at which time the GPU should be idle and
 818          * should *not* be performing page flips and thus not waiting on
 819          * vblanks...
 820          * Currently, the result of us stealing a vblank from the irq
 821          * handler is that a single frame will be skipped during swapbuffers.
 822          */
 823         I915_WRITE(pipestat_reg,
 824                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 825
 826         /* Wait for vblank interrupt bit to set */
 827         if (wait_for(I915_READ(pipestat_reg) &
 828                      PIPE_VBLANK_INTERRUPT_STATUS,
 829                      50))
 830                 DRM_DEBUG_KMS("vblank wait timed out\n");
 831 }
 832
 833 /*
 834  * intel_wait_for_pipe_off - wait for pipe to turn off
 835  * @dev: drm device
 836  * @pipe: pipe to wait for
 837  *
 838  * After disabling a pipe, we can't wait for vblank in the usual way,
 839  * spinning on the vblank interrupt status bit, since we won't actually
 840  * see an interrupt when the pipe is disabled.
 841  *
 842  * On Gen4 and above:
 843  *   wait for the pipe register state bit to turn off
 844  *
 845  * Otherwise:
 846  *   wait for the display line value to settle (it usually
 847  *   ends up stopping at the start of the next frame).
 848  *
 849  */
 850 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 851 {
 852         struct drm_i915_private *dev_priv = dev->dev_private;
 853         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 854                                                                       pipe);
 855
 856         if (INTEL_INFO(dev)->gen >= 4) {
 857                 int reg = PIPECONF(cpu_transcoder);
 858
 859                 /* Wait for the Pipe State to go off */
 860                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 861                              100))
 862                         WARN(1, "pipe_off wait timed out\n");
 863         } else {
 864                 u32 last_line, line_mask;
 865                 int reg = PIPEDSL(pipe);
 866                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 867
 868                 if (IS_GEN2(dev))
 869                         line_mask = DSL_LINEMASK_GEN2;
 870                 else
 871                         line_mask = DSL_LINEMASK_GEN3;
 872
 873                 /* Wait for the display line to settle */
 874                 do {
 875                         last_line = I915_READ(reg) & line_mask;
 876                         mdelay(5);
 877                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 878                          time_after(timeout, jiffies));
 879                 if (time_after(jiffies, timeout))
 880                         WARN(1, "pipe_off wait timed out\n");
 881         }
 882 }
 883
 884 /*
 885  * ibx_digital_port_connected - is the specified port connected?
 886  * @dev_priv: i915 private structure
 887  * @port: the port to test
 888  *
 889  * Returns true if @port is connected, false otherwise.
 890  */
 891 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
 892                                 struct intel_digital_port *port)
 893 {
 894         u32 bit;
 895
 896         if (HAS_PCH_IBX(dev_priv->dev)) {
 897                 switch(port->port) {
 898                 case PORT_B:
 899                         bit = SDE_PORTB_HOTPLUG;
 900                         break;
 901                 case PORT_C:
 902                         bit = SDE_PORTC_HOTPLUG;
 903                         break;
 904                 case PORT_D:
 905                         bit = SDE_PORTD_HOTPLUG;
 906                         break;
 907                 default:
 908                         return true;
 909                 }
 910         } else {
 911                 switch(port->port) {
 912                 case PORT_B:
 913                         bit = SDE_PORTB_HOTPLUG_CPT;
 914                         break;
 915                 case PORT_C:
 916                         bit = SDE_PORTC_HOTPLUG_CPT;
 917                         break;
 918                 case PORT_D:
 919                         bit = SDE_PORTD_HOTPLUG_CPT;
 920                         break;
 921                 default:
 922                         return true;
 923                 }
 924         }
 925
 926         return I915_READ(SDEISR) & bit;
 927 }
 928
 929 static const char *state_string(bool enabled)
 930 {
 931         return enabled ? "on" : "off";
 932 }
 933
 934 /* Only for pre-ILK configs */
 935 static void assert_pll(struct drm_i915_private *dev_priv,
 936                        enum pipe pipe, bool state)
 937 {
 938         int reg;
 939         u32 val;
 940         bool cur_state;
 941
 942         reg = DPLL(pipe);
 943         val = I915_READ(reg);
 944         cur_state = !!(val & DPLL_VCO_ENABLE);
 945         WARN(cur_state != state,
 946              "PLL state assertion failure (expected %s, current %s)\n",
 947              state_string(state), state_string(cur_state));
 948 }
 949 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
 950 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
 951
 952 /* For ILK+ */
 953 static void assert_pch_pll(struct drm_i915_private *dev_priv,
 954                            struct intel_pch_pll *pll,
 955                            struct intel_crtc *crtc,
 956                            bool state)
 957 {
 958         u32 val;
 959         bool cur_state;
 960
 961         if (HAS_PCH_LPT(dev_priv->dev)) {
 962                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
 963                 return;
 964         }
 965
 966         if (WARN (!pll,
 967                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
 968                 return;
 969
 970         val = I915_READ(pll->pll_reg);
 971         cur_state = !!(val & DPLL_VCO_ENABLE);
 972         WARN(cur_state != state,
 973              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
 974              pll->pll_reg, state_string(state), state_string(cur_state), val);
 975
 976         /* Make sure the selected PLL is correctly attached to the transcoder */
 977         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
 978                 u32 pch_dpll;
 979
 980                 pch_dpll = I915_READ(PCH_DPLL_SEL);
 981                 cur_state = pll->pll_reg == _PCH_DPLL_B;
 982                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
 983                           "PLL[%d] not attached to this transcoder %c: %08x\n",
 984                           cur_state, pipe_name(crtc->pipe), pch_dpll)) {
 985                         cur_state = !!(val >> (4*crtc->pipe + 3));
 986                         WARN(cur_state != state,
 987                              "PLL[%d] not %s on this transcoder %c: %08x\n",
 988                              pll->pll_reg == _PCH_DPLL_B,
 989                              state_string(state),
 990                              pipe_name(crtc->pipe),
 991                              val);
 992                 }
 993         }
 994 }
 995 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
 996 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
 997
 998 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
 999                           enum pipe pipe, bool state)
1000 {
1001         int reg;
1002         u32 val;
1003         bool cur_state;
1004         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1005                                                                       pipe);
1006
1007         if (HAS_DDI(dev_priv->dev)) {
1008                 /* DDI does not have a specific FDI_TX register */
1009                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1010                 val = I915_READ(reg);
1011                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1012         } else {
1013                 reg = FDI_TX_CTL(pipe);
1014                 val = I915_READ(reg);
1015                 cur_state = !!(val & FDI_TX_ENABLE);
1016         }
1017         WARN(cur_state != state,
1018              "FDI TX state assertion failure (expected %s, current %s)\n",
1019              state_string(state), state_string(cur_state));
1020 }
1021 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1022 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1023
1024 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1025                           enum pipe pipe, bool state)
1026 {
1027         int reg;
1028         u32 val;
1029         bool cur_state;
1030
1031         reg = FDI_RX_CTL(pipe);
1032         val = I915_READ(reg);
1033         cur_state = !!(val & FDI_RX_ENABLE);
1034         WARN(cur_state != state,
1035              "FDI RX state assertion failure (expected %s, current %s)\n",
1036              state_string(state), state_string(cur_state));
1037 }
1038 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1039 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1040
1041 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1042                                       enum pipe pipe)
1043 {
1044         int reg;
1045         u32 val;
1046
1047         /* ILK FDI PLL is always enabled */
1048         if (dev_priv->info->gen == 5)
1049                 return;
1050
1051         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1052         if (HAS_DDI(dev_priv->dev))
1053                 return;
1054
1055         reg = FDI_TX_CTL(pipe);
1056         val = I915_READ(reg);
1057         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1058 }
1059
1060 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1061                                       enum pipe pipe)
1062 {
1063         int reg;
1064         u32 val;
1065
1066         reg = FDI_RX_CTL(pipe);
1067         val = I915_READ(reg);
1068         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1069 }
1070
1071 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1072                                   enum pipe pipe)
1073 {
1074         int pp_reg, lvds_reg;
1075         u32 val;
1076         enum pipe panel_pipe = PIPE_A;
1077         bool locked = true;
1078
1079         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080                 pp_reg = PCH_PP_CONTROL;
1081                 lvds_reg = PCH_LVDS;
1082         } else {
1083                 pp_reg = PP_CONTROL;
1084                 lvds_reg = LVDS;
1085         }
1086
1087         val = I915_READ(pp_reg);
1088         if (!(val & PANEL_POWER_ON) ||
1089             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1090                 locked = false;
1091
1092         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1093                 panel_pipe = PIPE_B;
1094
1095         WARN(panel_pipe == pipe && locked,
1096              "panel assertion failure, pipe %c regs locked\n",
1097              pipe_name(pipe));
1098 }
1099
1100 void assert_pipe(struct drm_i915_private *dev_priv,
1101                  enum pipe pipe, bool state)
1102 {
1103         int reg;
1104         u32 val;
1105         bool cur_state;
1106         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1107                                                                       pipe);
1108
1109         /* if we need the pipe A quirk it must be always on */
1110         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1111                 state = true;
1112
1113         if (!intel_using_power_well(dev_priv->dev) &&
1114             cpu_transcoder != TRANSCODER_EDP) {
1115                 cur_state = false;
1116         } else {
1117                 reg = PIPECONF(cpu_transcoder);
1118                 val = I915_READ(reg);
1119                 cur_state = !!(val & PIPECONF_ENABLE);
1120         }
1121
1122         WARN(cur_state != state,
1123              "pipe %c assertion failure (expected %s, current %s)\n",
1124              pipe_name(pipe), state_string(state), state_string(cur_state));
1125 }
1126
1127 static void assert_plane(struct drm_i915_private *dev_priv,
1128                          enum plane plane, bool state)
1129 {
1130         int reg;
1131         u32 val;
1132         bool cur_state;
1133
1134         reg = DSPCNTR(plane);
1135         val = I915_READ(reg);
1136         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1137         WARN(cur_state != state,
1138              "plane %c assertion failure (expected %s, current %s)\n",
1139              plane_name(plane), state_string(state), state_string(cur_state));
1140 }
1141
1142 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1143 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1144
1145 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1146                                    enum pipe pipe)
1147 {
1148         int reg, i;
1149         u32 val;
1150         int cur_pipe;
1151
1152         /* Planes are fixed to pipes on ILK+ */
1153         if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
1154                 reg = DSPCNTR(pipe);
1155                 val = I915_READ(reg);
1156                 WARN((val & DISPLAY_PLANE_ENABLE),
1157                      "plane %c assertion failure, should be disabled but not\n",
1158                      plane_name(pipe));
1159                 return;
1160         }
1161
1162         /* Need to check both planes against the pipe */
1163         for (i = 0; i < 2; i++) {
1164                 reg = DSPCNTR(i);
1165                 val = I915_READ(reg);
1166                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1167                         DISPPLANE_SEL_PIPE_SHIFT;
1168                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1169                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1170                      plane_name(i), pipe_name(pipe));
1171         }
1172 }
1173
1174 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1175                                     enum pipe pipe)
1176 {
1177         int reg, i;
1178         u32 val;
1179
1180         if (!IS_VALLEYVIEW(dev_priv->dev))
1181                 return;
1182
1183         /* Need to check both planes against the pipe */
1184         for (i = 0; i < dev_priv->num_plane; i++) {
1185                 reg = SPCNTR(pipe, i);
1186                 val = I915_READ(reg);
1187                 WARN((val & SP_ENABLE),
1188                      "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1189                      sprite_name(pipe, i), pipe_name(pipe));
1190         }
1191 }
1192
1193 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1194 {
1195         u32 val;
1196         bool enabled;
1197
1198         if (HAS_PCH_LPT(dev_priv->dev)) {
1199                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1200                 return;
1201         }
1202
1203         val = I915_READ(PCH_DREF_CONTROL);
1204         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1205                             DREF_SUPERSPREAD_SOURCE_MASK));
1206         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1207 }
1208
1209 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1210                                            enum pipe pipe)
1211 {
1212         int reg;
1213         u32 val;
1214         bool enabled;
1215
1216         reg = PCH_TRANSCONF(pipe);
1217         val = I915_READ(reg);
1218         enabled = !!(val & TRANS_ENABLE);
1219         WARN(enabled,
1220              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1221              pipe_name(pipe));
1222 }
1223
1224 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1225                             enum pipe pipe, u32 port_sel, u32 val)
1226 {
1227         if ((val & DP_PORT_EN) == 0)
1228                 return false;
1229
1230         if (HAS_PCH_CPT(dev_priv->dev)) {
1231                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1232                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1233                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1234                         return false;
1235         } else {
1236                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1237                         return false;
1238         }
1239         return true;
1240 }
1241
1242 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1243                               enum pipe pipe, u32 val)
1244 {
1245         if ((val & SDVO_ENABLE) == 0)
1246                 return false;
1247
1248         if (HAS_PCH_CPT(dev_priv->dev)) {
1249                 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1250                         return false;
1251         } else {
1252                 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1253                         return false;
1254         }
1255         return true;
1256 }
1257
1258 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1259                               enum pipe pipe, u32 val)
1260 {
1261         if ((val & LVDS_PORT_EN) == 0)
1262                 return false;
1263
1264         if (HAS_PCH_CPT(dev_priv->dev)) {
1265                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1266                         return false;
1267         } else {
1268                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1269                         return false;
1270         }
1271         return true;
1272 }
1273
1274 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1275                               enum pipe pipe, u32 val)
1276 {
1277         if ((val & ADPA_DAC_ENABLE) == 0)
1278                 return false;
1279         if (HAS_PCH_CPT(dev_priv->dev)) {
1280                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281                         return false;
1282         } else {
1283                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1284                         return false;
1285         }
1286         return true;
1287 }
1288
1289 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1290                                    enum pipe pipe, int reg, u32 port_sel)
1291 {
1292         u32 val = I915_READ(reg);
1293         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1294              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1295              reg, pipe_name(pipe));
1296
1297         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1298              && (val & DP_PIPEB_SELECT),
1299              "IBX PCH dp port still using transcoder B\n");
1300 }
1301
1302 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1303                                      enum pipe pipe, int reg)
1304 {
1305         u32 val = I915_READ(reg);
1306         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1307              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1308              reg, pipe_name(pipe));
1309
1310         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1311              && (val & SDVO_PIPE_B_SELECT),
1312              "IBX PCH hdmi port still using transcoder B\n");
1313 }
1314
1315 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1316                                       enum pipe pipe)
1317 {
1318         int reg;
1319         u32 val;
1320
1321         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1322         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1323         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1324
1325         reg = PCH_ADPA;
1326         val = I915_READ(reg);
1327         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1328              "PCH VGA enabled on transcoder %c, should be disabled\n",
1329              pipe_name(pipe));
1330
1331         reg = PCH_LVDS;
1332         val = I915_READ(reg);
1333         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1334              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1335              pipe_name(pipe));
1336
1337         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1338         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1339         assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1340 }
1341
1342 /**
1343  * intel_enable_pll - enable a PLL
1344  * @dev_priv: i915 private structure
1345  * @pipe: pipe PLL to enable
1346  *
1347  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1348  * make sure the PLL reg is writable first though, since the panel write
1349  * protect mechanism may be enabled.
1350  *
1351  * Note!  This is for pre-ILK only.
1352  *
1353  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1354  */
1355 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1356 {
1357         int reg;
1358         u32 val;
1359
1360         assert_pipe_disabled(dev_priv, pipe);
1361
1362         /* No really, not for ILK+ */
1363         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1364
1365         /* PLL is protected by panel, make sure we can write it */
1366         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1367                 assert_panel_unlocked(dev_priv, pipe);
1368
1369         reg = DPLL(pipe);
1370         val = I915_READ(reg);
1371         val |= DPLL_VCO_ENABLE;
1372
1373         /* We do this three times for luck */
1374         I915_WRITE(reg, val);
1375         POSTING_READ(reg);
1376         udelay(150); /* wait for warmup */
1377         I915_WRITE(reg, val);
1378         POSTING_READ(reg);
1379         udelay(150); /* wait for warmup */
1380         I915_WRITE(reg, val);
1381         POSTING_READ(reg);
1382         udelay(150); /* wait for warmup */
1383 }
1384
1385 /**
1386  * intel_disable_pll - disable a PLL
1387  * @dev_priv: i915 private structure
1388  * @pipe: pipe PLL to disable
1389  *
1390  * Disable the PLL for @pipe, making sure the pipe is off first.
1391  *
1392  * Note!  This is for pre-ILK only.
1393  */
1394 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395 {
1396         int reg;
1397         u32 val;
1398
1399         /* Don't disable pipe A or pipe A PLLs if needed */
1400         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401                 return;
1402
1403         /* Make sure the pipe isn't still relying on us */
1404         assert_pipe_disabled(dev_priv, pipe);
1405
1406         reg = DPLL(pipe);
1407         val = I915_READ(reg);
1408         val &= ~DPLL_VCO_ENABLE;
1409         I915_WRITE(reg, val);
1410         POSTING_READ(reg);
1411 }
1412
1413 /* SBI access */
1414 static void
1415 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1416                 enum intel_sbi_destination destination)
1417 {
1418         u32 tmp;
1419
1420         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1421
1422         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1423                                 100)) {
1424                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1425                 return;
1426         }
1427
1428         I915_WRITE(SBI_ADDR, (reg << 16));
1429         I915_WRITE(SBI_DATA, value);
1430
1431         if (destination == SBI_ICLK)
1432                 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1433         else
1434                 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1435         I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
1436
1437         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1438                                 100)) {
1439                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1440                 return;
1441         }
1442 }
1443
1444 static u32
1445 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1446                enum intel_sbi_destination destination)
1447 {
1448         u32 value = 0;
1449         WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
1450
1451         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1452                                 100)) {
1453                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1454                 return 0;
1455         }
1456
1457         I915_WRITE(SBI_ADDR, (reg << 16));
1458
1459         if (destination == SBI_ICLK)
1460                 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1461         else
1462                 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1463         I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
1464
1465         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1466                                 100)) {
1467                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1468                 return 0;
1469         }
1470
1471         return I915_READ(SBI_DATA);
1472 }
1473
1474 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1475 {
1476         u32 port_mask;
1477
1478         if (!port)
1479                 port_mask = DPLL_PORTB_READY_MASK;
1480         else
1481                 port_mask = DPLL_PORTC_READY_MASK;
1482
1483         if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1484                 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1485                      'B' + port, I915_READ(DPLL(0)));
1486 }
1487
1488 /**
1489  * ironlake_enable_pch_pll - enable PCH PLL
1490  * @dev_priv: i915 private structure
1491  * @pipe: pipe PLL to enable
1492  *
1493  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1494  * drives the transcoder clock.
1495  */
1496 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1497 {
1498         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1499         struct intel_pch_pll *pll;
1500         int reg;
1501         u32 val;
1502
1503         /* PCH PLLs only available on ILK, SNB and IVB */
1504         BUG_ON(dev_priv->info->gen < 5);
1505         pll = intel_crtc->pch_pll;
1506         if (pll == NULL)
1507                 return;
1508
1509         if (WARN_ON(pll->refcount == 0))
1510                 return;
1511
1512         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1513                       pll->pll_reg, pll->active, pll->on,
1514                       intel_crtc->base.base.id);
1515
1516         /* PCH refclock must be enabled first */
1517         assert_pch_refclk_enabled(dev_priv);
1518
1519         if (pll->active++ && pll->on) {
1520                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1521                 return;
1522         }
1523
1524         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1525
1526         reg = pll->pll_reg;
1527         val = I915_READ(reg);
1528         val |= DPLL_VCO_ENABLE;
1529         I915_WRITE(reg, val);
1530         POSTING_READ(reg);
1531         udelay(200);
1532
1533         pll->on = true;
1534 }
1535
1536 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1537 {
1538         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1539         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1540         int reg;
1541         u32 val;
1542
1543         /* PCH only available on ILK+ */
1544         BUG_ON(dev_priv->info->gen < 5);
1545         if (pll == NULL)
1546                return;
1547
1548         if (WARN_ON(pll->refcount == 0))
1549                 return;
1550
1551         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1552                       pll->pll_reg, pll->active, pll->on,
1553                       intel_crtc->base.base.id);
1554
1555         if (WARN_ON(pll->active == 0)) {
1556                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1557                 return;
1558         }
1559
1560         if (--pll->active) {
1561                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1562                 return;
1563         }
1564
1565         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1566
1567         /* Make sure transcoder isn't still depending on us */
1568         assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
1569
1570         reg = pll->pll_reg;
1571         val = I915_READ(reg);
1572         val &= ~DPLL_VCO_ENABLE;
1573         I915_WRITE(reg, val);
1574         POSTING_READ(reg);
1575         udelay(200);
1576
1577         pll->on = false;
1578 }
1579
1580 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581                                            enum pipe pipe)
1582 {
1583         struct drm_device *dev = dev_priv->dev;
1584         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1585         uint32_t reg, val, pipeconf_val;
1586
1587         /* PCH only available on ILK+ */
1588         BUG_ON(dev_priv->info->gen < 5);
1589
1590         /* Make sure PCH DPLL is enabled */
1591         assert_pch_pll_enabled(dev_priv,
1592                                to_intel_crtc(crtc)->pch_pll,
1593                                to_intel_crtc(crtc));
1594
1595         /* FDI must be feeding us bits for PCH ports */
1596         assert_fdi_tx_enabled(dev_priv, pipe);
1597         assert_fdi_rx_enabled(dev_priv, pipe);
1598
1599         if (HAS_PCH_CPT(dev)) {
1600                 /* Workaround: Set the timing override bit before enabling the
1601                  * pch transcoder. */
1602                 reg = TRANS_CHICKEN2(pipe);
1603                 val = I915_READ(reg);
1604                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605                 I915_WRITE(reg, val);
1606         }
1607
1608         reg = PCH_TRANSCONF(pipe);
1609         val = I915_READ(reg);
1610         pipeconf_val = I915_READ(PIPECONF(pipe));
1611
1612         if (HAS_PCH_IBX(dev_priv->dev)) {
1613                 /*
1614                  * make the BPC in transcoder be consistent with
1615                  * that in pipeconf reg.
1616                  */
1617                 val &= ~PIPECONF_BPC_MASK;
1618                 val |= pipeconf_val & PIPECONF_BPC_MASK;
1619         }
1620
1621         val &= ~TRANS_INTERLACE_MASK;
1622         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1623                 if (HAS_PCH_IBX(dev_priv->dev) &&
1624                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625                         val |= TRANS_LEGACY_INTERLACED_ILK;
1626                 else
1627                         val |= TRANS_INTERLACED;
1628         else
1629                 val |= TRANS_PROGRESSIVE;
1630
1631         I915_WRITE(reg, val | TRANS_ENABLE);
1632         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1633                 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1634 }
1635
1636 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1637                                       enum transcoder cpu_transcoder)
1638 {
1639         u32 val, pipeconf_val;
1640
1641         /* PCH only available on ILK+ */
1642         BUG_ON(dev_priv->info->gen < 5);
1643
1644         /* FDI must be feeding us bits for PCH ports */
1645         assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1646         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1647
1648         /* Workaround: set timing override bit. */
1649         val = I915_READ(_TRANSA_CHICKEN2);
1650         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1651         I915_WRITE(_TRANSA_CHICKEN2, val);
1652
1653         val = TRANS_ENABLE;
1654         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1655
1656         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657             PIPECONF_INTERLACED_ILK)
1658                 val |= TRANS_INTERLACED;
1659         else
1660                 val |= TRANS_PROGRESSIVE;
1661
1662         I915_WRITE(LPT_TRANSCONF, val);
1663         if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1664                 DRM_ERROR("Failed to enable PCH transcoder\n");
1665 }
1666
1667 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668                                             enum pipe pipe)
1669 {
1670         struct drm_device *dev = dev_priv->dev;
1671         uint32_t reg, val;
1672
1673         /* FDI relies on the transcoder */
1674         assert_fdi_tx_disabled(dev_priv, pipe);
1675         assert_fdi_rx_disabled(dev_priv, pipe);
1676
1677         /* Ports must be off as well */
1678         assert_pch_ports_disabled(dev_priv, pipe);
1679
1680         reg = PCH_TRANSCONF(pipe);
1681         val = I915_READ(reg);
1682         val &= ~TRANS_ENABLE;
1683         I915_WRITE(reg, val);
1684         /* wait for PCH transcoder off, transcoder state */
1685         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1686                 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1687
1688         if (!HAS_PCH_IBX(dev)) {
1689                 /* Workaround: Clear the timing override chicken bit again. */
1690                 reg = TRANS_CHICKEN2(pipe);
1691                 val = I915_READ(reg);
1692                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693                 I915_WRITE(reg, val);
1694         }
1695 }
1696
1697 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1698 {
1699         u32 val;
1700
1701         val = I915_READ(LPT_TRANSCONF);
1702         val &= ~TRANS_ENABLE;
1703         I915_WRITE(LPT_TRANSCONF, val);
1704         /* wait for PCH transcoder off, transcoder state */
1705         if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1706                 DRM_ERROR("Failed to disable PCH transcoder\n");
1707
1708         /* Workaround: clear timing override bit. */
1709         val = I915_READ(_TRANSA_CHICKEN2);
1710         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1711         I915_WRITE(_TRANSA_CHICKEN2, val);
1712 }
1713
1714 /**
1715  * intel_enable_pipe - enable a pipe, asserting requirements
1716  * @dev_priv: i915 private structure
1717  * @pipe: pipe to enable
1718  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1719  *
1720  * Enable @pipe, making sure that various hardware specific requirements
1721  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722  *
1723  * @pipe should be %PIPE_A or %PIPE_B.
1724  *
1725  * Will wait until the pipe is actually running (i.e. first vblank) before
1726  * returning.
1727  */
1728 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729                               bool pch_port)
1730 {
1731         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732                                                                       pipe);
1733         enum pipe pch_transcoder;
1734         int reg;
1735         u32 val;
1736
1737         assert_planes_disabled(dev_priv, pipe);
1738         assert_sprites_disabled(dev_priv, pipe);
1739
1740         if (HAS_PCH_LPT(dev_priv->dev))
1741                 pch_transcoder = TRANSCODER_A;
1742         else
1743                 pch_transcoder = pipe;
1744
1745         /*
1746          * A pipe without a PLL won't actually be able to drive bits from
1747          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1748          * need the check.
1749          */
1750         if (!HAS_PCH_SPLIT(dev_priv->dev))
1751                 assert_pll_enabled(dev_priv, pipe);
1752         else {
1753                 if (pch_port) {
1754                         /* if driving the PCH, we need FDI enabled */
1755                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1756                         assert_fdi_tx_pll_enabled(dev_priv,
1757                                                   (enum pipe) cpu_transcoder);
1758                 }
1759                 /* FIXME: assert CPU port conditions for SNB+ */
1760         }
1761
1762         reg = PIPECONF(cpu_transcoder);
1763         val = I915_READ(reg);
1764         if (val & PIPECONF_ENABLE)
1765                 return;
1766
1767         I915_WRITE(reg, val | PIPECONF_ENABLE);
1768         intel_wait_for_vblank(dev_priv->dev, pipe);
1769 }
1770
1771 /**
1772  * intel_disable_pipe - disable a pipe, asserting requirements
1773  * @dev_priv: i915 private structure
1774  * @pipe: pipe to disable
1775  *
1776  * Disable @pipe, making sure that various hardware specific requirements
1777  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1778  *
1779  * @pipe should be %PIPE_A or %PIPE_B.
1780  *
1781  * Will wait until the pipe has shut down before returning.
1782  */
1783 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1784                                enum pipe pipe)
1785 {
1786         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1787                                                                       pipe);
1788         int reg;
1789         u32 val;
1790
1791         /*
1792          * Make sure planes won't keep trying to pump pixels to us,
1793          * or we might hang the display.
1794          */
1795         assert_planes_disabled(dev_priv, pipe);
1796         assert_sprites_disabled(dev_priv, pipe);
1797
1798         /* Don't disable pipe A or pipe A PLLs if needed */
1799         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1800                 return;
1801
1802         reg = PIPECONF(cpu_transcoder);
1803         val = I915_READ(reg);
1804         if ((val & PIPECONF_ENABLE) == 0)
1805                 return;
1806
1807         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1808         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1809 }
1810
1811 /*
1812  * Plane regs are double buffered, going from enabled->disabled needs a
1813  * trigger in order to latch.  The display address reg provides this.
1814  */
1815 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1816                                       enum plane plane)
1817 {
1818         if (dev_priv->info->gen >= 4)
1819                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1820         else
1821                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1822 }
1823
1824 /**
1825  * intel_enable_plane - enable a display plane on a given pipe
1826  * @dev_priv: i915 private structure
1827  * @plane: plane to enable
1828  * @pipe: pipe being fed
1829  *
1830  * Enable @plane on @pipe, making sure that @pipe is running first.
1831  */
1832 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833                                enum plane plane, enum pipe pipe)
1834 {
1835         int reg;
1836         u32 val;
1837
1838         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839         assert_pipe_enabled(dev_priv, pipe);
1840
1841         reg = DSPCNTR(plane);
1842         val = I915_READ(reg);
1843         if (val & DISPLAY_PLANE_ENABLE)
1844                 return;
1845
1846         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1847         intel_flush_display_plane(dev_priv, plane);
1848         intel_wait_for_vblank(dev_priv->dev, pipe);
1849 }
1850
1851 /**
1852  * intel_disable_plane - disable a display plane
1853  * @dev_priv: i915 private structure
1854  * @plane: plane to disable
1855  * @pipe: pipe consuming the data
1856  *
1857  * Disable @plane; should be an independent operation.
1858  */
1859 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860                                 enum plane plane, enum pipe pipe)
1861 {
1862         int reg;
1863         u32 val;
1864
1865         reg = DSPCNTR(plane);
1866         val = I915_READ(reg);
1867         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1868                 return;
1869
1870         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1871         intel_flush_display_plane(dev_priv, plane);
1872         intel_wait_for_vblank(dev_priv->dev, pipe);
1873 }
1874
1875 static bool need_vtd_wa(struct drm_device *dev)
1876 {
1877 #ifdef CONFIG_INTEL_IOMMU
1878         if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1879                 return true;
1880 #endif
1881         return false;
1882 }
1883
1884 int
1885 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1886                            struct drm_i915_gem_object *obj,
1887                            struct intel_ring_buffer *pipelined)
1888 {
1889         struct drm_i915_private *dev_priv = dev->dev_private;
1890         u32 alignment;
1891         int ret;
1892
1893         switch (obj->tiling_mode) {
1894         case I915_TILING_NONE:
1895                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1896                         alignment = 128 * 1024;
1897                 else if (INTEL_INFO(dev)->gen >= 4)
1898                         alignment = 4 * 1024;
1899                 else
1900                         alignment = 64 * 1024;
1901                 break;
1902         case I915_TILING_X:
1903                 /* pin() will align the object as required by fence */
1904                 alignment = 0;
1905                 break;
1906         case I915_TILING_Y:
1907                 /* Despite that we check this in framebuffer_init userspace can
1908                  * screw us over and change the tiling after the fact. Only
1909                  * pinned buffers can't change their tiling. */
1910                 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1911                 return -EINVAL;
1912         default:
1913                 BUG();
1914         }
1915
1916         /* Note that the w/a also requires 64 PTE of padding following the
1917          * bo. We currently fill all unused PTE with the shadow page and so
1918          * we should always have valid PTE following the scanout preventing
1919          * the VT-d warning.
1920          */
1921         if (need_vtd_wa(dev) && alignment < 256 * 1024)
1922                 alignment = 256 * 1024;
1923
1924         dev_priv->mm.interruptible = false;
1925         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1926         if (ret)
1927                 goto err_interruptible;
1928
1929         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930          * fence, whereas 965+ only requires a fence if using
1931          * framebuffer compression.  For simplicity, we always install
1932          * a fence as the cost is not that onerous.
1933          */
1934         ret = i915_gem_object_get_fence(obj);
1935         if (ret)
1936                 goto err_unpin;
1937
1938         i915_gem_object_pin_fence(obj);
1939
1940         dev_priv->mm.interruptible = true;
1941         return 0;
1942
1943 err_unpin:
1944         i915_gem_object_unpin(obj);
1945 err_interruptible:
1946         dev_priv->mm.interruptible = true;
1947         return ret;
1948 }
1949
1950 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951 {
1952         i915_gem_object_unpin_fence(obj);
1953         i915_gem_object_unpin(obj);
1954 }
1955
1956 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957  * is assumed to be a power-of-two. */
1958 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1959                                              unsigned int tiling_mode,
1960                                              unsigned int cpp,
1961                                              unsigned int pitch)
1962 {
1963         if (tiling_mode != I915_TILING_NONE) {
1964                 unsigned int tile_rows, tiles;
1965
1966                 tile_rows = *y / 8;
1967                 *y %= 8;
1968
1969                 tiles = *x / (512/cpp);
1970                 *x %= 512/cpp;
1971
1972                 return tile_rows * pitch * 8 + tiles * 4096;
1973         } else {
1974                 unsigned int offset;
1975
1976                 offset = *y * pitch + *x * cpp;
1977                 *y = 0;
1978                 *x = (offset & 4095) / cpp;
1979                 return offset & -4096;
1980         }
1981 }
1982
1983 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1984                              int x, int y)
1985 {
1986         struct drm_device *dev = crtc->dev;
1987         struct drm_i915_private *dev_priv = dev->dev_private;
1988         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1989         struct intel_framebuffer *intel_fb;
1990         struct drm_i915_gem_object *obj;
1991         int plane = intel_crtc->plane;
1992         unsigned long linear_offset;
1993         u32 dspcntr;
1994         u32 reg;
1995
1996         switch (plane) {
1997         case 0:
1998         case 1:
1999                 break;
2000         default:
2001                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2002                 return -EINVAL;
2003         }
2004
2005         intel_fb = to_intel_framebuffer(fb);
2006         obj = intel_fb->obj;
2007
2008         reg = DSPCNTR(plane);
2009         dspcntr = I915_READ(reg);
2010         /* Mask out pixel format bits in case we change it */
2011         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2012         switch (fb->pixel_format) {
2013         case DRM_FORMAT_C8:
2014                 dspcntr |= DISPPLANE_8BPP;
2015                 break;
2016         case DRM_FORMAT_XRGB1555:
2017         case DRM_FORMAT_ARGB1555:
2018                 dspcntr |= DISPPLANE_BGRX555;
2019                 break;
2020         case DRM_FORMAT_RGB565:
2021                 dspcntr |= DISPPLANE_BGRX565;
2022                 break;
2023         case DRM_FORMAT_XRGB8888:
2024         case DRM_FORMAT_ARGB8888:
2025                 dspcntr |= DISPPLANE_BGRX888;
2026                 break;
2027         case DRM_FORMAT_XBGR8888:
2028         case DRM_FORMAT_ABGR8888:
2029                 dspcntr |= DISPPLANE_RGBX888;
2030                 break;
2031         case DRM_FORMAT_XRGB2101010:
2032         case DRM_FORMAT_ARGB2101010:
2033                 dspcntr |= DISPPLANE_BGRX101010;
2034                 break;
2035         case DRM_FORMAT_XBGR2101010:
2036         case DRM_FORMAT_ABGR2101010:
2037                 dspcntr |= DISPPLANE_RGBX101010;
2038                 break;
2039         default:
2040                 BUG();
2041         }
2042
2043         if (INTEL_INFO(dev)->gen >= 4) {
2044                 if (obj->tiling_mode != I915_TILING_NONE)
2045                         dspcntr |= DISPPLANE_TILED;
2046                 else
2047                         dspcntr &= ~DISPPLANE_TILED;
2048         }
2049
2050         I915_WRITE(reg, dspcntr);
2051
2052         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2053
2054         if (INTEL_INFO(dev)->gen >= 4) {
2055                 intel_crtc->dspaddr_offset =
2056                         intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2057                                                        fb->bits_per_pixel / 8,
2058                                                        fb->pitches[0]);
2059                 linear_offset -= intel_crtc->dspaddr_offset;
2060         } else {
2061                 intel_crtc->dspaddr_offset = linear_offset;
2062         }
2063
2064         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2065                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2066         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2067         if (INTEL_INFO(dev)->gen >= 4) {
2068                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2069                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2070                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2071                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2072         } else
2073                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2074         POSTING_READ(reg);
2075
2076         return 0;
2077 }
2078
2079 static int ironlake_update_plane(struct drm_crtc *crtc,
2080                                  struct drm_framebuffer *fb, int x, int y)
2081 {
2082         struct drm_device *dev = crtc->dev;
2083         struct drm_i915_private *dev_priv = dev->dev_private;
2084         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085         struct intel_framebuffer *intel_fb;
2086         struct drm_i915_gem_object *obj;
2087         int plane = intel_crtc->plane;
2088         unsigned long linear_offset;
2089         u32 dspcntr;
2090         u32 reg;
2091
2092         switch (plane) {
2093         case 0:
2094         case 1:
2095         case 2:
2096                 break;
2097         default:
2098                 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
2099                 return -EINVAL;
2100         }
2101
2102         intel_fb = to_intel_framebuffer(fb);
2103         obj = intel_fb->obj;
2104
2105         reg = DSPCNTR(plane);
2106         dspcntr = I915_READ(reg);
2107         /* Mask out pixel format bits in case we change it */
2108         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2109         switch (fb->pixel_format) {
2110         case DRM_FORMAT_C8:
2111                 dspcntr |= DISPPLANE_8BPP;
2112                 break;
2113         case DRM_FORMAT_RGB565:
2114                 dspcntr |= DISPPLANE_BGRX565;
2115                 break;
2116         case DRM_FORMAT_XRGB8888:
2117         case DRM_FORMAT_ARGB8888:
2118                 dspcntr |= DISPPLANE_BGRX888;
2119                 break;
2120         case DRM_FORMAT_XBGR8888:
2121         case DRM_FORMAT_ABGR8888:
2122                 dspcntr |= DISPPLANE_RGBX888;
2123                 break;
2124         case DRM_FORMAT_XRGB2101010:
2125         case DRM_FORMAT_ARGB2101010:
2126                 dspcntr |= DISPPLANE_BGRX101010;
2127                 break;
2128         case DRM_FORMAT_XBGR2101010:
2129         case DRM_FORMAT_ABGR2101010:
2130                 dspcntr |= DISPPLANE_RGBX101010;
2131                 break;
2132         default:
2133                 BUG();
2134         }
2135
2136         if (obj->tiling_mode != I915_TILING_NONE)
2137                 dspcntr |= DISPPLANE_TILED;
2138         else
2139                 dspcntr &= ~DISPPLANE_TILED;
2140
2141         /* must disable */
2142         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2143
2144         I915_WRITE(reg, dspcntr);
2145
2146         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2147         intel_crtc->dspaddr_offset =
2148                 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2149                                                fb->bits_per_pixel / 8,
2150                                                fb->pitches[0]);
2151         linear_offset -= intel_crtc->dspaddr_offset;
2152
2153         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2154                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2155         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2156         I915_MODIFY_DISPBASE(DSPSURF(plane),
2157                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2158         if (IS_HASWELL(dev)) {
2159                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2160         } else {
2161                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2162                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2163         }
2164         POSTING_READ(reg);
2165
2166         return 0;
2167 }
2168
2169 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2170 static int
2171 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2172                            int x, int y, enum mode_set_atomic state)
2173 {
2174         struct drm_device *dev = crtc->dev;
2175         struct drm_i915_private *dev_priv = dev->dev_private;
2176
2177         if (dev_priv->display.disable_fbc)
2178                 dev_priv->display.disable_fbc(dev);
2179         intel_increase_pllclock(crtc);
2180
2181         return dev_priv->display.update_plane(crtc, fb, x, y);
2182 }
2183
2184 void intel_display_handle_reset(struct drm_device *dev)
2185 {
2186         struct drm_i915_private *dev_priv = dev->dev_private;
2187         struct drm_crtc *crtc;
2188
2189         /*
2190          * Flips in the rings have been nuked by the reset,
2191          * so complete all pending flips so that user space
2192          * will get its events and not get stuck.
2193          *
2194          * Also update the base address of all primary
2195          * planes to the the last fb to make sure we're
2196          * showing the correct fb after a reset.
2197          *
2198          * Need to make two loops over the crtcs so that we
2199          * don't try to grab a crtc mutex before the
2200          * pending_flip_queue really got woken up.
2201          */
2202
2203         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2204                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2205                 enum plane plane = intel_crtc->plane;
2206
2207                 intel_prepare_page_flip(dev, plane);
2208                 intel_finish_page_flip_plane(dev, plane);
2209         }
2210
2211         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2212                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214                 mutex_lock(&crtc->mutex);
2215                 if (intel_crtc->active)
2216                         dev_priv->display.update_plane(crtc, crtc->fb,
2217                                                        crtc->x, crtc->y);
2218                 mutex_unlock(&crtc->mutex);
2219         }
2220 }
2221
2222 static int
2223 intel_finish_fb(struct drm_framebuffer *old_fb)
2224 {
2225         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2226         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2227         bool was_interruptible = dev_priv->mm.interruptible;
2228         int ret;
2229
2230         /* Big Hammer, we also need to ensure that any pending
2231          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2232          * current scanout is retired before unpinning the old
2233          * framebuffer.
2234          *
2235          * This should only fail upon a hung GPU, in which case we
2236          * can safely continue.
2237          */
2238         dev_priv->mm.interruptible = false;
2239         ret = i915_gem_object_finish_gpu(obj);
2240         dev_priv->mm.interruptible = was_interruptible;
2241
2242         return ret;
2243 }
2244
2245 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2246 {
2247         struct drm_device *dev = crtc->dev;
2248         struct drm_i915_master_private *master_priv;
2249         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2250
2251         if (!dev->primary->master)
2252                 return;
2253
2254         master_priv = dev->primary->master->driver_priv;
2255         if (!master_priv->sarea_priv)
2256                 return;
2257
2258         switch (intel_crtc->pipe) {
2259         case 0:
2260                 master_priv->sarea_priv->pipeA_x = x;
2261                 master_priv->sarea_priv->pipeA_y = y;
2262                 break;
2263         case 1:
2264                 master_priv->sarea_priv->pipeB_x = x;
2265                 master_priv->sarea_priv->pipeB_y = y;
2266                 break;
2267         default:
2268                 break;
2269         }
2270 }
2271
2272 static int
2273 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2274                     struct drm_framebuffer *fb)
2275 {
2276         struct drm_device *dev = crtc->dev;
2277         struct drm_i915_private *dev_priv = dev->dev_private;
2278         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2279         struct drm_framebuffer *old_fb;
2280         int ret;
2281
2282         /* no fb bound */
2283         if (!fb) {
2284                 DRM_ERROR("No FB bound\n");
2285                 return 0;
2286         }
2287
2288         if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2289                 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2290                           plane_name(intel_crtc->plane),
2291                           INTEL_INFO(dev)->num_pipes);
2292                 return -EINVAL;
2293         }
2294
2295         mutex_lock(&dev->struct_mutex);
2296         ret = intel_pin_and_fence_fb_obj(dev,
2297                                          to_intel_framebuffer(fb)->obj,
2298                                          NULL);
2299         if (ret != 0) {
2300                 mutex_unlock(&dev->struct_mutex);
2301                 DRM_ERROR("pin & fence failed\n");
2302                 return ret;
2303         }
2304
2305         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2306         if (ret) {
2307                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2308                 mutex_unlock(&dev->struct_mutex);
2309                 DRM_ERROR("failed to update base address\n");
2310                 return ret;
2311         }
2312
2313         old_fb = crtc->fb;
2314         crtc->fb = fb;
2315         crtc->x = x;
2316         crtc->y = y;
2317
2318         if (old_fb) {
2319                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2320                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2321         }
2322
2323         intel_update_fbc(dev);
2324         mutex_unlock(&dev->struct_mutex);
2325
2326         intel_crtc_update_sarea_pos(crtc, x, y);
2327
2328         return 0;
2329 }
2330
2331 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332 {
2333         struct drm_device *dev = crtc->dev;
2334         struct drm_i915_private *dev_priv = dev->dev_private;
2335         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336         int pipe = intel_crtc->pipe;
2337         u32 reg, temp;
2338
2339         /* enable normal train */
2340         reg = FDI_TX_CTL(pipe);
2341         temp = I915_READ(reg);
2342         if (IS_IVYBRIDGE(dev)) {
2343                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2345         } else {
2346                 temp &= ~FDI_LINK_TRAIN_NONE;
2347                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2348         }
2349         I915_WRITE(reg, temp);
2350
2351         reg = FDI_RX_CTL(pipe);
2352         temp = I915_READ(reg);
2353         if (HAS_PCH_CPT(dev)) {
2354                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356         } else {
2357                 temp &= ~FDI_LINK_TRAIN_NONE;
2358                 temp |= FDI_LINK_TRAIN_NONE;
2359         }
2360         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362         /* wait one idle pattern time */
2363         POSTING_READ(reg);
2364         udelay(1000);
2365
2366         /* IVB wants error correction enabled */
2367         if (IS_IVYBRIDGE(dev))
2368                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369                            FDI_FE_ERRC_ENABLE);
2370 }
2371
2372 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373 {
2374         return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375 }
2376
2377 static void ivb_modeset_global_resources(struct drm_device *dev)
2378 {
2379         struct drm_i915_private *dev_priv = dev->dev_private;
2380         struct intel_crtc *pipe_B_crtc =
2381                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382         struct intel_crtc *pipe_C_crtc =
2383                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384         uint32_t temp;
2385
2386         /*
2387          * When everything is off disable fdi C so that we could enable fdi B
2388          * with all lanes. Note that we don't care about enabled pipes without
2389          * an enabled pch encoder.
2390          */
2391         if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392             !pipe_has_enabled_pch(pipe_C_crtc)) {
2393                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396                 temp = I915_READ(SOUTH_CHICKEN1);
2397                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399                 I915_WRITE(SOUTH_CHICKEN1, temp);
2400         }
2401 }
2402
2403 /* The FDI link training functions for ILK/Ibexpeak. */
2404 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405 {
2406         struct drm_device *dev = crtc->dev;
2407         struct drm_i915_private *dev_priv = dev->dev_private;
2408         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409         int pipe = intel_crtc->pipe;
2410         int plane = intel_crtc->plane;
2411         u32 reg, temp, tries;
2412
2413         /* FDI needs bits from pipe & plane first */
2414         assert_pipe_enabled(dev_priv, pipe);
2415         assert_plane_enabled(dev_priv, plane);
2416
2417         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418            for train result */
2419         reg = FDI_RX_IMR(pipe);
2420         temp = I915_READ(reg);
2421         temp &= ~FDI_RX_SYMBOL_LOCK;
2422         temp &= ~FDI_RX_BIT_LOCK;
2423         I915_WRITE(reg, temp);
2424         I915_READ(reg);
2425         udelay(150);
2426
2427         /* enable CPU FDI TX and PCH FDI RX */
2428         reg = FDI_TX_CTL(pipe);
2429         temp = I915_READ(reg);
2430         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2432         temp &= ~FDI_LINK_TRAIN_NONE;
2433         temp |= FDI_LINK_TRAIN_PATTERN_1;
2434         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2435
2436         reg = FDI_RX_CTL(pipe);
2437         temp = I915_READ(reg);
2438         temp &= ~FDI_LINK_TRAIN_NONE;
2439         temp |= FDI_LINK_TRAIN_PATTERN_1;
2440         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442         POSTING_READ(reg);
2443         udelay(150);
2444
2445         /* Ironlake workaround, enable clock pointer after FDI enable*/
2446         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448                    FDI_RX_PHASE_SYNC_POINTER_EN);
2449
2450         reg = FDI_RX_IIR(pipe);
2451         for (tries = 0; tries < 5; tries++) {
2452                 temp = I915_READ(reg);
2453                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455                 if ((temp & FDI_RX_BIT_LOCK)) {
2456                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2457                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2458                         break;
2459                 }
2460         }
2461         if (tries == 5)
2462                 DRM_ERROR("FDI train 1 fail!\n");
2463
2464         /* Train 2 */
2465         reg = FDI_TX_CTL(pipe);
2466         temp = I915_READ(reg);
2467         temp &= ~FDI_LINK_TRAIN_NONE;
2468         temp |= FDI_LINK_TRAIN_PATTERN_2;
2469         I915_WRITE(reg, temp);
2470
2471         reg = FDI_RX_CTL(pipe);
2472         temp = I915_READ(reg);
2473         temp &= ~FDI_LINK_TRAIN_NONE;
2474         temp |= FDI_LINK_TRAIN_PATTERN_2;
2475         I915_WRITE(reg, temp);
2476
2477         POSTING_READ(reg);
2478         udelay(150);
2479
2480         reg = FDI_RX_IIR(pipe);
2481         for (tries = 0; tries < 5; tries++) {
2482                 temp = I915_READ(reg);
2483                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485                 if (temp & FDI_RX_SYMBOL_LOCK) {
2486                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2487                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2488                         break;
2489                 }
2490         }
2491         if (tries == 5)
2492                 DRM_ERROR("FDI train 2 fail!\n");
2493
2494         DRM_DEBUG_KMS("FDI train done\n");
2495
2496 }
2497
2498 static const int snb_b_fdi_train_param[] = {
2499         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503 };
2504
2505 /* The FDI link training functions for SNB/Cougarpoint. */
2506 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507 {
2508         struct drm_device *dev = crtc->dev;
2509         struct drm_i915_private *dev_priv = dev->dev_private;
2510         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511         int pipe = intel_crtc->pipe;
2512         u32 reg, temp, i, retry;
2513
2514         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515            for train result */
2516         reg = FDI_RX_IMR(pipe);
2517         temp = I915_READ(reg);
2518         temp &= ~FDI_RX_SYMBOL_LOCK;
2519         temp &= ~FDI_RX_BIT_LOCK;
2520         I915_WRITE(reg, temp);
2521
2522         POSTING_READ(reg);
2523         udelay(150);
2524
2525         /* enable CPU FDI TX and PCH FDI RX */
2526         reg = FDI_TX_CTL(pipe);
2527         temp = I915_READ(reg);
2528         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2530         temp &= ~FDI_LINK_TRAIN_NONE;
2531         temp |= FDI_LINK_TRAIN_PATTERN_1;
2532         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533         /* SNB-B */
2534         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2535         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2536
2537         I915_WRITE(FDI_RX_MISC(pipe),
2538                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
2540         reg = FDI_RX_CTL(pipe);
2541         temp = I915_READ(reg);
2542         if (HAS_PCH_CPT(dev)) {
2543                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545         } else {
2546                 temp &= ~FDI_LINK_TRAIN_NONE;
2547                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548         }
2549         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551         POSTING_READ(reg);
2552         udelay(150);
2553
2554         for (i = 0; i < 4; i++) {
2555                 reg = FDI_TX_CTL(pipe);
2556                 temp = I915_READ(reg);
2557                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558                 temp |= snb_b_fdi_train_param[i];
2559                 I915_WRITE(reg, temp);
2560
2561                 POSTING_READ(reg);
2562                 udelay(500);
2563
2564                 for (retry = 0; retry < 5; retry++) {
2565                         reg = FDI_RX_IIR(pipe);
2566                         temp = I915_READ(reg);
2567                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568                         if (temp & FDI_RX_BIT_LOCK) {
2569                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571                                 break;
2572                         }
2573                         udelay(50);
2574                 }
2575                 if (retry < 5)
2576                         break;
2577         }
2578         if (i == 4)
2579                 DRM_ERROR("FDI train 1 fail!\n");
2580
2581         /* Train 2 */
2582         reg = FDI_TX_CTL(pipe);
2583         temp = I915_READ(reg);
2584         temp &= ~FDI_LINK_TRAIN_NONE;
2585         temp |= FDI_LINK_TRAIN_PATTERN_2;
2586         if (IS_GEN6(dev)) {
2587                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588                 /* SNB-B */
2589                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590         }
2591         I915_WRITE(reg, temp);
2592
2593         reg = FDI_RX_CTL(pipe);
2594         temp = I915_READ(reg);
2595         if (HAS_PCH_CPT(dev)) {
2596                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598         } else {
2599                 temp &= ~FDI_LINK_TRAIN_NONE;
2600                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601         }
2602         I915_WRITE(reg, temp);
2603
2604         POSTING_READ(reg);
2605         udelay(150);
2606
2607         for (i = 0; i < 4; i++) {
2608                 reg = FDI_TX_CTL(pipe);
2609                 temp = I915_READ(reg);
2610                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611                 temp |= snb_b_fdi_train_param[i];
2612                 I915_WRITE(reg, temp);
2613
2614                 POSTING_READ(reg);
2615                 udelay(500);
2616
2617                 for (retry = 0; retry < 5; retry++) {
2618                         reg = FDI_RX_IIR(pipe);
2619                         temp = I915_READ(reg);
2620                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621                         if (temp & FDI_RX_SYMBOL_LOCK) {
2622                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624                                 break;
2625                         }
2626                         udelay(50);
2627                 }
2628                 if (retry < 5)
2629                         break;
2630         }
2631         if (i == 4)
2632                 DRM_ERROR("FDI train 2 fail!\n");
2633
2634         DRM_DEBUG_KMS("FDI train done.\n");
2635 }
2636
2637 /* Manual link training for Ivy Bridge A0 parts */
2638 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639 {
2640         struct drm_device *dev = crtc->dev;
2641         struct drm_i915_private *dev_priv = dev->dev_private;
2642         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643         int pipe = intel_crtc->pipe;
2644         u32 reg, temp, i;
2645
2646         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647            for train result */
2648         reg = FDI_RX_IMR(pipe);
2649         temp = I915_READ(reg);
2650         temp &= ~FDI_RX_SYMBOL_LOCK;
2651         temp &= ~FDI_RX_BIT_LOCK;
2652         I915_WRITE(reg, temp);
2653
2654         POSTING_READ(reg);
2655         udelay(150);
2656
2657         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658                       I915_READ(FDI_RX_IIR(pipe)));
2659
2660         /* enable CPU FDI TX and PCH FDI RX */
2661         reg = FDI_TX_CTL(pipe);
2662         temp = I915_READ(reg);
2663         temp &= ~FDI_DP_PORT_WIDTH_MASK;
2664         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2665         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2667         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2668         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2669         temp |= FDI_COMPOSITE_SYNC;
2670         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2671
2672         I915_WRITE(FDI_RX_MISC(pipe),
2673                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2674
2675         reg = FDI_RX_CTL(pipe);
2676         temp = I915_READ(reg);
2677         temp &= ~FDI_LINK_TRAIN_AUTO;
2678         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2679         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2680         temp |= FDI_COMPOSITE_SYNC;
2681         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2682
2683         POSTING_READ(reg);
2684         udelay(150);
2685
2686         for (i = 0; i < 4; i++) {
2687                 reg = FDI_TX_CTL(pipe);
2688                 temp = I915_READ(reg);
2689                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690                 temp |= snb_b_fdi_train_param[i];
2691                 I915_WRITE(reg, temp);
2692
2693                 POSTING_READ(reg);
2694                 udelay(500);
2695
2696                 reg = FDI_RX_IIR(pipe);
2697                 temp = I915_READ(reg);
2698                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700                 if (temp & FDI_RX_BIT_LOCK ||
2701                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2702                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2703                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2704                         break;
2705                 }
2706         }
2707         if (i == 4)
2708                 DRM_ERROR("FDI train 1 fail!\n");
2709
2710         /* Train 2 */
2711         reg = FDI_TX_CTL(pipe);
2712         temp = I915_READ(reg);
2713         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2714         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2715         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2716         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2717         I915_WRITE(reg, temp);
2718
2719         reg = FDI_RX_CTL(pipe);
2720         temp = I915_READ(reg);
2721         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2722         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2723         I915_WRITE(reg, temp);
2724
2725         POSTING_READ(reg);
2726         udelay(150);
2727
2728         for (i = 0; i < 4; i++) {
2729                 reg = FDI_TX_CTL(pipe);
2730                 temp = I915_READ(reg);
2731                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732                 temp |= snb_b_fdi_train_param[i];
2733                 I915_WRITE(reg, temp);
2734
2735                 POSTING_READ(reg);
2736                 udelay(500);
2737
2738                 reg = FDI_RX_IIR(pipe);
2739                 temp = I915_READ(reg);
2740                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2741
2742                 if (temp & FDI_RX_SYMBOL_LOCK) {
2743                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2744                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2745                         break;
2746                 }
2747         }
2748         if (i == 4)
2749                 DRM_ERROR("FDI train 2 fail!\n");
2750
2751         DRM_DEBUG_KMS("FDI train done.\n");
2752 }
2753
2754 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2755 {
2756         struct drm_device *dev = intel_crtc->base.dev;
2757         struct drm_i915_private *dev_priv = dev->dev_private;
2758         int pipe = intel_crtc->pipe;
2759         u32 reg, temp;
2760
2761
2762         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2763         reg = FDI_RX_CTL(pipe);
2764         temp = I915_READ(reg);
2765         temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2766         temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2767         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2768         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2769
2770         POSTING_READ(reg);
2771         udelay(200);
2772
2773         /* Switch from Rawclk to PCDclk */
2774         temp = I915_READ(reg);
2775         I915_WRITE(reg, temp | FDI_PCDCLK);
2776
2777         POSTING_READ(reg);
2778         udelay(200);
2779
2780         /* Enable CPU FDI TX PLL, always on for Ironlake */
2781         reg = FDI_TX_CTL(pipe);
2782         temp = I915_READ(reg);
2783         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2784                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2785
2786                 POSTING_READ(reg);
2787                 udelay(100);
2788         }
2789 }
2790
2791 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2792 {
2793         struct drm_device *dev = intel_crtc->base.dev;
2794         struct drm_i915_private *dev_priv = dev->dev_private;
2795         int pipe = intel_crtc->pipe;
2796         u32 reg, temp;
2797
2798         /* Switch from PCDclk to Rawclk */
2799         reg = FDI_RX_CTL(pipe);
2800         temp = I915_READ(reg);
2801         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2802
2803         /* Disable CPU FDI TX PLL */
2804         reg = FDI_TX_CTL(pipe);
2805         temp = I915_READ(reg);
2806         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2807
2808         POSTING_READ(reg);
2809         udelay(100);
2810
2811         reg = FDI_RX_CTL(pipe);
2812         temp = I915_READ(reg);
2813         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2814
2815         /* Wait for the clocks to turn off. */
2816         POSTING_READ(reg);
2817         udelay(100);
2818 }
2819
2820 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2821 {
2822         struct drm_device *dev = crtc->dev;
2823         struct drm_i915_private *dev_priv = dev->dev_private;
2824         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825         int pipe = intel_crtc->pipe;
2826         u32 reg, temp;
2827
2828         /* disable CPU FDI tx and PCH FDI rx */
2829         reg = FDI_TX_CTL(pipe);
2830         temp = I915_READ(reg);
2831         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2832         POSTING_READ(reg);
2833
2834         reg = FDI_RX_CTL(pipe);
2835         temp = I915_READ(reg);
2836         temp &= ~(0x7 << 16);
2837         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2838         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2839
2840         POSTING_READ(reg);
2841         udelay(100);
2842
2843         /* Ironlake workaround, disable clock pointer after downing FDI */
2844         if (HAS_PCH_IBX(dev)) {
2845                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2846         }
2847
2848         /* still set train pattern 1 */
2849         reg = FDI_TX_CTL(pipe);
2850         temp = I915_READ(reg);
2851         temp &= ~FDI_LINK_TRAIN_NONE;
2852         temp |= FDI_LINK_TRAIN_PATTERN_1;
2853         I915_WRITE(reg, temp);
2854
2855         reg = FDI_RX_CTL(pipe);
2856         temp = I915_READ(reg);
2857         if (HAS_PCH_CPT(dev)) {
2858                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2859                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2860         } else {
2861                 temp &= ~FDI_LINK_TRAIN_NONE;
2862                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2863         }
2864         /* BPC in FDI rx is consistent with that in PIPECONF */
2865         temp &= ~(0x07 << 16);
2866         temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2867         I915_WRITE(reg, temp);
2868
2869         POSTING_READ(reg);
2870         udelay(100);
2871 }
2872
2873 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2874 {
2875         struct drm_device *dev = crtc->dev;
2876         struct drm_i915_private *dev_priv = dev->dev_private;
2877         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2878         unsigned long flags;
2879         bool pending;
2880
2881         if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2882             intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2883                 return false;
2884
2885         spin_lock_irqsave(&dev->event_lock, flags);
2886         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2887         spin_unlock_irqrestore(&dev->event_lock, flags);
2888
2889         return pending;
2890 }
2891
2892 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2893 {
2894         struct drm_device *dev = crtc->dev;
2895         struct drm_i915_private *dev_priv = dev->dev_private;
2896
2897         if (crtc->fb == NULL)
2898                 return;
2899
2900         WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2901
2902         wait_event(dev_priv->pending_flip_queue,
2903                    !intel_crtc_has_pending_flip(crtc));
2904
2905         mutex_lock(&dev->struct_mutex);
2906         intel_finish_fb(crtc->fb);
2907         mutex_unlock(&dev->struct_mutex);
2908 }
2909
2910 /* Program iCLKIP clock to the desired frequency */
2911 static void lpt_program_iclkip(struct drm_crtc *crtc)
2912 {
2913         struct drm_device *dev = crtc->dev;
2914         struct drm_i915_private *dev_priv = dev->dev_private;
2915         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2916         u32 temp;
2917
2918         mutex_lock(&dev_priv->dpio_lock);
2919
2920         /* It is necessary to ungate the pixclk gate prior to programming
2921          * the divisors, and gate it back when it is done.
2922          */
2923         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2924
2925         /* Disable SSCCTL */
2926         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2927                         intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2928                                 SBI_SSCCTL_DISABLE,
2929                         SBI_ICLK);
2930
2931         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2932         if (crtc->mode.clock == 20000) {
2933                 auxdiv = 1;
2934                 divsel = 0x41;
2935                 phaseinc = 0x20;
2936         } else {
2937                 /* The iCLK virtual clock root frequency is in MHz,
2938                  * but the crtc->mode.clock in in KHz. To get the divisors,
2939                  * it is necessary to divide one by another, so we
2940                  * convert the virtual clock precision to KHz here for higher
2941                  * precision.
2942                  */
2943                 u32 iclk_virtual_root_freq = 172800 * 1000;
2944                 u32 iclk_pi_range = 64;
2945                 u32 desired_divisor, msb_divisor_value, pi_value;
2946
2947                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2948                 msb_divisor_value = desired_divisor / iclk_pi_range;
2949                 pi_value = desired_divisor % iclk_pi_range;
2950
2951                 auxdiv = 0;
2952                 divsel = msb_divisor_value - 2;
2953                 phaseinc = pi_value;
2954         }
2955
2956         /* This should not happen with any sane values */
2957         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2958                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2959         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2960                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2961
2962         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2963                         crtc->mode.clock,
2964                         auxdiv,
2965                         divsel,
2966                         phasedir,
2967                         phaseinc);
2968
2969         /* Program SSCDIVINTPHASE6 */
2970         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2971         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2972         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2973         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2974         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2975         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2976         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2977         intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2978
2979         /* Program SSCAUXDIV */
2980         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2981         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2982         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2983         intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2984
2985         /* Enable modulator and associated divider */
2986         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2987         temp &= ~SBI_SSCCTL_DISABLE;
2988         intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2989
2990         /* Wait for initialization time */
2991         udelay(24);
2992
2993         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2994
2995         mutex_unlock(&dev_priv->dpio_lock);
2996 }
2997
2998 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2999                                                 enum pipe pch_transcoder)
3000 {
3001         struct drm_device *dev = crtc->base.dev;
3002         struct drm_i915_private *dev_priv = dev->dev_private;
3003         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3004
3005         I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3006                    I915_READ(HTOTAL(cpu_transcoder)));
3007         I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3008                    I915_READ(HBLANK(cpu_transcoder)));
3009         I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3010                    I915_READ(HSYNC(cpu_transcoder)));
3011
3012         I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3013                    I915_READ(VTOTAL(cpu_transcoder)));
3014         I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3015                    I915_READ(VBLANK(cpu_transcoder)));
3016         I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3017                    I915_READ(VSYNC(cpu_transcoder)));
3018         I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3019                    I915_READ(VSYNCSHIFT(cpu_transcoder)));
3020 }
3021
3022 /*
3023  * Enable PCH resources required for PCH ports:
3024  *   - PCH PLLs
3025  *   - FDI training & RX/TX
3026  *   - update transcoder timings
3027  *   - DP transcoding bits
3028  *   - transcoder
3029  */
3030 static void ironlake_pch_enable(struct drm_crtc *crtc)
3031 {
3032         struct drm_device *dev = crtc->dev;
3033         struct drm_i915_private *dev_priv = dev->dev_private;
3034         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3035         int pipe = intel_crtc->pipe;
3036         u32 reg, temp;
3037
3038         assert_pch_transcoder_disabled(dev_priv, pipe);
3039
3040         /* Write the TU size bits before fdi link training, so that error
3041          * detection works. */
3042         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3043                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3044
3045         /* For PCH output, training FDI link */
3046         dev_priv->display.fdi_link_train(crtc);
3047
3048         /* XXX: pch pll's can be enabled any time before we enable the PCH
3049          * transcoder, and we actually should do this to not upset any PCH
3050          * transcoder that already use the clock when we share it.
3051          *
3052          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3053          * unconditionally resets the pll - we need that to have the right LVDS
3054          * enable sequence. */
3055         ironlake_enable_pch_pll(intel_crtc);
3056
3057         if (HAS_PCH_CPT(dev)) {
3058                 u32 sel;
3059
3060                 temp = I915_READ(PCH_DPLL_SEL);
3061                 switch (pipe) {
3062                 default:
3063                 case 0:
3064                         temp |= TRANSA_DPLL_ENABLE;
3065                         sel = TRANSA_DPLLB_SEL;
3066                         break;
3067                 case 1:
3068                         temp |= TRANSB_DPLL_ENABLE;
3069                         sel = TRANSB_DPLLB_SEL;
3070                         break;
3071                 case 2:
3072                         temp |= TRANSC_DPLL_ENABLE;
3073                         sel = TRANSC_DPLLB_SEL;
3074                         break;
3075                 }
3076                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3077                         temp |= sel;
3078                 else
3079                         temp &= ~sel;
3080                 I915_WRITE(PCH_DPLL_SEL, temp);
3081         }
3082
3083         /* set transcoder timing, panel must allow it */
3084         assert_panel_unlocked(dev_priv, pipe);
3085         ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3086
3087         intel_fdi_normal_train(crtc);
3088
3089         /* For PCH DP, enable TRANS_DP_CTL */
3090         if (HAS_PCH_CPT(dev) &&
3091             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3092              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3093                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3094                 reg = TRANS_DP_CTL(pipe);
3095                 temp = I915_READ(reg);
3096                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3097                           TRANS_DP_SYNC_MASK |
3098                           TRANS_DP_BPC_MASK);
3099                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3100                          TRANS_DP_ENH_FRAMING);
3101                 temp |= bpc << 9; /* same format but at 11:9 */
3102
3103                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3104                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3105                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3106                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3107
3108                 switch (intel_trans_dp_port_sel(crtc)) {
3109                 case PCH_DP_B:
3110                         temp |= TRANS_DP_PORT_SEL_B;
3111                         break;
3112                 case PCH_DP_C:
3113                         temp |= TRANS_DP_PORT_SEL_C;
3114                         break;
3115                 case PCH_DP_D:
3116                         temp |= TRANS_DP_PORT_SEL_D;
3117                         break;
3118                 default:
3119                         BUG();
3120                 }
3121
3122                 I915_WRITE(reg, temp);
3123         }
3124
3125         ironlake_enable_pch_transcoder(dev_priv, pipe);
3126 }
3127
3128 static void lpt_pch_enable(struct drm_crtc *crtc)
3129 {
3130         struct drm_device *dev = crtc->dev;
3131         struct drm_i915_private *dev_priv = dev->dev_private;
3132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3133         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3134
3135         assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3136
3137         lpt_program_iclkip(crtc);
3138
3139         /* Set transcoder timing. */
3140         ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3141
3142         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3143 }
3144
3145 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3146 {
3147         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3148
3149         if (pll == NULL)
3150                 return;
3151
3152         if (pll->refcount == 0) {
3153                 WARN(1, "bad PCH PLL refcount\n");
3154                 return;
3155         }
3156
3157         --pll->refcount;
3158         intel_crtc->pch_pll = NULL;
3159 }
3160
3161 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3162 {
3163         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3164         struct intel_pch_pll *pll;
3165         int i;
3166
3167         pll = intel_crtc->pch_pll;
3168         if (pll) {
3169                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3170                               intel_crtc->base.base.id, pll->pll_reg);
3171                 goto prepare;
3172         }
3173
3174         if (HAS_PCH_IBX(dev_priv->dev)) {
3175                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3176                 i = intel_crtc->pipe;
3177                 pll = &dev_priv->pch_plls[i];
3178
3179                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3180                               intel_crtc->base.base.id, pll->pll_reg);
3181
3182                 goto found;
3183         }
3184
3185         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3186                 pll = &dev_priv->pch_plls[i];
3187
3188                 /* Only want to check enabled timings first */
3189                 if (pll->refcount == 0)
3190                         continue;
3191
3192                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3193                     fp == I915_READ(pll->fp0_reg)) {
3194                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3195                                       intel_crtc->base.base.id,
3196                                       pll->pll_reg, pll->refcount, pll->active);
3197
3198                         goto found;
3199                 }
3200         }
3201
3202         /* Ok no matching timings, maybe there's a free one? */
3203         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3204                 pll = &dev_priv->pch_plls[i];
3205                 if (pll->refcount == 0) {
3206                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3207                                       intel_crtc->base.base.id, pll->pll_reg);
3208                         goto found;
3209                 }
3210         }
3211
3212         return NULL;
3213
3214 found:
3215         intel_crtc->pch_pll = pll;
3216         pll->refcount++;
3217         DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
3218 prepare: /* separate function? */
3219         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3220
3221         /* Wait for the clocks to stabilize before rewriting the regs */
3222         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3223         POSTING_READ(pll->pll_reg);
3224         udelay(150);
3225
3226         I915_WRITE(pll->fp0_reg, fp);
3227         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3228         pll->on = false;
3229         return pll;
3230 }
3231
3232 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3233 {
3234         struct drm_i915_private *dev_priv = dev->dev_private;
3235         int dslreg = PIPEDSL(pipe);
3236         u32 temp;
3237
3238         temp = I915_READ(dslreg);
3239         udelay(500);
3240         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3241                 if (wait_for(I915_READ(dslreg) != temp, 5))
3242                         DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3243         }
3244 }
3245
3246 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3247 {
3248         struct drm_device *dev = crtc->base.dev;
3249         struct drm_i915_private *dev_priv = dev->dev_private;
3250         int pipe = crtc->pipe;
3251
3252         if (crtc->config.pch_pfit.size &&
3253             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
3254                 /* Force use of hard-coded filter coefficients
3255                  * as some pre-programmed values are broken,
3256                  * e.g. x201.
3257                  */
3258                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3259                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3260                                                  PF_PIPE_SEL_IVB(pipe));
3261                 else
3262                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3263                 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3264                 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3265         }
3266 }
3267
3268 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3269 {
3270         struct drm_device *dev = crtc->dev;
3271         struct drm_i915_private *dev_priv = dev->dev_private;
3272         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3273         struct intel_encoder *encoder;
3274         int pipe = intel_crtc->pipe;
3275         int plane = intel_crtc->plane;
3276         u32 temp;
3277
3278         WARN_ON(!crtc->enabled);
3279
3280         if (intel_crtc->active)
3281                 return;
3282
3283         intel_crtc->active = true;
3284
3285         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3286         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3287
3288         intel_update_watermarks(dev);
3289
3290         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3291                 temp = I915_READ(PCH_LVDS);
3292                 if ((temp & LVDS_PORT_EN) == 0)
3293                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3294         }
3295
3296
3297         if (intel_crtc->config.has_pch_encoder) {
3298                 /* Note: FDI PLL enabling _must_ be done before we enable the
3299                  * cpu pipes, hence this is separate from all the other fdi/pch
3300                  * enabling. */
3301                 ironlake_fdi_pll_enable(intel_crtc);
3302         } else {
3303                 assert_fdi_tx_disabled(dev_priv, pipe);
3304                 assert_fdi_rx_disabled(dev_priv, pipe);
3305         }
3306
3307         for_each_encoder_on_crtc(dev, crtc, encoder)
3308                 if (encoder->pre_enable)
3309                         encoder->pre_enable(encoder);
3310
3311         /* Enable panel fitting for LVDS */
3312         ironlake_pfit_enable(intel_crtc);
3313
3314         /*
3315          * On ILK+ LUT must be loaded before the pipe is running but with
3316          * clocks enabled
3317          */
3318         intel_crtc_load_lut(crtc);
3319
3320         intel_enable_pipe(dev_priv, pipe,
3321                           intel_crtc->config.has_pch_encoder);
3322         intel_enable_plane(dev_priv, plane, pipe);
3323
3324         if (intel_crtc->config.has_pch_encoder)
3325                 ironlake_pch_enable(crtc);
3326
3327         mutex_lock(&dev->struct_mutex);
3328         intel_update_fbc(dev);
3329         mutex_unlock(&dev->struct_mutex);
3330
3331         intel_crtc_update_cursor(crtc, true);
3332
3333         for_each_encoder_on_crtc(dev, crtc, encoder)
3334                 encoder->enable(encoder);
3335
3336         if (HAS_PCH_CPT(dev))
3337                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3338
3339         /*
3340          * There seems to be a race in PCH platform hw (at least on some
3341          * outputs) where an enabled pipe still completes any pageflip right
3342          * away (as if the pipe is off) instead of waiting for vblank. As soon
3343          * as the first vblank happend, everything works as expected. Hence just
3344          * wait for one vblank before returning to avoid strange things
3345          * happening.
3346          */
3347         intel_wait_for_vblank(dev, intel_crtc->pipe);
3348 }
3349
3350 static void haswell_crtc_enable(struct drm_crtc *crtc)
3351 {
3352         struct drm_device *dev = crtc->dev;
3353         struct drm_i915_private *dev_priv = dev->dev_private;
3354         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3355         struct intel_encoder *encoder;
3356         int pipe = intel_crtc->pipe;
3357         int plane = intel_crtc->plane;
3358
3359         WARN_ON(!crtc->enabled);
3360
3361         if (intel_crtc->active)
3362                 return;
3363
3364         intel_crtc->active = true;
3365
3366         intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3367         if (intel_crtc->config.has_pch_encoder)
3368                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3369
3370         intel_update_watermarks(dev);
3371
3372         if (intel_crtc->config.has_pch_encoder)
3373                 dev_priv->display.fdi_link_train(crtc);
3374
3375         for_each_encoder_on_crtc(dev, crtc, encoder)
3376                 if (encoder->pre_enable)
3377                         encoder->pre_enable(encoder);
3378
3379         intel_ddi_enable_pipe_clock(intel_crtc);
3380
3381         /* Enable panel fitting for eDP */
3382         ironlake_pfit_enable(intel_crtc);
3383
3384         /*
3385          * On ILK+ LUT must be loaded before the pipe is running but with
3386          * clocks enabled
3387          */
3388         intel_crtc_load_lut(crtc);
3389
3390         intel_ddi_set_pipe_settings(crtc);
3391         intel_ddi_enable_transcoder_func(crtc);
3392
3393         intel_enable_pipe(dev_priv, pipe,
3394                           intel_crtc->config.has_pch_encoder);
3395         intel_enable_plane(dev_priv, plane, pipe);
3396
3397         if (intel_crtc->config.has_pch_encoder)
3398                 lpt_pch_enable(crtc);
3399
3400         mutex_lock(&dev->struct_mutex);
3401         intel_update_fbc(dev);
3402         mutex_unlock(&dev->struct_mutex);
3403
3404         intel_crtc_update_cursor(crtc, true);
3405
3406         for_each_encoder_on_crtc(dev, crtc, encoder)
3407                 encoder->enable(encoder);
3408
3409         /*
3410          * There seems to be a race in PCH platform hw (at least on some
3411          * outputs) where an enabled pipe still completes any pageflip right
3412          * away (as if the pipe is off) instead of waiting for vblank. As soon
3413          * as the first vblank happend, everything works as expected. Hence just
3414          * wait for one vblank before returning to avoid strange things
3415          * happening.
3416          */
3417         intel_wait_for_vblank(dev, intel_crtc->pipe);
3418 }
3419
3420 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3421 {
3422         struct drm_device *dev = crtc->dev;
3423         struct drm_i915_private *dev_priv = dev->dev_private;
3424         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3425         struct intel_encoder *encoder;
3426         int pipe = intel_crtc->pipe;
3427         int plane = intel_crtc->plane;
3428         u32 reg, temp;
3429
3430
3431         if (!intel_crtc->active)
3432                 return;
3433
3434         for_each_encoder_on_crtc(dev, crtc, encoder)
3435                 encoder->disable(encoder);
3436
3437         intel_crtc_wait_for_pending_flips(crtc);
3438         drm_vblank_off(dev, pipe);
3439         intel_crtc_update_cursor(crtc, false);
3440
3441         intel_disable_plane(dev_priv, plane, pipe);
3442
3443         if (dev_priv->cfb_plane == plane)
3444                 intel_disable_fbc(dev);
3445
3446         intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3447         intel_disable_pipe(dev_priv, pipe);
3448
3449         /* Disable PF */
3450         I915_WRITE(PF_CTL(pipe), 0);
3451         I915_WRITE(PF_WIN_SZ(pipe), 0);
3452
3453         for_each_encoder_on_crtc(dev, crtc, encoder)
3454                 if (encoder->post_disable)
3455                         encoder->post_disable(encoder);
3456
3457         ironlake_fdi_disable(crtc);
3458
3459         ironlake_disable_pch_transcoder(dev_priv, pipe);
3460         intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3461
3462         if (HAS_PCH_CPT(dev)) {
3463                 /* disable TRANS_DP_CTL */
3464                 reg = TRANS_DP_CTL(pipe);
3465                 temp = I915_READ(reg);
3466                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3467                 temp |= TRANS_DP_PORT_SEL_NONE;
3468                 I915_WRITE(reg, temp);
3469
3470                 /* disable DPLL_SEL */
3471                 temp = I915_READ(PCH_DPLL_SEL);
3472                 switch (pipe) {
3473                 case 0:
3474                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3475                         break;
3476                 case 1:
3477                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3478                         break;
3479                 case 2:
3480                         /* C shares PLL A or B */
3481                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3482                         break;
3483                 default:
3484                         BUG(); /* wtf */
3485                 }
3486                 I915_WRITE(PCH_DPLL_SEL, temp);
3487         }
3488
3489         /* disable PCH DPLL */
3490         intel_disable_pch_pll(intel_crtc);
3491
3492         ironlake_fdi_pll_disable(intel_crtc);
3493
3494         intel_crtc->active = false;
3495         intel_update_watermarks(dev);
3496
3497         mutex_lock(&dev->struct_mutex);
3498         intel_update_fbc(dev);
3499         mutex_unlock(&dev->struct_mutex);
3500 }
3501
3502 static void haswell_crtc_disable(struct drm_crtc *crtc)
3503 {
3504         struct drm_device *dev = crtc->dev;
3505         struct drm_i915_private *dev_priv = dev->dev_private;
3506         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507         struct intel_encoder *encoder;
3508         int pipe = intel_crtc->pipe;
3509         int plane = intel_crtc->plane;
3510         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3511
3512         if (!intel_crtc->active)
3513                 return;
3514
3515         for_each_encoder_on_crtc(dev, crtc, encoder)
3516                 encoder->disable(encoder);
3517
3518         intel_crtc_wait_for_pending_flips(crtc);
3519         drm_vblank_off(dev, pipe);
3520         intel_crtc_update_cursor(crtc, false);
3521
3522         intel_disable_plane(dev_priv, plane, pipe);
3523
3524         if (dev_priv->cfb_plane == plane)
3525                 intel_disable_fbc(dev);
3526
3527         if (intel_crtc->config.has_pch_encoder)
3528                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3529         intel_disable_pipe(dev_priv, pipe);
3530
3531         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3532
3533         /* XXX: Once we have proper panel fitter state tracking implemented with
3534          * hardware state read/check support we should switch to only disable
3535          * the panel fitter when we know it's used. */
3536         if (intel_using_power_well(dev)) {
3537                 I915_WRITE(PF_CTL(pipe), 0);
3538                 I915_WRITE(PF_WIN_SZ(pipe), 0);
3539         }
3540
3541         intel_ddi_disable_pipe_clock(intel_crtc);
3542
3543         for_each_encoder_on_crtc(dev, crtc, encoder)
3544                 if (encoder->post_disable)
3545                         encoder->post_disable(encoder);
3546
3547         if (intel_crtc->config.has_pch_encoder) {
3548                 lpt_disable_pch_transcoder(dev_priv);
3549                 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3550                 intel_ddi_fdi_disable(crtc);
3551         }
3552
3553         intel_crtc->active = false;
3554         intel_update_watermarks(dev);
3555
3556         mutex_lock(&dev->struct_mutex);
3557         intel_update_fbc(dev);
3558         mutex_unlock(&dev->struct_mutex);
3559 }
3560
3561 static void ironlake_crtc_off(struct drm_crtc *crtc)
3562 {
3563         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3564         intel_put_pch_pll(intel_crtc);
3565 }
3566
3567 static void haswell_crtc_off(struct drm_crtc *crtc)
3568 {
3569         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3570
3571         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3572          * start using it. */
3573         intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
3574
3575         intel_ddi_put_crtc_pll(crtc);
3576 }
3577
3578 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3579 {
3580         if (!enable && intel_crtc->overlay) {
3581                 struct drm_device *dev = intel_crtc->base.dev;
3582                 struct drm_i915_private *dev_priv = dev->dev_private;
3583
3584                 mutex_lock(&dev->struct_mutex);
3585                 dev_priv->mm.interruptible = false;
3586                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3587                 dev_priv->mm.interruptible = true;
3588                 mutex_unlock(&dev->struct_mutex);
3589         }
3590
3591         /* Let userspace switch the overlay on again. In most cases userspace
3592          * has to recompute where to put it anyway.
3593          */
3594 }
3595
3596 /**
3597  * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3598  * cursor plane briefly if not already running after enabling the display
3599  * plane.
3600  * This workaround avoids occasional blank screens when self refresh is
3601  * enabled.
3602  */
3603 static void
3604 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3605 {
3606         u32 cntl = I915_READ(CURCNTR(pipe));
3607
3608         if ((cntl & CURSOR_MODE) == 0) {
3609                 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3610
3611                 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3612                 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3613                 intel_wait_for_vblank(dev_priv->dev, pipe);
3614                 I915_WRITE(CURCNTR(pipe), cntl);
3615                 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3616                 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3617         }
3618 }
3619
3620 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3621 {
3622         struct drm_device *dev = crtc->base.dev;
3623         struct drm_i915_private *dev_priv = dev->dev_private;
3624         struct intel_crtc_config *pipe_config = &crtc->config;
3625
3626         if (!(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
3627               intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)))
3628                 return;
3629
3630         WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3631         assert_pipe_disabled(dev_priv, crtc->pipe);
3632
3633         /*
3634          * Enable automatic panel scaling so that non-native modes
3635          * fill the screen.  The panel fitter should only be
3636          * adjusted whilst the pipe is disabled, according to
3637          * register description and PRM.
3638          */
3639         DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
3640                       pipe_config->gmch_pfit.control,
3641                       pipe_config->gmch_pfit.pgm_ratios);
3642
3643         I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3644         I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3645
3646         /* Border color in case we don't scale up to the full screen. Black by
3647          * default, change to something else for debugging. */
3648         I915_WRITE(BCLRPAT(crtc->pipe), 0);
3649 }
3650
3651 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3652 {
3653         struct drm_device *dev = crtc->dev;
3654         struct drm_i915_private *dev_priv = dev->dev_private;
3655         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3656         struct intel_encoder *encoder;
3657         int pipe = intel_crtc->pipe;
3658         int plane = intel_crtc->plane;
3659
3660         WARN_ON(!crtc->enabled);
3661
3662         if (intel_crtc->active)
3663                 return;
3664
3665         intel_crtc->active = true;
3666         intel_update_watermarks(dev);
3667
3668         mutex_lock(&dev_priv->dpio_lock);
3669
3670         for_each_encoder_on_crtc(dev, crtc, encoder)
3671                 if (encoder->pre_pll_enable)
3672                         encoder->pre_pll_enable(encoder);
3673
3674         intel_enable_pll(dev_priv, pipe);
3675
3676         for_each_encoder_on_crtc(dev, crtc, encoder)
3677                 if (encoder->pre_enable)
3678                         encoder->pre_enable(encoder);
3679
3680         /* VLV wants encoder enabling _before_ the pipe is up. */
3681         for_each_encoder_on_crtc(dev, crtc, encoder)
3682                 encoder->enable(encoder);
3683
3684         /* Enable panel fitting for eDP */
3685         i9xx_pfit_enable(intel_crtc);
3686
3687         intel_enable_pipe(dev_priv, pipe, false);
3688         intel_enable_plane(dev_priv, plane, pipe);
3689
3690         intel_crtc_load_lut(crtc);
3691         intel_update_fbc(dev);
3692
3693         /* Give the overlay scaler a chance to enable if it's on this pipe */
3694         intel_crtc_dpms_overlay(intel_crtc, true);
3695         intel_crtc_update_cursor(crtc, true);
3696
3697         mutex_unlock(&dev_priv->dpio_lock);
3698 }
3699
3700 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3701 {
3702         struct drm_device *dev = crtc->dev;
3703         struct drm_i915_private *dev_priv = dev->dev_private;
3704         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3705         struct intel_encoder *encoder;
3706         int pipe = intel_crtc->pipe;
3707         int plane = intel_crtc->plane;
3708
3709         WARN_ON(!crtc->enabled);
3710
3711         if (intel_crtc->active)
3712                 return;
3713
3714         intel_crtc->active = true;
3715         intel_update_watermarks(dev);
3716
3717         intel_enable_pll(dev_priv, pipe);
3718
3719         for_each_encoder_on_crtc(dev, crtc, encoder)
3720                 if (encoder->pre_enable)
3721                         encoder->pre_enable(encoder);
3722
3723         /* Enable panel fitting for LVDS */
3724         i9xx_pfit_enable(intel_crtc);
3725
3726         intel_enable_pipe(dev_priv, pipe, false);
3727         intel_enable_plane(dev_priv, plane, pipe);
3728         if (IS_G4X(dev))
3729                 g4x_fixup_plane(dev_priv, pipe);
3730
3731         intel_crtc_load_lut(crtc);
3732         intel_update_fbc(dev);
3733
3734         /* Give the overlay scaler a chance to enable if it's on this pipe */
3735         intel_crtc_dpms_overlay(intel_crtc, true);
3736         intel_crtc_update_cursor(crtc, true);
3737
3738         for_each_encoder_on_crtc(dev, crtc, encoder)
3739                 encoder->enable(encoder);
3740 }
3741
3742 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3743 {
3744         struct drm_device *dev = crtc->base.dev;
3745         struct drm_i915_private *dev_priv = dev->dev_private;
3746         enum pipe pipe;
3747         uint32_t pctl = I915_READ(PFIT_CONTROL);
3748
3749         assert_pipe_disabled(dev_priv, crtc->pipe);
3750
3751         if (INTEL_INFO(dev)->gen >= 4)
3752                 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3753         else
3754                 pipe = PIPE_B;
3755
3756         if (pipe == crtc->pipe) {
3757                 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3758                 I915_WRITE(PFIT_CONTROL, 0);
3759         }
3760 }
3761
3762 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3763 {
3764         struct drm_device *dev = crtc->dev;
3765         struct drm_i915_private *dev_priv = dev->dev_private;
3766         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3767         struct intel_encoder *encoder;
3768         int pipe = intel_crtc->pipe;
3769         int plane = intel_crtc->plane;
3770
3771         if (!intel_crtc->active)
3772                 return;
3773
3774         for_each_encoder_on_crtc(dev, crtc, encoder)
3775                 encoder->disable(encoder);
3776
3777         /* Give the overlay scaler a chance to disable if it's on this pipe */
3778         intel_crtc_wait_for_pending_flips(crtc);
3779         drm_vblank_off(dev, pipe);
3780         intel_crtc_dpms_overlay(intel_crtc, false);
3781         intel_crtc_update_cursor(crtc, false);
3782
3783         if (dev_priv->cfb_plane == plane)
3784                 intel_disable_fbc(dev);
3785
3786         intel_disable_plane(dev_priv, plane, pipe);
3787         intel_disable_pipe(dev_priv, pipe);
3788
3789         i9xx_pfit_disable(intel_crtc);
3790
3791         for_each_encoder_on_crtc(dev, crtc, encoder)
3792                 if (encoder->post_disable)
3793                         encoder->post_disable(encoder);
3794
3795         intel_disable_pll(dev_priv, pipe);
3796
3797         intel_crtc->active = false;
3798         intel_update_fbc(dev);
3799         intel_update_watermarks(dev);
3800 }
3801
3802 static void i9xx_crtc_off(struct drm_crtc *crtc)
3803 {
3804 }
3805
3806 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3807                                     bool enabled)
3808 {
3809         struct drm_device *dev = crtc->dev;
3810         struct drm_i915_master_private *master_priv;
3811         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3812         int pipe = intel_crtc->pipe;
3813
3814         if (!dev->primary->master)
3815                 return;
3816
3817         master_priv = dev->primary->master->driver_priv;
3818         if (!master_priv->sarea_priv)
3819                 return;
3820
3821         switch (pipe) {
3822         case 0:
3823                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3824                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3825                 break;
3826         case 1:
3827                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3828                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3829                 break;
3830         default:
3831                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3832                 break;
3833         }
3834 }
3835
3836 /**
3837  * Sets the power management mode of the pipe and plane.
3838  */
3839 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3840 {
3841         struct drm_device *dev = crtc->dev;
3842         struct drm_i915_private *dev_priv = dev->dev_private;
3843         struct intel_encoder *intel_encoder;
3844         bool enable = false;
3845
3846         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3847                 enable |= intel_encoder->connectors_active;
3848
3849         if (enable)
3850                 dev_priv->display.crtc_enable(crtc);
3851         else
3852                 dev_priv->display.crtc_disable(crtc);
3853
3854         intel_crtc_update_sarea(crtc, enable);
3855 }
3856
3857 static void intel_crtc_disable(struct drm_crtc *crtc)
3858 {
3859         struct drm_device *dev = crtc->dev;
3860         struct drm_connector *connector;
3861         struct drm_i915_private *dev_priv = dev->dev_private;
3862         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3863
3864         /* crtc should still be enabled when we disable it. */
3865         WARN_ON(!crtc->enabled);
3866
3867         intel_crtc->eld_vld = false;
3868         dev_priv->display.crtc_disable(crtc);
3869         intel_crtc_update_sarea(crtc, false);
3870         dev_priv->display.off(crtc);
3871
3872         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3873         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3874
3875         if (crtc->fb) {
3876                 mutex_lock(&dev->struct_mutex);
3877                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3878                 mutex_unlock(&dev->struct_mutex);
3879                 crtc->fb = NULL;
3880         }
3881
3882         /* Update computed state. */
3883         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3884                 if (!connector->encoder || !connector->encoder->crtc)
3885                         continue;
3886
3887                 if (connector->encoder->crtc != crtc)
3888                         continue;
3889
3890                 connector->dpms = DRM_MODE_DPMS_OFF;
3891                 to_intel_encoder(connector->encoder)->connectors_active = false;
3892         }
3893 }
3894
3895 void intel_modeset_disable(struct drm_device *dev)
3896 {
3897         struct drm_crtc *crtc;
3898
3899         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3900                 if (crtc->enabled)
3901                         intel_crtc_disable(crtc);
3902         }
3903 }
3904
3905 void intel_encoder_destroy(struct drm_encoder *encoder)
3906 {
3907         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3908
3909         drm_encoder_cleanup(encoder);
3910         kfree(intel_encoder);
3911 }
3912
3913 /* Simple dpms helper for encodres with just one connector, no cloning and only
3914  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3915  * state of the entire output pipe. */
3916 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3917 {
3918         if (mode == DRM_MODE_DPMS_ON) {
3919                 encoder->connectors_active = true;
3920
3921                 intel_crtc_update_dpms(encoder->base.crtc);
3922         } else {
3923                 encoder->connectors_active = false;
3924
3925                 intel_crtc_update_dpms(encoder->base.crtc);
3926         }
3927 }
3928
3929 /* Cross check the actual hw state with our own modeset state tracking (and it's
3930  * internal consistency). */
3931 static void intel_connector_check_state(struct intel_connector *connector)
3932 {
3933         if (connector->get_hw_state(connector)) {
3934                 struct intel_encoder *encoder = connector->encoder;
3935                 struct drm_crtc *crtc;
3936                 bool encoder_enabled;
3937                 enum pipe pipe;
3938
3939                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3940                               connector->base.base.id,
3941                               drm_get_connector_name(&connector->base));
3942
3943                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3944                      "wrong connector dpms state\n");
3945                 WARN(connector->base.encoder != &encoder->base,
3946                      "active connector not linked to encoder\n");
3947                 WARN(!encoder->connectors_active,
3948                      "encoder->connectors_active not set\n");
3949
3950                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3951                 WARN(!encoder_enabled, "encoder not enabled\n");
3952                 if (WARN_ON(!encoder->base.crtc))
3953                         return;
3954
3955                 crtc = encoder->base.crtc;
3956
3957                 WARN(!crtc->enabled, "crtc not enabled\n");
3958                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3959                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3960                      "encoder active on the wrong pipe\n");
3961         }
3962 }
3963
3964 /* Even simpler default implementation, if there's really no special case to
3965  * consider. */
3966 void intel_connector_dpms(struct drm_connector *connector, int mode)
3967 {
3968         struct intel_encoder *encoder = intel_attached_encoder(connector);
3969
3970         /* All the simple cases only support two dpms states. */
3971         if (mode != DRM_MODE_DPMS_ON)
3972                 mode = DRM_MODE_DPMS_OFF;
3973
3974         if (mode == connector->dpms)
3975                 return;
3976
3977         connector->dpms = mode;
3978
3979         /* Only need to change hw state when actually enabled */
3980         if (encoder->base.crtc)
3981                 intel_encoder_dpms(encoder, mode);
3982         else
3983                 WARN_ON(encoder->connectors_active != false);
3984
3985         intel_modeset_check_state(connector->dev);
3986 }
3987
3988 /* Simple connector->get_hw_state implementation for encoders that support only
3989  * one connector and no cloning and hence the encoder state determines the state
3990  * of the connector. */
3991 bool intel_connector_get_hw_state(struct intel_connector *connector)
3992 {
3993         enum pipe pipe = 0;
3994         struct intel_encoder *encoder = connector->encoder;
3995
3996         return encoder->get_hw_state(encoder, &pipe);
3997 }
3998
3999 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4000                                      struct intel_crtc_config *pipe_config)
4001 {
4002         struct drm_i915_private *dev_priv = dev->dev_private;
4003         struct intel_crtc *pipe_B_crtc =
4004                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4005
4006         DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4007                       pipe_name(pipe), pipe_config->fdi_lanes);
4008         if (pipe_config->fdi_lanes > 4) {
4009                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4010                               pipe_name(pipe), pipe_config->fdi_lanes);
4011                 return false;
4012         }
4013
4014         if (IS_HASWELL(dev)) {
4015                 if (pipe_config->fdi_lanes > 2) {
4016                         DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4017                                       pipe_config->fdi_lanes);
4018                         return false;
4019                 } else {
4020                         return true;
4021                 }
4022         }
4023
4024         if (INTEL_INFO(dev)->num_pipes == 2)
4025                 return true;
4026
4027         /* Ivybridge 3 pipe is really complicated */
4028         switch (pipe) {
4029         case PIPE_A:
4030                 return true;
4031         case PIPE_B:
4032                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4033                     pipe_config->fdi_lanes > 2) {
4034                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4035                                       pipe_name(pipe), pipe_config->fdi_lanes);
4036                         return false;
4037                 }
4038                 return true;
4039         case PIPE_C:
4040                 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
4041                     pipe_B_crtc->config.fdi_lanes <= 2) {
4042                         if (pipe_config->fdi_lanes > 2) {
4043                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4044                                               pipe_name(pipe), pipe_config->fdi_lanes);
4045                                 return false;
4046                         }
4047                 } else {
4048                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4049                         return false;
4050                 }
4051                 return true;
4052         default:
4053                 BUG();
4054         }
4055 }
4056
4057 #define RETRY 1
4058 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4059                                        struct intel_crtc_config *pipe_config)
4060 {
4061         struct drm_device *dev = intel_crtc->base.dev;
4062         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4063         int target_clock, lane, link_bw;
4064         bool setup_ok, needs_recompute = false;
4065
4066 retry:
4067         /* FDI is a binary signal running at ~2.7GHz, encoding
4068          * each output octet as 10 bits. The actual frequency
4069          * is stored as a divider into a 100MHz clock, and the
4070          * mode pixel clock is stored in units of 1KHz.
4071          * Hence the bw of each lane in terms of the mode signal
4072          * is:
4073          */
4074         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4075
4076         if (pipe_config->pixel_target_clock)
4077                 target_clock = pipe_config->pixel_target_clock;
4078         else
4079                 target_clock = adjusted_mode->clock;
4080
4081         lane = ironlake_get_lanes_required(target_clock, link_bw,
4082                                            pipe_config->pipe_bpp);
4083
4084         pipe_config->fdi_lanes = lane;
4085
4086         if (pipe_config->pixel_multiplier > 1)
4087                 link_bw *= pipe_config->pixel_multiplier;
4088         intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4089                                link_bw, &pipe_config->fdi_m_n);
4090
4091         setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4092                                             intel_crtc->pipe, pipe_config);
4093         if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4094                 pipe_config->pipe_bpp -= 2*3;
4095                 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4096                               pipe_config->pipe_bpp);
4097                 needs_recompute = true;
4098                 pipe_config->bw_constrained = true;
4099
4100                 goto retry;
4101         }
4102
4103         if (needs_recompute)
4104                 return RETRY;
4105
4106         return setup_ok ? 0 : -EINVAL;
4107 }
4108
4109 static int intel_crtc_compute_config(struct drm_crtc *crtc,
4110                                      struct intel_crtc_config *pipe_config)
4111 {
4112         struct drm_device *dev = crtc->dev;
4113         struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4114
4115         if (HAS_PCH_SPLIT(dev)) {
4116                 /* FDI link clock is fixed at 2.7G */
4117                 if (pipe_config->requested_mode.clock * 3
4118                     > IRONLAKE_FDI_FREQ * 4)
4119                         return -EINVAL;
4120         }
4121
4122         /* All interlaced capable intel hw wants timings in frames. Note though
4123          * that intel_lvds_mode_fixup does some funny tricks with the crtc
4124          * timings, so we need to be careful not to clobber these.*/
4125         if (!pipe_config->timings_set)
4126                 drm_mode_set_crtcinfo(adjusted_mode, 0);
4127
4128         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4129          * with a hsync front porch of 0.
4130          */
4131         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4132                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4133                 return -EINVAL;
4134
4135         if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4136                 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4137         } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4138                 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4139                  * for lvds. */
4140                 pipe_config->pipe_bpp = 8*3;
4141         }
4142
4143         if (pipe_config->has_pch_encoder)
4144                 return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
4145
4146         return 0;
4147 }
4148
4149 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4150 {
4151         return 400000; /* FIXME */
4152 }
4153
4154 static int i945_get_display_clock_speed(struct drm_device *dev)
4155 {
4156         return 400000;
4157 }
4158
4159 static int i915_get_display_clock_speed(struct drm_device *dev)
4160 {
4161         return 333000;
4162 }
4163
4164 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4165 {
4166         return 200000;
4167 }
4168
4169 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4170 {
4171         u16 gcfgc = 0;
4172
4173         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4174
4175         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4176                 return 133000;
4177         else {
4178                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4179                 case GC_DISPLAY_CLOCK_333_MHZ:
4180                         return 333000;
4181                 default:
4182                 case GC_DISPLAY_CLOCK_190_200_MHZ:
4183                         return 190000;
4184                 }
4185         }
4186 }
4187
4188 static int i865_get_display_clock_speed(struct drm_device *dev)
4189 {
4190         return 266000;
4191 }
4192
4193 static int i855_get_display_clock_speed(struct drm_device *dev)
4194 {
4195         u16 hpllcc = 0;
4196         /* Assume that the hardware is in the high speed state.  This
4197          * should be the default.
4198          */
4199         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4200         case GC_CLOCK_133_200:
4201         case GC_CLOCK_100_200:
4202                 return 200000;
4203         case GC_CLOCK_166_250:
4204                 return 250000;
4205         case GC_CLOCK_100_133:
4206                 return 133000;
4207         }
4208
4209         /* Shouldn't happen */
4210         return 0;
4211 }
4212
4213 static int i830_get_display_clock_speed(struct drm_device *dev)
4214 {
4215         return 133000;
4216 }
4217
4218 static void
4219 intel_reduce_ratio(uint32_t *num, uint32_t *den)
4220 {
4221         while (*num > 0xffffff || *den > 0xffffff) {
4222                 *num >>= 1;
4223                 *den >>= 1;
4224         }
4225 }
4226
4227 void
4228 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4229                        int pixel_clock, int link_clock,
4230                        struct intel_link_m_n *m_n)
4231 {
4232         m_n->tu = 64;
4233         m_n->gmch_m = bits_per_pixel * pixel_clock;
4234         m_n->gmch_n = link_clock * nlanes * 8;
4235         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4236         m_n->link_m = pixel_clock;
4237         m_n->link_n = link_clock;
4238         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
4239 }
4240
4241 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4242 {
4243         if (i915_panel_use_ssc >= 0)
4244                 return i915_panel_use_ssc != 0;
4245         return dev_priv->lvds_use_ssc
4246                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4247 }
4248
4249 static int vlv_get_refclk(struct drm_crtc *crtc)
4250 {
4251         struct drm_device *dev = crtc->dev;
4252         struct drm_i915_private *dev_priv = dev->dev_private;
4253         int refclk = 27000; /* for DP & HDMI */
4254
4255         return 100000; /* only one validated so far */
4256
4257         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4258                 refclk = 96000;
4259         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4260                 if (intel_panel_use_ssc(dev_priv))
4261                         refclk = 100000;
4262                 else
4263                         refclk = 96000;
4264         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4265                 refclk = 100000;
4266         }
4267
4268         return refclk;
4269 }
4270
4271 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4272 {
4273         struct drm_device *dev = crtc->dev;
4274         struct drm_i915_private *dev_priv = dev->dev_private;
4275         int refclk;
4276
4277         if (IS_VALLEYVIEW(dev)) {
4278                 refclk = vlv_get_refclk(crtc);
4279         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4280             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4281                 refclk = dev_priv->lvds_ssc_freq * 1000;
4282                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4283                               refclk / 1000);
4284         } else if (!IS_GEN2(dev)) {
4285                 refclk = 96000;
4286         } else {
4287                 refclk = 48000;
4288         }
4289
4290         return refclk;
4291 }
4292
4293 static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
4294 {
4295         unsigned dotclock = crtc->config.adjusted_mode.clock;
4296         struct dpll *clock = &crtc->config.dpll;
4297
4298         /* SDVO TV has fixed PLL values depend on its clock range,
4299            this mirrors vbios setting. */
4300         if (dotclock >= 100000 && dotclock < 140500) {
4301                 clock->p1 = 2;
4302                 clock->p2 = 10;
4303                 clock->n = 3;
4304                 clock->m1 = 16;
4305                 clock->m2 = 8;
4306         } else if (dotclock >= 140500 && dotclock <= 200000) {
4307                 clock->p1 = 1;
4308                 clock->p2 = 10;
4309                 clock->n = 6;
4310                 clock->m1 = 12;
4311                 clock->m2 = 8;
4312         }
4313
4314         crtc->config.clock_set = true;
4315 }
4316
4317 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4318 {
4319         return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4320 }
4321
4322 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4323 {
4324         return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4325 }
4326
4327 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4328                                      intel_clock_t *reduced_clock)
4329 {
4330         struct drm_device *dev = crtc->base.dev;
4331         struct drm_i915_private *dev_priv = dev->dev_private;
4332         int pipe = crtc->pipe;
4333         u32 fp, fp2 = 0;
4334
4335         if (IS_PINEVIEW(dev)) {
4336                 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4337                 if (reduced_clock)
4338                         fp2 = pnv_dpll_compute_fp(reduced_clock);
4339         } else {
4340                 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4341                 if (reduced_clock)
4342                         fp2 = i9xx_dpll_compute_fp(reduced_clock);
4343         }
4344
4345         I915_WRITE(FP0(pipe), fp);
4346
4347         crtc->lowfreq_avail = false;
4348         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4349             reduced_clock && i915_powersave) {
4350                 I915_WRITE(FP1(pipe), fp2);
4351                 crtc->lowfreq_avail = true;
4352         } else {
4353                 I915_WRITE(FP1(pipe), fp);
4354         }
4355 }
4356
4357 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4358 {
4359         u32 reg_val;
4360
4361         /*
4362          * PLLB opamp always calibrates to max value of 0x3f, force enable it
4363          * and set it to a reasonable value instead.
4364          */
4365         reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4366         reg_val &= 0xffffff00;
4367         reg_val |= 0x00000030;
4368         intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4369
4370         reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4371         reg_val &= 0x8cffffff;
4372         reg_val = 0x8c000000;
4373         intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4374
4375         reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4376         reg_val &= 0xffffff00;
4377         intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4378
4379         reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4380         reg_val &= 0x00ffffff;
4381         reg_val |= 0xb0000000;
4382         intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4383 }
4384
4385 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4386 {
4387         if (crtc->config.has_pch_encoder)
4388                 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4389         else
4390                 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4391 }
4392
4393 static void vlv_update_pll(struct intel_crtc *crtc)
4394 {
4395         struct drm_device *dev = crtc->base.dev;
4396         struct drm_i915_private *dev_priv = dev->dev_private;
4397         struct drm_display_mode *adjusted_mode =
4398                 &crtc->config.adjusted_mode;
4399         struct intel_encoder *encoder;
4400         int pipe = crtc->pipe;
4401         u32 dpll, mdiv;
4402         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4403         bool is_hdmi;
4404         u32 coreclk, reg_val, dpll_md;
4405
4406         mutex_lock(&dev_priv->dpio_lock);
4407
4408         is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4409
4410         bestn = crtc->config.dpll.n;
4411         bestm1 = crtc->config.dpll.m1;
4412         bestm2 = crtc->config.dpll.m2;
4413         bestp1 = crtc->config.dpll.p1;
4414         bestp2 = crtc->config.dpll.p2;
4415
4416         /* See eDP HDMI DPIO driver vbios notes doc */
4417
4418         /* PLL B needs special handling */
4419         if (pipe)
4420                 vlv_pllb_recal_opamp(dev_priv);
4421
4422         /* Set up Tx target for periodic Rcomp update */
4423         intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4424
4425         /* Disable target IRef on PLL */
4426         reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4427         reg_val &= 0x00ffffff;
4428         intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4429
4430         /* Disable fast lock */
4431         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4432
4433         /* Set idtafcrecal before PLL is enabled */
4434         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4435         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4436         mdiv |= ((bestn << DPIO_N_SHIFT));
4437         mdiv |= (1 << DPIO_K_SHIFT);
4438         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
4439             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4440             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4441                 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4442         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4443
4444         mdiv |= DPIO_ENABLE_CALIBRATION;
4445         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4446
4447         /* Set HBR and RBR LPF coefficients */
4448         if (adjusted_mode->clock == 162000 ||
4449             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4450                 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4451                                  0x005f0021);
4452         else
4453                 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4454                                  0x00d0000f);
4455
4456         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4457             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4458                 /* Use SSC source */
4459                 if (!pipe)
4460                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4461                                          0x0df40000);
4462                 else
4463                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4464                                          0x0df70000);
4465         } else { /* HDMI or VGA */
4466                 /* Use bend source */
4467                 if (!pipe)
4468                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4469                                          0x0df70000);
4470                 else
4471                         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4472                                          0x0df40000);
4473         }
4474
4475         coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4476         coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4477         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4478             intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4479                 coreclk |= 0x01000000;
4480         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4481
4482         intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4483
4484         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4485                 if (encoder->pre_pll_enable)
4486                         encoder->pre_pll_enable(encoder);
4487
4488         /* Enable DPIO clock input */
4489         dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4490                 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4491         if (pipe)
4492                 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4493
4494         dpll |= DPLL_VCO_ENABLE;
4495         I915_WRITE(DPLL(pipe), dpll);
4496         POSTING_READ(DPLL(pipe));
4497         udelay(150);
4498
4499         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4500                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4501
4502         dpll_md = 0;
4503         if (crtc->config.pixel_multiplier > 1) {
4504                 dpll_md = (crtc->config.pixel_multiplier - 1)
4505                         << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4506         }
4507         I915_WRITE(DPLL_MD(pipe), dpll_md);
4508         POSTING_READ(DPLL_MD(pipe));
4509
4510         if (crtc->config.has_dp_encoder)
4511                 intel_dp_set_m_n(crtc);
4512
4513         mutex_unlock(&dev_priv->dpio_lock);
4514 }
4515
4516 static void i9xx_update_pll(struct intel_crtc *crtc,
4517                             intel_clock_t *reduced_clock,
4518                             int num_connectors)
4519 {
4520         struct drm_device *dev = crtc->base.dev;
4521         struct drm_i915_private *dev_priv = dev->dev_private;
4522         struct intel_encoder *encoder;
4523         int pipe = crtc->pipe;
4524         u32 dpll;
4525         bool is_sdvo;
4526         struct dpll *clock = &crtc->config.dpll;
4527
4528         i9xx_update_pll_dividers(crtc, reduced_clock);
4529
4530         is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4531                 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4532
4533         dpll = DPLL_VGA_MODE_DIS;
4534
4535         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4536                 dpll |= DPLLB_MODE_LVDS;
4537         else
4538                 dpll |= DPLLB_MODE_DAC_SERIAL;
4539
4540         if ((crtc->config.pixel_multiplier > 1) &&
4541             (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4542                 dpll |= (crtc->config.pixel_multiplier - 1)
4543                         << SDVO_MULTIPLIER_SHIFT_HIRES;
4544         }
4545
4546         if (is_sdvo)
4547                 dpll |= DPLL_DVO_HIGH_SPEED;
4548
4549         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4550                 dpll |= DPLL_DVO_HIGH_SPEED;
4551
4552         /* compute bitmask from p1 value */
4553         if (IS_PINEVIEW(dev))
4554                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4555         else {
4556                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4557                 if (IS_G4X(dev) && reduced_clock)
4558                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4559         }
4560         switch (clock->p2) {
4561         case 5:
4562                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4563                 break;
4564         case 7:
4565                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4566                 break;
4567         case 10:
4568                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4569                 break;
4570         case 14:
4571                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4572                 break;
4573         }
4574         if (INTEL_INFO(dev)->gen >= 4)
4575                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4576
4577         if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4578                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4579         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
4580                 /* XXX: just matching BIOS for now */
4581                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4582                 dpll |= 3;
4583         else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4584                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4585                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4586         else
4587                 dpll |= PLL_REF_INPUT_DREFCLK;
4588
4589         dpll |= DPLL_VCO_ENABLE;
4590         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4591         POSTING_READ(DPLL(pipe));
4592         udelay(150);
4593
4594         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4595                 if (encoder->pre_pll_enable)
4596                         encoder->pre_pll_enable(encoder);
4597
4598         if (crtc->config.has_dp_encoder)
4599                 intel_dp_set_m_n(crtc);
4600
4601         I915_WRITE(DPLL(pipe), dpll);
4602
4603         /* Wait for the clocks to stabilize. */
4604         POSTING_READ(DPLL(pipe));
4605         udelay(150);
4606
4607         if (INTEL_INFO(dev)->gen >= 4) {
4608                 u32 dpll_md = 0;
4609                 if (crtc->config.pixel_multiplier > 1) {
4610                         dpll_md = (crtc->config.pixel_multiplier - 1)
4611                                 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4612                 }
4613                 I915_WRITE(DPLL_MD(pipe), dpll_md);
4614         } else {
4615                 /* The pixel multiplier can only be updated once the
4616                  * DPLL is enabled and the clocks are stable.
4617                  *
4618                  * So write it again.
4619                  */
4620                 I915_WRITE(DPLL(pipe), dpll);
4621         }
4622 }
4623
4624 static void i8xx_update_pll(struct intel_crtc *crtc,
4625                             struct drm_display_mode *adjusted_mode,
4626                             intel_clock_t *reduced_clock,
4627                             int num_connectors)
4628 {
4629         struct drm_device *dev = crtc->base.dev;
4630         struct drm_i915_private *dev_priv = dev->dev_private;
4631         struct intel_encoder *encoder;
4632         int pipe = crtc->pipe;
4633         u32 dpll;
4634         struct dpll *clock = &crtc->config.dpll;
4635
4636         i9xx_update_pll_dividers(crtc, reduced_clock);
4637
4638         dpll = DPLL_VGA_MODE_DIS;
4639
4640         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4641                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4642         } else {
4643                 if (clock->p1 == 2)
4644                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4645                 else
4646                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4647                 if (clock->p2 == 4)
4648                         dpll |= PLL_P2_DIVIDE_BY_4;
4649         }
4650
4651         if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4652                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4653                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4654         else
4655                 dpll |= PLL_REF_INPUT_DREFCLK;
4656
4657         dpll |= DPLL_VCO_ENABLE;
4658         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4659         POSTING_READ(DPLL(pipe));
4660         udelay(150);
4661
4662         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4663                 if (encoder->pre_pll_enable)
4664                         encoder->pre_pll_enable(encoder);
4665
4666         I915_WRITE(DPLL(pipe), dpll);
4667
4668         /* Wait for the clocks to stabilize. */
4669         POSTING_READ(DPLL(pipe));
4670         udelay(150);
4671
4672         /* The pixel multiplier can only be updated once the
4673          * DPLL is enabled and the clocks are stable.
4674          *
4675          * So write it again.
4676          */
4677         I915_WRITE(DPLL(pipe), dpll);
4678 }
4679
4680 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4681                                    struct drm_display_mode *mode,
4682                                    struct drm_display_mode *adjusted_mode)
4683 {
4684         struct drm_device *dev = intel_crtc->base.dev;
4685         struct drm_i915_private *dev_priv = dev->dev_private;
4686         enum pipe pipe = intel_crtc->pipe;
4687         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4688         uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4689
4690         /* We need to be careful not to changed the adjusted mode, for otherwise
4691          * the hw state checker will get angry at the mismatch. */
4692         crtc_vtotal = adjusted_mode->crtc_vtotal;
4693         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4694
4695         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4696                 /* the chip adds 2 halflines automatically */
4697                 crtc_vtotal -= 1;
4698                 crtc_vblank_end -= 1;
4699                 vsyncshift = adjusted_mode->crtc_hsync_start
4700                              - adjusted_mode->crtc_htotal / 2;
4701         } else {
4702                 vsyncshift = 0;
4703         }
4704
4705         if (INTEL_INFO(dev)->gen > 3)
4706                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4707
4708         I915_WRITE(HTOTAL(cpu_transcoder),
4709                    (adjusted_mode->crtc_hdisplay - 1) |
4710                    ((adjusted_mode->crtc_htotal - 1) << 16));
4711         I915_WRITE(HBLANK(cpu_transcoder),
4712                    (adjusted_mode->crtc_hblank_start - 1) |
4713                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4714         I915_WRITE(HSYNC(cpu_transcoder),
4715                    (adjusted_mode->crtc_hsync_start - 1) |
4716                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4717
4718         I915_WRITE(VTOTAL(cpu_transcoder),
4719                    (adjusted_mode->crtc_vdisplay - 1) |
4720                    ((crtc_vtotal - 1) << 16));
4721         I915_WRITE(VBLANK(cpu_transcoder),
4722                    (adjusted_mode->crtc_vblank_start - 1) |
4723                    ((crtc_vblank_end - 1) << 16));
4724         I915_WRITE(VSYNC(cpu_transcoder),
4725                    (adjusted_mode->crtc_vsync_start - 1) |
4726                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4727
4728         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4729          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4730          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4731          * bits. */
4732         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4733             (pipe == PIPE_B || pipe == PIPE_C))
4734                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4735
4736         /* pipesrc controls the size that is scaled from, which should
4737          * always be the user's requested size.
4738          */
4739         I915_WRITE(PIPESRC(pipe),
4740                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4741 }
4742
4743 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4744                                    struct intel_crtc_config *pipe_config)
4745 {
4746         struct drm_device *dev = crtc->base.dev;
4747         struct drm_i915_private *dev_priv = dev->dev_private;
4748         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4749         uint32_t tmp;
4750
4751         tmp = I915_READ(HTOTAL(cpu_transcoder));
4752         pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4753         pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4754         tmp = I915_READ(HBLANK(cpu_transcoder));
4755         pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4756         pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4757         tmp = I915_READ(HSYNC(cpu_transcoder));
4758         pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4759         pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4760
4761         tmp = I915_READ(VTOTAL(cpu_transcoder));
4762         pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4763         pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4764         tmp = I915_READ(VBLANK(cpu_transcoder));
4765         pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4766         pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4767         tmp = I915_READ(VSYNC(cpu_transcoder));
4768         pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4769         pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4770
4771         if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4772                 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4773                 pipe_config->adjusted_mode.crtc_vtotal += 1;
4774                 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4775         }
4776
4777         tmp = I915_READ(PIPESRC(crtc->pipe));
4778         pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4779         pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4780 }
4781
4782 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4783 {
4784         struct drm_device *dev = intel_crtc->base.dev;
4785         struct drm_i915_private *dev_priv = dev->dev_private;
4786         uint32_t pipeconf;
4787
4788         pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4789
4790         if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4791                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4792                  * core speed.
4793                  *
4794                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4795                  * pipe == 0 check?
4796                  */
4797                 if (intel_crtc->config.requested_mode.clock >
4798                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4799                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4800                 else
4801                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4802         }
4803
4804         /* only g4x and later have fancy bpc/dither controls */
4805         if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4806                 pipeconf &= ~(PIPECONF_BPC_MASK |
4807                               PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4808
4809                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4810                 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4811                         pipeconf |= PIPECONF_DITHER_EN |
4812                                     PIPECONF_DITHER_TYPE_SP;
4813
4814                 switch (intel_crtc->config.pipe_bpp) {
4815                 case 18:
4816                         pipeconf |= PIPECONF_6BPC;
4817                         break;
4818                 case 24:
4819                         pipeconf |= PIPECONF_8BPC;
4820                         break;
4821                 case 30:
4822                         pipeconf |= PIPECONF_10BPC;
4823                         break;
4824                 default:
4825                         /* Case prevented by intel_choose_pipe_bpp_dither. */
4826                         BUG();
4827                 }
4828         }
4829
4830         if (HAS_PIPE_CXSR(dev)) {
4831                 if (intel_crtc->lowfreq_avail) {
4832                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4833                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4834                 } else {
4835                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4836                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4837                 }
4838         }
4839
4840         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4841         if (!IS_GEN2(dev) &&
4842             intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4843                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4844         else
4845                 pipeconf |= PIPECONF_PROGRESSIVE;
4846
4847         if (IS_VALLEYVIEW(dev)) {
4848                 if (intel_crtc->config.limited_color_range)
4849                         pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4850                 else
4851                         pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4852         }
4853
4854         I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4855         POSTING_READ(PIPECONF(intel_crtc->pipe));
4856 }
4857
4858 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4859                               int x, int y,
4860                               struct drm_framebuffer *fb)
4861 {
4862         struct drm_device *dev = crtc->dev;
4863         struct drm_i915_private *dev_priv = dev->dev_private;
4864         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4865         struct drm_display_mode *adjusted_mode =
4866                 &intel_crtc->config.adjusted_mode;
4867         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4868         int pipe = intel_crtc->pipe;
4869         int plane = intel_crtc->plane;
4870         int refclk, num_connectors = 0;
4871         intel_clock_t clock, reduced_clock;
4872         u32 dspcntr;
4873         bool ok, has_reduced_clock = false, is_sdvo = false;
4874         bool is_lvds = false, is_tv = false;
4875         struct intel_encoder *encoder;
4876         const intel_limit_t *limit;
4877         int ret;
4878
4879         for_each_encoder_on_crtc(dev, crtc, encoder) {
4880                 switch (encoder->type) {
4881                 case INTEL_OUTPUT_LVDS:
4882                         is_lvds = true;
4883                         break;
4884                 case INTEL_OUTPUT_SDVO:
4885                 case INTEL_OUTPUT_HDMI:
4886                         is_sdvo = true;
4887                         if (encoder->needs_tv_clock)
4888                                 is_tv = true;
4889                         break;
4890                 case INTEL_OUTPUT_TVOUT:
4891                         is_tv = true;
4892                         break;
4893                 }
4894
4895                 num_connectors++;
4896         }
4897
4898         refclk = i9xx_get_refclk(crtc, num_connectors);
4899
4900         /*
4901          * Returns a set of divisors for the desired target clock with the given
4902          * refclk, or FALSE.  The returned values represent the clock equation:
4903          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4904          */
4905         limit = intel_limit(crtc, refclk);
4906         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4907                              &clock);
4908         if (!ok) {
4909                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4910                 return -EINVAL;
4911         }
4912
4913         /* Ensure that the cursor is valid for the new mode before changing... */
4914         intel_crtc_update_cursor(crtc, true);
4915
4916         if (is_lvds && dev_priv->lvds_downclock_avail) {
4917                 /*
4918                  * Ensure we match the reduced clock's P to the target clock.
4919                  * If the clocks don't match, we can't switch the display clock
4920                  * by using the FP0/FP1. In such case we will disable the LVDS
4921                  * downclock feature.
4922                 */
4923                 has_reduced_clock = limit->find_pll(limit, crtc,
4924                                                     dev_priv->lvds_downclock,
4925                                                     refclk,
4926                                                     &clock,
4927                                                     &reduced_clock);
4928         }
4929         /* Compat-code for transition, will disappear. */
4930         if (!intel_crtc->config.clock_set) {
4931                 intel_crtc->config.dpll.n = clock.n;
4932                 intel_crtc->config.dpll.m1 = clock.m1;
4933                 intel_crtc->config.dpll.m2 = clock.m2;
4934                 intel_crtc->config.dpll.p1 = clock.p1;
4935                 intel_crtc->config.dpll.p2 = clock.p2;
4936         }
4937
4938         if (is_sdvo && is_tv)
4939                 i9xx_adjust_sdvo_tv_clock(intel_crtc);
4940
4941         if (IS_GEN2(dev))
4942                 i8xx_update_pll(intel_crtc, adjusted_mode,
4943                                 has_reduced_clock ? &reduced_clock : NULL,
4944                                 num_connectors);
4945         else if (IS_VALLEYVIEW(dev))
4946                 vlv_update_pll(intel_crtc);
4947         else
4948                 i9xx_update_pll(intel_crtc,
4949                                 has_reduced_clock ? &reduced_clock : NULL,
4950                                 num_connectors);
4951
4952         /* Set up the display plane register */
4953         dspcntr = DISPPLANE_GAMMA_ENABLE;
4954
4955         if (!IS_VALLEYVIEW(dev)) {
4956                 if (pipe == 0)
4957                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4958                 else
4959                         dspcntr |= DISPPLANE_SEL_PIPE_B;
4960         }
4961
4962         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
4963         drm_mode_debug_printmodeline(mode);
4964
4965         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4966
4967         /* pipesrc and dspsize control the size that is scaled from,
4968          * which should always be the user's requested size.
4969          */
4970         I915_WRITE(DSPSIZE(plane),
4971                    ((mode->vdisplay - 1) << 16) |
4972                    (mode->hdisplay - 1));
4973         I915_WRITE(DSPPOS(plane), 0);
4974
4975         i9xx_set_pipeconf(intel_crtc);
4976
4977         I915_WRITE(DSPCNTR(plane), dspcntr);
4978         POSTING_READ(DSPCNTR(plane));
4979
4980         ret = intel_pipe_set_base(crtc, x, y, fb);
4981
4982         intel_update_watermarks(dev);
4983
4984         return ret;
4985 }
4986
4987 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4988                                  struct intel_crtc_config *pipe_config)
4989 {
4990         struct drm_device *dev = crtc->base.dev;
4991         struct drm_i915_private *dev_priv = dev->dev_private;
4992         uint32_t tmp;
4993
4994         tmp = I915_READ(PIPECONF(crtc->pipe));
4995         if (!(tmp & PIPECONF_ENABLE))
4996                 return false;
4997
4998         intel_get_pipe_timings(crtc, pipe_config);
4999
5000         return true;
5001 }
5002
5003 static void ironlake_init_pch_refclk(struct drm_device *dev)
5004 {
5005         struct drm_i915_private *dev_priv = dev->dev_private;
5006         struct drm_mode_config *mode_config = &dev->mode_config;
5007         struct intel_encoder *encoder;
5008         u32 val, final;
5009         bool has_lvds = false;
5010         bool has_cpu_edp = false;
5011         bool has_pch_edp = false;
5012         bool has_panel = false;
5013         bool has_ck505 = false;
5014         bool can_ssc = false;
5015
5016         /* We need to take the global config into account */
5017         list_for_each_entry(encoder, &mode_config->encoder_list,
5018                             base.head) {
5019                 switch (encoder->type) {
5020                 case INTEL_OUTPUT_LVDS:
5021                         has_panel = true;
5022                         has_lvds = true;
5023                         break;
5024                 case INTEL_OUTPUT_EDP:
5025                         has_panel = true;
5026                         if (intel_encoder_is_pch_edp(&encoder->base))
5027                                 has_pch_edp = true;
5028                         else
5029                                 has_cpu_edp = true;
5030                         break;
5031                 }
5032         }
5033
5034         if (HAS_PCH_IBX(dev)) {
5035                 has_ck505 = dev_priv->display_clock_mode;
5036                 can_ssc = has_ck505;
5037         } else {
5038                 has_ck505 = false;
5039                 can_ssc = true;
5040         }
5041
5042         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5043                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5044                       has_ck505);
5045
5046         /* Ironlake: try to setup display ref clock before DPLL
5047          * enabling. This is only under driver's control after
5048          * PCH B stepping, previous chipset stepping should be
5049          * ignoring this setting.
5050          */
5051         val = I915_READ(PCH_DREF_CONTROL);
5052
5053         /* As we must carefully and slowly disable/enable each source in turn,
5054          * compute the final state we want first and check if we need to
5055          * make any changes at all.
5056          */
5057         final = val;
5058         final &= ~DREF_NONSPREAD_SOURCE_MASK;
5059         if (has_ck505)
5060                 final |= DREF_NONSPREAD_CK505_ENABLE;
5061         else
5062                 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5063
5064         final &= ~DREF_SSC_SOURCE_MASK;
5065         final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5066         final &= ~DREF_SSC1_ENABLE;
5067
5068         if (has_panel) {
5069                 final |= DREF_SSC_SOURCE_ENABLE;
5070
5071                 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5072                         final |= DREF_SSC1_ENABLE;
5073
5074                 if (has_cpu_edp) {
5075                         if (intel_panel_use_ssc(dev_priv) && can_ssc)
5076                                 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5077                         else
5078                                 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5079                 } else
5080                         final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5081         } else {
5082                 final |= DREF_SSC_SOURCE_DISABLE;
5083                 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5084         }
5085
5086         if (final == val)
5087                 return;
5088
5089         /* Always enable nonspread source */
5090         val &= ~DREF_NONSPREAD_SOURCE_MASK;
5091
5092         if (has_ck505)
5093                 val |= DREF_NONSPREAD_CK505_ENABLE;
5094         else
5095                 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5096
5097         if (has_panel) {
5098                 val &= ~DREF_SSC_SOURCE_MASK;
5099                 val |= DREF_SSC_SOURCE_ENABLE;
5100
5101                 /* SSC must be turned on before enabling the CPU output  */
5102                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5103                         DRM_DEBUG_KMS("Using SSC on panel\n");
5104                         val |= DREF_SSC1_ENABLE;
5105                 } else
5106                         val &= ~DREF_SSC1_ENABLE;
5107
5108                 /* Get SSC going before enabling the outputs */
5109                 I915_WRITE(PCH_DREF_CONTROL, val);
5110                 POSTING_READ(PCH_DREF_CONTROL);
5111                 udelay(200);
5112
5113                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5114
5115                 /* Enable CPU source on CPU attached eDP */
5116                 if (has_cpu_edp) {
5117                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5118                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
5119                                 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5120                         }
5121                         else
5122                                 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5123                 } else
5124                         val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5125
5126                 I915_WRITE(PCH_DREF_CONTROL, val);
5127                 POSTING_READ(PCH_DREF_CONTROL);
5128                 udelay(200);
5129         } else {
5130                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5131
5132                 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5133
5134                 /* Turn off CPU output */
5135                 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5136
5137                 I915_WRITE(PCH_DREF_CONTROL, val);
5138                 POSTING_READ(PCH_DREF_CONTROL);
5139                 udelay(200);
5140
5141                 /* Turn off the SSC source */
5142                 val &= ~DREF_SSC_SOURCE_MASK;
5143                 val |= DREF_SSC_SOURCE_DISABLE;
5144
5145                 /* Turn off SSC1 */
5146                 val &= ~DREF_SSC1_ENABLE;
5147
5148                 I915_WRITE(PCH_DREF_CONTROL, val);
5149                 POSTING_READ(PCH_DREF_CONTROL);
5150                 udelay(200);
5151         }
5152
5153         BUG_ON(val != final);
5154 }
5155
5156 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5157 static void lpt_init_pch_refclk(struct drm_device *dev)
5158 {
5159         struct drm_i915_private *dev_priv = dev->dev_private;
5160         struct drm_mode_config *mode_config = &dev->mode_config;
5161         struct intel_encoder *encoder;
5162         bool has_vga = false;
5163         bool is_sdv = false;
5164         u32 tmp;
5165
5166         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5167                 switch (encoder->type) {
5168                 case INTEL_OUTPUT_ANALOG:
5169                         has_vga = true;
5170                         break;
5171                 }
5172         }
5173
5174         if (!has_vga)
5175                 return;
5176
5177         mutex_lock(&dev_priv->dpio_lock);
5178
5179         /* XXX: Rip out SDV support once Haswell ships for real. */
5180         if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5181                 is_sdv = true;
5182
5183         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5184         tmp &= ~SBI_SSCCTL_DISABLE;
5185         tmp |= SBI_SSCCTL_PATHALT;
5186         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5187
5188         udelay(24);
5189
5190         tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5191         tmp &= ~SBI_SSCCTL_PATHALT;
5192         intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5193
5194         if (!is_sdv) {
5195                 tmp = I915_READ(SOUTH_CHICKEN2);
5196                 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5197                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5198
5199                 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5200                                        FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5201                         DRM_ERROR("FDI mPHY reset assert timeout\n");
5202
5203                 tmp = I915_READ(SOUTH_CHICKEN2);
5204                 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5205                 I915_WRITE(SOUTH_CHICKEN2, tmp);
5206
5207                 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5208                                         FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5209                                        100))
5210                         DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5211         }
5212
5213         tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5214         tmp &= ~(0xFF << 24);
5215         tmp |= (0x12 << 24);
5216         intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5217
5218         if (is_sdv) {
5219                 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5220                 tmp |= 0x7FFF;
5221                 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5222         }
5223
5224         tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5225         tmp |= (1 << 11);
5226         intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5227
5228         tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5229         tmp |= (1 << 11);
5230         intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5231
5232         if (is_sdv) {
5233                 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5234                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5235                 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5236
5237                 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5238                 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5239                 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5240
5241                 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5242                 tmp |= (0x3F << 8);
5243                 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5244
5245                 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5246                 tmp |= (0x3F << 8);
5247                 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5248         }
5249
5250         tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5251         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5252         intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5253
5254         tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5255         tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5256         intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5257
5258         if (!is_sdv) {
5259                 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5260                 tmp &= ~(7 << 13);
5261                 tmp |= (5 << 13);
5262                 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5263
5264                 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5265                 tmp &= ~(7 << 13);
5266                 tmp |= (5 << 13);
5267                 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5268         }
5269
5270         tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5271         tmp &= ~0xFF;
5272         tmp |= 0x1C;
5273         intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5274
5275         tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5276         tmp &= ~0xFF;
5277         tmp |= 0x1C;
5278         intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5279
5280         tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5281         tmp &= ~(0xFF << 16);
5282         tmp |= (0x1C << 16);
5283         intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5284
5285         tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5286         tmp &= ~(0xFF << 16);
5287         tmp |= (0x1C << 16);
5288         intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5289
5290         if (!is_sdv) {
5291                 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5292                 tmp |= (1 << 27);
5293                 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5294
5295                 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5296                 tmp |= (1 << 27);
5297                 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5298
5299                 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5300                 tmp &= ~(0xF << 28);
5301                 tmp |= (4 << 28);
5302                 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5303
5304                 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5305                 tmp &= ~(0xF << 28);
5306                 tmp |= (4 << 28);
5307                 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5308         }
5309
5310         /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5311         tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5312         tmp |= SBI_DBUFF0_ENABLE;
5313         intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5314
5315         mutex_unlock(&dev_priv->dpio_lock);
5316 }
5317
5318 /*
5319  * Initialize reference clocks when the driver loads
5320  */
5321 void intel_init_pch_refclk(struct drm_device *dev)
5322 {
5323         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5324                 ironlake_init_pch_refclk(dev);
5325         else if (HAS_PCH_LPT(dev))
5326                 lpt_init_pch_refclk(dev);
5327 }
5328
5329 static int ironlake_get_refclk(struct drm_crtc *crtc)
5330 {
5331         struct drm_device *dev = crtc->dev;
5332         struct drm_i915_private *dev_priv = dev->dev_private;
5333         struct intel_encoder *encoder;
5334         struct intel_encoder *edp_encoder = NULL;
5335         int num_connectors = 0;
5336         bool is_lvds = false;
5337
5338         for_each_encoder_on_crtc(dev, crtc, encoder) {
5339                 switch (encoder->type) {
5340                 case INTEL_OUTPUT_LVDS:
5341                         is_lvds = true;
5342                         break;
5343                 case INTEL_OUTPUT_EDP:
5344                         edp_encoder = encoder;
5345                         break;
5346                 }
5347                 num_connectors++;
5348         }
5349
5350         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5351                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5352                               dev_priv->lvds_ssc_freq);
5353                 return dev_priv->lvds_ssc_freq * 1000;
5354         }
5355
5356         return 120000;
5357 }
5358
5359 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5360 {
5361         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5362         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5363         int pipe = intel_crtc->pipe;
5364         uint32_t val;
5365
5366         val = I915_READ(PIPECONF(pipe));
5367
5368         val &= ~PIPECONF_BPC_MASK;
5369         switch (intel_crtc->config.pipe_bpp) {
5370         case 18:
5371                 val |= PIPECONF_6BPC;
5372                 break;
5373         case 24:
5374                 val |= PIPECONF_8BPC;
5375                 break;
5376         case 30:
5377                 val |= PIPECONF_10BPC;
5378                 break;
5379         case 36:
5380                 val |= PIPECONF_12BPC;
5381                 break;
5382         default:
5383                 /* Case prevented by intel_choose_pipe_bpp_dither. */
5384                 BUG();
5385         }
5386
5387         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5388         if (intel_crtc->config.dither)
5389                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5390
5391         val &= ~PIPECONF_INTERLACE_MASK;
5392         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5393                 val |= PIPECONF_INTERLACED_ILK;
5394         else
5395                 val |= PIPECONF_PROGRESSIVE;
5396
5397         if (intel_crtc->config.limited_color_range)
5398                 val |= PIPECONF_COLOR_RANGE_SELECT;
5399         else
5400                 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5401
5402         I915_WRITE(PIPECONF(pipe), val);
5403         POSTING_READ(PIPECONF(pipe));
5404 }
5405
5406 /*
5407  * Set up the pipe CSC unit.
5408  *
5409  * Currently only full range RGB to limited range RGB conversion
5410  * is supported, but eventually this should handle various
5411  * RGB<->YCbCr scenarios as well.
5412  */
5413 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5414 {
5415         struct drm_device *dev = crtc->dev;
5416         struct drm_i915_private *dev_priv = dev->dev_private;
5417         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5418         int pipe = intel_crtc->pipe;
5419         uint16_t coeff = 0x7800; /* 1.0 */
5420
5421         /*
5422          * TODO: Check what kind of values actually come out of the pipe
5423          * with these coeff/postoff values and adjust to get the best
5424          * accuracy. Perhaps we even need to take the bpc value into
5425          * consideration.
5426          */
5427
5428         if (intel_crtc->config.limited_color_range)
5429                 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5430
5431         /*
5432          * GY/GU and RY/RU should be the other way around according
5433          * to BSpec, but reality doesn't agree. Just set them up in
5434          * a way that results in the correct picture.
5435          */
5436         I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5437         I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5438
5439         I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5440         I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5441
5442         I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5443         I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5444
5445         I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5446         I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5447         I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5448
5449         if (INTEL_INFO(dev)->gen > 6) {
5450                 uint16_t postoff = 0;
5451
5452                 if (intel_crtc->config.limited_color_range)
5453                         postoff = (16 * (1 << 13) / 255) & 0x1fff;
5454
5455                 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5456                 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5457                 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5458
5459                 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5460         } else {
5461                 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5462
5463                 if (intel_crtc->config.limited_color_range)
5464                         mode |= CSC_BLACK_SCREEN_OFFSET;
5465
5466                 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5467         }
5468 }
5469
5470 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5471 {
5472         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5473         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5474         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5475         uint32_t val;
5476
5477         val = I915_READ(PIPECONF(cpu_transcoder));
5478
5479         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5480         if (intel_crtc->config.dither)
5481                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5482
5483         val &= ~PIPECONF_INTERLACE_MASK_HSW;
5484         if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5485                 val |= PIPECONF_INTERLACED_ILK;
5486         else
5487                 val |= PIPECONF_PROGRESSIVE;
5488
5489         I915_WRITE(PIPECONF(cpu_transcoder), val);
5490         POSTING_READ(PIPECONF(cpu_transcoder));
5491 }
5492
5493 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5494                                     struct drm_display_mode *adjusted_mode,
5495                                     intel_clock_t *clock,
5496                                     bool *has_reduced_clock,
5497                                     intel_clock_t *reduced_clock)
5498 {
5499         struct drm_device *dev = crtc->dev;
5500         struct drm_i915_private *dev_priv = dev->dev_private;
5501         struct intel_encoder *intel_encoder;
5502         int refclk;
5503         const intel_limit_t *limit;
5504         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
5505
5506         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5507                 switch (intel_encoder->type) {
5508                 case INTEL_OUTPUT_LVDS:
5509                         is_lvds = true;
5510                         break;
5511                 case INTEL_OUTPUT_SDVO:
5512                 case INTEL_OUTPUT_HDMI:
5513                         is_sdvo = true;
5514                         if (intel_encoder->needs_tv_clock)
5515                                 is_tv = true;
5516                         break;
5517                 case INTEL_OUTPUT_TVOUT:
5518                         is_tv = true;
5519                         break;
5520                 }
5521         }
5522
5523         refclk = ironlake_get_refclk(crtc);
5524
5525         /*
5526          * Returns a set of divisors for the desired target clock with the given
5527          * refclk, or FALSE.  The returned values represent the clock equation:
5528          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5529          */
5530         limit = intel_limit(crtc, refclk);
5531         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5532                               clock);
5533         if (!ret)
5534                 return false;
5535
5536         if (is_lvds && dev_priv->lvds_downclock_avail) {
5537                 /*
5538                  * Ensure we match the reduced clock's P to the target clock.
5539                  * If the clocks don't match, we can't switch the display clock
5540                  * by using the FP0/FP1. In such case we will disable the LVDS
5541                  * downclock feature.
5542                 */
5543                 *has_reduced_clock = limit->find_pll(limit, crtc,
5544                                                      dev_priv->lvds_downclock,
5545                                                      refclk,
5546                                                      clock,
5547                                                      reduced_clock);
5548         }
5549
5550         if (is_sdvo && is_tv)
5551                 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
5552
5553         return true;
5554 }
5555
5556 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5557 {
5558         struct drm_i915_private *dev_priv = dev->dev_private;
5559         uint32_t temp;
5560
5561         temp = I915_READ(SOUTH_CHICKEN1);
5562         if (temp & FDI_BC_BIFURCATION_SELECT)
5563                 return;
5564
5565         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5566         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5567
5568         temp |= FDI_BC_BIFURCATION_SELECT;
5569         DRM_DEBUG_KMS("enabling fdi C rx\n");
5570         I915_WRITE(SOUTH_CHICKEN1, temp);
5571         POSTING_READ(SOUTH_CHICKEN1);
5572 }
5573
5574 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5575 {
5576         struct drm_device *dev = intel_crtc->base.dev;
5577         struct drm_i915_private *dev_priv = dev->dev_private;
5578
5579         switch (intel_crtc->pipe) {
5580         case PIPE_A:
5581                 break;
5582         case PIPE_B:
5583                 if (intel_crtc->config.fdi_lanes > 2)
5584                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5585                 else
5586                         cpt_enable_fdi_bc_bifurcation(dev);
5587
5588                 break;
5589         case PIPE_C:
5590                 cpt_enable_fdi_bc_bifurcation(dev);
5591
5592                 break;
5593         default:
5594                 BUG();
5595         }
5596 }
5597
5598 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5599 {
5600         /*
5601          * Account for spread spectrum to avoid
5602          * oversubscribing the link. Max center spread
5603          * is 2.5%; use 5% for safety's sake.
5604          */
5605         u32 bps = target_clock * bpp * 21 / 20;
5606         return bps / (link_bw * 8) + 1;
5607 }
5608
5609 void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5610                                   struct intel_link_m_n *m_n)
5611 {
5612         struct drm_device *dev = crtc->base.dev;
5613         struct drm_i915_private *dev_priv = dev->dev_private;
5614         int pipe = crtc->pipe;
5615
5616         I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5617         I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5618         I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5619         I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5620 }
5621
5622 void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5623                                   struct intel_link_m_n *m_n)
5624 {
5625         struct drm_device *dev = crtc->base.dev;
5626         struct drm_i915_private *dev_priv = dev->dev_private;
5627         int pipe = crtc->pipe;
5628         enum transcoder transcoder = crtc->config.cpu_transcoder;
5629
5630         if (INTEL_INFO(dev)->gen >= 5) {
5631                 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5632                 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5633                 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5634                 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5635         } else {
5636                 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5637                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5638                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5639                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5640         }
5641 }
5642
5643 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5644 {
5645         return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5646 }
5647
5648 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5649                                       u32 *fp,
5650                                       intel_clock_t *reduced_clock, u32 *fp2)
5651 {
5652         struct drm_crtc *crtc = &intel_crtc->base;
5653         struct drm_device *dev = crtc->dev;
5654         struct drm_i915_private *dev_priv = dev->dev_private;
5655         struct intel_encoder *intel_encoder;
5656         uint32_t dpll;
5657         int factor, num_connectors = 0;
5658         bool is_lvds = false, is_sdvo = false, is_tv = false;
5659
5660         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5661                 switch (intel_encoder->type) {
5662                 case INTEL_OUTPUT_LVDS:
5663                         is_lvds = true;
5664                         break;
5665                 case INTEL_OUTPUT_SDVO:
5666                 case INTEL_OUTPUT_HDMI:
5667                         is_sdvo = true;
5668                         if (intel_encoder->needs_tv_clock)
5669                                 is_tv = true;
5670                         break;
5671                 case INTEL_OUTPUT_TVOUT:
5672                         is_tv = true;
5673                         break;
5674                 }
5675
5676                 num_connectors++;
5677         }
5678
5679         /* Enable autotuning of the PLL clock (if permissible) */
5680         factor = 21;
5681         if (is_lvds) {
5682                 if ((intel_panel_use_ssc(dev_priv) &&
5683                      dev_priv->lvds_ssc_freq == 100) ||
5684                     (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5685                         factor = 25;
5686         } else if (is_sdvo && is_tv)
5687                 factor = 20;
5688
5689         if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5690                 *fp |= FP_CB_TUNE;
5691
5692         if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5693                 *fp2 |= FP_CB_TUNE;
5694
5695         dpll = 0;
5696
5697         if (is_lvds)
5698                 dpll |= DPLLB_MODE_LVDS;
5699         else
5700                 dpll |= DPLLB_MODE_DAC_SERIAL;
5701
5702         if (intel_crtc->config.pixel_multiplier > 1) {
5703                 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5704                         << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5705         }
5706
5707         if (is_sdvo)
5708                 dpll |= DPLL_DVO_HIGH_SPEED;
5709         if (intel_crtc->config.has_dp_encoder)
5710                 dpll |= DPLL_DVO_HIGH_SPEED;
5711
5712         /* compute bitmask from p1 value */
5713         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5714         /* also FPA1 */
5715         dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5716
5717         switch (intel_crtc->config.dpll.p2) {
5718         case 5:
5719                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5720                 break;
5721         case 7:
5722                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5723                 break;
5724         case 10:
5725                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5726                 break;
5727         case 14:
5728                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5729                 break;
5730         }
5731
5732         if (is_sdvo && is_tv)
5733                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5734         else if (is_tv)
5735                 /* XXX: just matching BIOS for now */
5736                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5737                 dpll |= 3;
5738         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5739                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5740         else
5741                 dpll |= PLL_REF_INPUT_DREFCLK;
5742
5743         return dpll;
5744 }
5745
5746 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5747                                   int x, int y,
5748                                   struct drm_framebuffer *fb)
5749 {
5750         struct drm_device *dev = crtc->dev;
5751         struct drm_i915_private *dev_priv = dev->dev_private;
5752         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5753         struct drm_display_mode *adjusted_mode =
5754                 &intel_crtc->config.adjusted_mode;
5755         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5756         int pipe = intel_crtc->pipe;
5757         int plane = intel_crtc->plane;
5758         int num_connectors = 0;
5759         intel_clock_t clock, reduced_clock;
5760         u32 dpll = 0, fp = 0, fp2 = 0;
5761         bool ok, has_reduced_clock = false;
5762         bool is_lvds = false;
5763         struct intel_encoder *encoder;
5764         int ret;
5765
5766         for_each_encoder_on_crtc(dev, crtc, encoder) {
5767                 switch (encoder->type) {
5768                 case INTEL_OUTPUT_LVDS:
5769                         is_lvds = true;
5770                         break;
5771                 }
5772
5773                 num_connectors++;
5774         }
5775
5776         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5777              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5778
5779         intel_crtc->config.cpu_transcoder = pipe;
5780
5781         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5782                                      &has_reduced_clock, &reduced_clock);
5783         if (!ok) {
5784                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5785                 return -EINVAL;
5786         }
5787         /* Compat-code for transition, will disappear. */
5788         if (!intel_crtc->config.clock_set) {
5789                 intel_crtc->config.dpll.n = clock.n;
5790                 intel_crtc->config.dpll.m1 = clock.m1;
5791                 intel_crtc->config.dpll.m2 = clock.m2;
5792                 intel_crtc->config.dpll.p1 = clock.p1;
5793                 intel_crtc->config.dpll.p2 = clock.p2;
5794         }
5795
5796         /* Ensure that the cursor is valid for the new mode before changing... */
5797         intel_crtc_update_cursor(crtc, true);
5798
5799         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
5800         drm_mode_debug_printmodeline(mode);
5801
5802         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5803         if (intel_crtc->config.has_pch_encoder) {
5804                 struct intel_pch_pll *pll;
5805
5806                 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5807                 if (has_reduced_clock)
5808                         fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5809
5810                 dpll = ironlake_compute_dpll(intel_crtc,
5811                                              &fp, &reduced_clock,
5812                                              has_reduced_clock ? &fp2 : NULL);
5813
5814                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5815                 if (pll == NULL) {
5816                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5817                                          pipe_name(pipe));
5818                         return -EINVAL;
5819                 }
5820         } else
5821                 intel_put_pch_pll(intel_crtc);
5822
5823         if (intel_crtc->config.has_dp_encoder)
5824                 intel_dp_set_m_n(intel_crtc);
5825
5826         for_each_encoder_on_crtc(dev, crtc, encoder)
5827                 if (encoder->pre_pll_enable)
5828                         encoder->pre_pll_enable(encoder);
5829
5830         if (intel_crtc->pch_pll) {
5831                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5832
5833                 /* Wait for the clocks to stabilize. */
5834                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5835                 udelay(150);
5836
5837                 /* The pixel multiplier can only be updated once the
5838                  * DPLL is enabled and the clocks are stable.
5839                  *
5840                  * So write it again.
5841                  */
5842                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5843         }
5844
5845         intel_crtc->lowfreq_avail = false;
5846         if (intel_crtc->pch_pll) {
5847                 if (is_lvds && has_reduced_clock && i915_powersave) {
5848                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5849                         intel_crtc->lowfreq_avail = true;
5850                 } else {
5851                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5852                 }
5853         }
5854
5855         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5856
5857         if (intel_crtc->config.has_pch_encoder) {
5858                 intel_cpu_transcoder_set_m_n(intel_crtc,
5859                                              &intel_crtc->config.fdi_m_n);
5860         }
5861
5862         if (IS_IVYBRIDGE(dev))
5863                 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5864
5865         ironlake_set_pipeconf(crtc);
5866
5867         /* Set up the display plane register */
5868         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5869         POSTING_READ(DSPCNTR(plane));
5870
5871         ret = intel_pipe_set_base(crtc, x, y, fb);
5872
5873         intel_update_watermarks(dev);
5874
5875         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5876
5877         return ret;
5878 }
5879
5880 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5881                                         struct intel_crtc_config *pipe_config)
5882 {
5883         struct drm_device *dev = crtc->base.dev;
5884         struct drm_i915_private *dev_priv = dev->dev_private;
5885         enum transcoder transcoder = pipe_config->cpu_transcoder;
5886
5887         pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5888         pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5889         pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5890                                         & ~TU_SIZE_MASK;
5891         pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5892         pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5893                                    & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5894 }
5895
5896 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5897                                      struct intel_crtc_config *pipe_config)
5898 {
5899         struct drm_device *dev = crtc->base.dev;
5900         struct drm_i915_private *dev_priv = dev->dev_private;
5901         uint32_t tmp;
5902
5903         tmp = I915_READ(PIPECONF(crtc->pipe));
5904         if (!(tmp & PIPECONF_ENABLE))
5905                 return false;
5906
5907         if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5908                 pipe_config->has_pch_encoder = true;
5909
5910                 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5911                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5912                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
5913
5914                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5915         }
5916
5917         intel_get_pipe_timings(crtc, pipe_config);
5918
5919         return true;
5920 }
5921
5922 static void haswell_modeset_global_resources(struct drm_device *dev)
5923 {
5924         bool enable = false;
5925         struct intel_crtc *crtc;
5926         struct intel_encoder *encoder;
5927
5928         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5929                 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5930                         enable = true;
5931                 /* XXX: Should check for edp transcoder here, but thanks to init
5932                  * sequence that's not yet available. Just in case desktop eDP
5933                  * on PORT D is possible on haswell, too. */
5934                 /* Even the eDP panel fitter is outside the always-on well. */
5935                 if (crtc->config.pch_pfit.size && crtc->base.enabled)
5936                         enable = true;
5937         }
5938
5939         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5940                             base.head) {
5941                 if (encoder->type != INTEL_OUTPUT_EDP &&
5942                     encoder->connectors_active)
5943                         enable = true;
5944         }
5945
5946         intel_set_power_well(dev, enable);
5947 }
5948
5949 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5950                                  int x, int y,
5951                                  struct drm_framebuffer *fb)
5952 {
5953         struct drm_device *dev = crtc->dev;
5954         struct drm_i915_private *dev_priv = dev->dev_private;
5955         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5956         struct drm_display_mode *adjusted_mode =
5957                 &intel_crtc->config.adjusted_mode;
5958         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
5959         int pipe = intel_crtc->pipe;
5960         int plane = intel_crtc->plane;
5961         int num_connectors = 0;
5962         bool is_cpu_edp = false;
5963         struct intel_encoder *encoder;
5964         int ret;
5965
5966         for_each_encoder_on_crtc(dev, crtc, encoder) {
5967                 switch (encoder->type) {
5968                 case INTEL_OUTPUT_EDP:
5969                         if (!intel_encoder_is_pch_edp(&encoder->base))
5970                                 is_cpu_edp = true;
5971                         break;
5972                 }
5973
5974                 num_connectors++;
5975         }
5976
5977         if (is_cpu_edp)
5978                 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
5979         else
5980                 intel_crtc->config.cpu_transcoder = pipe;
5981
5982         /* We are not sure yet this won't happen. */
5983         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5984              INTEL_PCH_TYPE(dev));
5985
5986         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5987              num_connectors, pipe_name(pipe));
5988
5989         WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
5990                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5991
5992         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5993
5994         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5995                 return -EINVAL;
5996
5997         /* Ensure that the cursor is valid for the new mode before changing... */
5998         intel_crtc_update_cursor(crtc, true);
5999
6000         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
6001         drm_mode_debug_printmodeline(mode);
6002
6003         if (intel_crtc->config.has_dp_encoder)
6004                 intel_dp_set_m_n(intel_crtc);
6005
6006         intel_crtc->lowfreq_avail = false;
6007
6008         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
6009
6010         if (intel_crtc->config.has_pch_encoder) {
6011                 intel_cpu_transcoder_set_m_n(intel_crtc,
6012                                              &intel_crtc->config.fdi_m_n);
6013         }
6014
6015         haswell_set_pipeconf(crtc);
6016
6017         intel_set_pipe_csc(crtc);
6018
6019         /* Set up the display plane register */
6020         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
6021         POSTING_READ(DSPCNTR(plane));
6022
6023         ret = intel_pipe_set_base(crtc, x, y, fb);
6024
6025         intel_update_watermarks(dev);
6026
6027         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
6028
6029         return ret;
6030 }
6031
6032 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6033                                     struct intel_crtc_config *pipe_config)
6034 {
6035         struct drm_device *dev = crtc->base.dev;
6036         struct drm_i915_private *dev_priv = dev->dev_private;
6037         enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
6038         uint32_t tmp;
6039
6040         if (!intel_using_power_well(dev_priv->dev) &&
6041             cpu_transcoder != TRANSCODER_EDP)
6042                 return false;
6043
6044         tmp = I915_READ(PIPECONF(cpu_transcoder));
6045         if (!(tmp & PIPECONF_ENABLE))
6046                 return false;
6047
6048         /*
6049          * Haswell has only FDI/PCH transcoder A. It is which is connected to
6050          * DDI E. So just check whether this pipe is wired to DDI E and whether
6051          * the PCH transcoder is on.
6052          */
6053         tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
6054         if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6055             I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6056                 pipe_config->has_pch_encoder = true;
6057
6058                 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6059                 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6060                                           FDI_DP_PORT_WIDTH_SHIFT) + 1;
6061
6062                 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6063         }
6064
6065         intel_get_pipe_timings(crtc, pipe_config);
6066
6067         return true;
6068 }
6069
6070 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6071                                int x, int y,
6072                                struct drm_framebuffer *fb)
6073 {
6074         struct drm_device *dev = crtc->dev;
6075         struct drm_i915_private *dev_priv = dev->dev_private;
6076         struct drm_encoder_helper_funcs *encoder_funcs;
6077         struct intel_encoder *encoder;
6078         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6079         struct drm_display_mode *adjusted_mode =
6080                 &intel_crtc->config.adjusted_mode;
6081         struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6082         int pipe = intel_crtc->pipe;
6083         int ret;
6084
6085         drm_vblank_pre_modeset(dev, pipe);
6086
6087         ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6088
6089         drm_vblank_post_modeset(dev, pipe);
6090
6091         if (ret != 0)
6092                 return ret;
6093
6094         for_each_encoder_on_crtc(dev, crtc, encoder) {
6095                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6096                         encoder->base.base.id,
6097                         drm_get_encoder_name(&encoder->base),
6098                         mode->base.id, mode->name);
6099                 if (encoder->mode_set) {
6100                         encoder->mode_set(encoder);
6101                 } else {
6102                         encoder_funcs = encoder->base.helper_private;
6103                         encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6104                 }
6105         }
6106
6107         return 0;
6108 }
6109
6110 static bool intel_eld_uptodate(struct drm_connector *connector,
6111                                int reg_eldv, uint32_t bits_eldv,
6112                                int reg_elda, uint32_t bits_elda,
6113                                int reg_edid)
6114 {
6115         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6116         uint8_t *eld = connector->eld;
6117         uint32_t i;
6118
6119         i = I915_READ(reg_eldv);
6120         i &= bits_eldv;
6121
6122         if (!eld[0])
6123                 return !i;
6124
6125         if (!i)
6126                 return false;
6127
6128         i = I915_READ(reg_elda);
6129         i &= ~bits_elda;
6130         I915_WRITE(reg_elda, i);
6131
6132         for (i = 0; i < eld[2]; i++)
6133                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6134                         return false;
6135
6136         return true;
6137 }
6138
6139 static void g4x_write_eld(struct drm_connector *connector,
6140                           struct drm_crtc *crtc)
6141 {
6142         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6143         uint8_t *eld = connector->eld;
6144         uint32_t eldv;
6145         uint32_t len;
6146         uint32_t i;
6147
6148         i = I915_READ(G4X_AUD_VID_DID);
6149
6150         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6151                 eldv = G4X_ELDV_DEVCL_DEVBLC;
6152         else
6153                 eldv = G4X_ELDV_DEVCTG;
6154
6155         if (intel_eld_uptodate(connector,
6156                                G4X_AUD_CNTL_ST, eldv,
6157                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6158                                G4X_HDMIW_HDMIEDID))
6159                 return;
6160
6161         i = I915_READ(G4X_AUD_CNTL_ST);
6162         i &= ~(eldv | G4X_ELD_ADDR);
6163         len = (i >> 9) & 0x1f;          /* ELD buffer size */
6164         I915_WRITE(G4X_AUD_CNTL_ST, i);
6165
6166         if (!eld[0])
6167                 return;
6168
6169         len = min_t(uint8_t, eld[2], len);
6170         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6171         for (i = 0; i < len; i++)
6172                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6173
6174         i = I915_READ(G4X_AUD_CNTL_ST);
6175         i |= eldv;
6176         I915_WRITE(G4X_AUD_CNTL_ST, i);
6177 }
6178
6179 static void haswell_write_eld(struct drm_connector *connector,
6180                                      struct drm_crtc *crtc)
6181 {
6182         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6183         uint8_t *eld = connector->eld;
6184         struct drm_device *dev = crtc->dev;
6185         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6186         uint32_t eldv;
6187         uint32_t i;
6188         int len;
6189         int pipe = to_intel_crtc(crtc)->pipe;
6190         int tmp;
6191
6192         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6193         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6194         int aud_config = HSW_AUD_CFG(pipe);
6195         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6196
6197
6198         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6199
6200         /* Audio output enable */
6201         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6202         tmp = I915_READ(aud_cntrl_st2);
6203         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6204         I915_WRITE(aud_cntrl_st2, tmp);
6205
6206         /* Wait for 1 vertical blank */
6207         intel_wait_for_vblank(dev, pipe);
6208
6209         /* Set ELD valid state */
6210         tmp = I915_READ(aud_cntrl_st2);
6211         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6212         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6213         I915_WRITE(aud_cntrl_st2, tmp);
6214         tmp = I915_READ(aud_cntrl_st2);
6215         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6216
6217         /* Enable HDMI mode */
6218         tmp = I915_READ(aud_config);
6219         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6220         /* clear N_programing_enable and N_value_index */
6221         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6222         I915_WRITE(aud_config, tmp);
6223
6224         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6225
6226         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6227         intel_crtc->eld_vld = true;
6228
6229         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6230                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6231                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6232                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6233         } else
6234                 I915_WRITE(aud_config, 0);
6235
6236         if (intel_eld_uptodate(connector,
6237                                aud_cntrl_st2, eldv,
6238                                aud_cntl_st, IBX_ELD_ADDRESS,
6239                                hdmiw_hdmiedid))
6240                 return;
6241
6242         i = I915_READ(aud_cntrl_st2);
6243         i &= ~eldv;
6244         I915_WRITE(aud_cntrl_st2, i);
6245
6246         if (!eld[0])
6247                 return;
6248
6249         i = I915_READ(aud_cntl_st);
6250         i &= ~IBX_ELD_ADDRESS;
6251         I915_WRITE(aud_cntl_st, i);
6252         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6253         DRM_DEBUG_DRIVER("port num:%d\n", i);
6254
6255         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6256         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6257         for (i = 0; i < len; i++)
6258                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6259
6260         i = I915_READ(aud_cntrl_st2);
6261         i |= eldv;
6262         I915_WRITE(aud_cntrl_st2, i);
6263
6264 }
6265
6266 static void ironlake_write_eld(struct drm_connector *connector,
6267                                      struct drm_crtc *crtc)
6268 {
6269         struct drm_i915_private *dev_priv = connector->dev->dev_private;
6270         uint8_t *eld = connector->eld;
6271         uint32_t eldv;
6272         uint32_t i;
6273         int len;
6274         int hdmiw_hdmiedid;
6275         int aud_config;
6276         int aud_cntl_st;
6277         int aud_cntrl_st2;
6278         int pipe = to_intel_crtc(crtc)->pipe;
6279
6280         if (HAS_PCH_IBX(connector->dev)) {
6281                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6282                 aud_config = IBX_AUD_CFG(pipe);
6283                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6284                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6285         } else {
6286                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6287                 aud_config = CPT_AUD_CFG(pipe);
6288                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6289                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6290         }
6291
6292         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6293
6294         i = I915_READ(aud_cntl_st);
6295         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
6296         if (!i) {
6297                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6298                 /* operate blindly on all ports */
6299                 eldv = IBX_ELD_VALIDB;
6300                 eldv |= IBX_ELD_VALIDB << 4;
6301                 eldv |= IBX_ELD_VALIDB << 8;
6302         } else {
6303                 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6304                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6305         }
6306
6307         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6308                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6309                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
6310                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6311         } else
6312                 I915_WRITE(aud_config, 0);
6313
6314         if (intel_eld_uptodate(connector,
6315                                aud_cntrl_st2, eldv,
6316                                aud_cntl_st, IBX_ELD_ADDRESS,
6317                                hdmiw_hdmiedid))
6318                 return;
6319
6320         i = I915_READ(aud_cntrl_st2);
6321         i &= ~eldv;
6322         I915_WRITE(aud_cntrl_st2, i);
6323
6324         if (!eld[0])
6325                 return;
6326
6327         i = I915_READ(aud_cntl_st);
6328         i &= ~IBX_ELD_ADDRESS;
6329         I915_WRITE(aud_cntl_st, i);
6330
6331         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
6332         DRM_DEBUG_DRIVER("ELD size %d\n", len);
6333         for (i = 0; i < len; i++)
6334                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6335
6336         i = I915_READ(aud_cntrl_st2);
6337         i |= eldv;
6338         I915_WRITE(aud_cntrl_st2, i);
6339 }
6340
6341 void intel_write_eld(struct drm_encoder *encoder,
6342                      struct drm_display_mode *mode)
6343 {
6344         struct drm_crtc *crtc = encoder->crtc;
6345         struct drm_connector *connector;
6346         struct drm_device *dev = encoder->dev;
6347         struct drm_i915_private *dev_priv = dev->dev_private;
6348
6349         connector = drm_select_eld(encoder, mode);
6350         if (!connector)
6351                 return;
6352
6353         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6354                          connector->base.id,
6355                          drm_get_connector_name(connector),
6356                          connector->encoder->base.id,
6357                          drm_get_encoder_name(connector->encoder));
6358
6359         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6360
6361         if (dev_priv->display.write_eld)
6362                 dev_priv->display.write_eld(connector, crtc);
6363 }
6364
6365 /** Loads the palette/gamma unit for the CRTC with the prepared values */
6366 void intel_crtc_load_lut(struct drm_crtc *crtc)
6367 {
6368         struct drm_device *dev = crtc->dev;
6369         struct drm_i915_private *dev_priv = dev->dev_private;
6370         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6371         int palreg = PALETTE(intel_crtc->pipe);
6372         int i;
6373
6374         /* The clocks have to be on to load the palette. */
6375         if (!crtc->enabled || !intel_crtc->active)
6376                 return;
6377
6378         /* use legacy palette for Ironlake */
6379         if (HAS_PCH_SPLIT(dev))
6380                 palreg = LGC_PALETTE(intel_crtc->pipe);
6381
6382         for (i = 0; i < 256; i++) {
6383                 I915_WRITE(palreg + 4 * i,
6384                            (intel_crtc->lut_r[i] << 16) |
6385                            (intel_crtc->lut_g[i] << 8) |
6386                            intel_crtc->lut_b[i]);
6387         }
6388 }
6389
6390 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6391 {
6392         struct drm_device *dev = crtc->dev;
6393         struct drm_i915_private *dev_priv = dev->dev_private;
6394         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6395         bool visible = base != 0;
6396         u32 cntl;
6397
6398         if (intel_crtc->cursor_visible == visible)
6399                 return;
6400
6401         cntl = I915_READ(_CURACNTR);
6402         if (visible) {
6403                 /* On these chipsets we can only modify the base whilst
6404                  * the cursor is disabled.
6405                  */
6406                 I915_WRITE(_CURABASE, base);
6407
6408                 cntl &= ~(CURSOR_FORMAT_MASK);
6409                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6410                 cntl |= CURSOR_ENABLE |
6411                         CURSOR_GAMMA_ENABLE |
6412                         CURSOR_FORMAT_ARGB;
6413         } else
6414                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6415         I915_WRITE(_CURACNTR, cntl);
6416
6417         intel_crtc->cursor_visible = visible;
6418 }
6419
6420 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6421 {
6422         struct drm_device *dev = crtc->dev;
6423         struct drm_i915_private *dev_priv = dev->dev_private;
6424         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6425         int pipe = intel_crtc->pipe;
6426         bool visible = base != 0;
6427
6428         if (intel_crtc->cursor_visible != visible) {
6429                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6430                 if (base) {
6431                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6432                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6433                         cntl |= pipe << 28; /* Connect to correct pipe */
6434                 } else {
6435                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6436                         cntl |= CURSOR_MODE_DISABLE;
6437                 }
6438                 I915_WRITE(CURCNTR(pipe), cntl);
6439
6440                 intel_crtc->cursor_visible = visible;
6441         }
6442         /* and commit changes on next vblank */
6443         I915_WRITE(CURBASE(pipe), base);
6444 }
6445
6446 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6447 {
6448         struct drm_device *dev = crtc->dev;
6449         struct drm_i915_private *dev_priv = dev->dev_private;
6450         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6451         int pipe = intel_crtc->pipe;
6452         bool visible = base != 0;
6453
6454         if (intel_crtc->cursor_visible != visible) {
6455                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6456                 if (base) {
6457                         cntl &= ~CURSOR_MODE;
6458                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6459                 } else {
6460                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6461                         cntl |= CURSOR_MODE_DISABLE;
6462                 }
6463                 if (IS_HASWELL(dev))
6464                         cntl |= CURSOR_PIPE_CSC_ENABLE;
6465                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6466
6467                 intel_crtc->cursor_visible = visible;
6468         }
6469         /* and commit changes on next vblank */
6470         I915_WRITE(CURBASE_IVB(pipe), base);
6471 }
6472
6473 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6474 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6475                                      bool on)
6476 {
6477         struct drm_device *dev = crtc->dev;
6478         struct drm_i915_private *dev_priv = dev->dev_private;
6479         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6480         int pipe = intel_crtc->pipe;
6481         int x = intel_crtc->cursor_x;
6482         int y = intel_crtc->cursor_y;
6483         u32 base, pos;
6484         bool visible;
6485
6486         pos = 0;
6487
6488         if (on && crtc->enabled && crtc->fb) {
6489                 base = intel_crtc->cursor_addr;
6490                 if (x > (int) crtc->fb->width)
6491                         base = 0;
6492
6493                 if (y > (int) crtc->fb->height)
6494                         base = 0;
6495         } else
6496                 base = 0;
6497
6498         if (x < 0) {
6499                 if (x + intel_crtc->cursor_width < 0)
6500                         base = 0;
6501
6502                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6503                 x = -x;
6504         }
6505         pos |= x << CURSOR_X_SHIFT;
6506
6507         if (y < 0) {
6508                 if (y + intel_crtc->cursor_height < 0)
6509                         base = 0;
6510
6511                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6512                 y = -y;
6513         }
6514         pos |= y << CURSOR_Y_SHIFT;
6515
6516         visible = base != 0;
6517         if (!visible && !intel_crtc->cursor_visible)
6518                 return;
6519
6520         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6521                 I915_WRITE(CURPOS_IVB(pipe), pos);
6522                 ivb_update_cursor(crtc, base);
6523         } else {
6524                 I915_WRITE(CURPOS(pipe), pos);
6525                 if (IS_845G(dev) || IS_I865G(dev))
6526                         i845_update_cursor(crtc, base);
6527                 else
6528                         i9xx_update_cursor(crtc, base);
6529         }
6530 }
6531
6532 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6533                                  struct drm_file *file,
6534                                  uint32_t handle,
6535                                  uint32_t width, uint32_t height)
6536 {
6537         struct drm_device *dev = crtc->dev;
6538         struct drm_i915_private *dev_priv = dev->dev_private;
6539         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6540         struct drm_i915_gem_object *obj;
6541         uint32_t addr;
6542         int ret;
6543
6544         /* if we want to turn off the cursor ignore width and height */
6545         if (!handle) {
6546                 DRM_DEBUG_KMS("cursor off\n");
6547                 addr = 0;
6548                 obj = NULL;
6549                 mutex_lock(&dev->struct_mutex);
6550                 goto finish;
6551         }
6552
6553         /* Currently we only support 64x64 cursors */
6554         if (width != 64 || height != 64) {
6555                 DRM_ERROR("we currently only support 64x64 cursors\n");
6556                 return -EINVAL;
6557         }
6558
6559         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6560         if (&obj->base == NULL)
6561                 return -ENOENT;
6562
6563         if (obj->base.size < width * height * 4) {
6564                 DRM_ERROR("buffer is to small\n");
6565                 ret = -ENOMEM;
6566                 goto fail;
6567         }
6568
6569         /* we only need to pin inside GTT if cursor is non-phy */
6570         mutex_lock(&dev->struct_mutex);
6571         if (!dev_priv->info->cursor_needs_physical) {
6572                 unsigned alignment;
6573
6574                 if (obj->tiling_mode) {
6575                         DRM_ERROR("cursor cannot be tiled\n");
6576                         ret = -EINVAL;
6577                         goto fail_locked;
6578                 }
6579
6580                 /* Note that the w/a also requires 2 PTE of padding following
6581                  * the bo. We currently fill all unused PTE with the shadow
6582                  * page and so we should always have valid PTE following the
6583                  * cursor preventing the VT-d warning.
6584                  */
6585                 alignment = 0;
6586                 if (need_vtd_wa(dev))
6587                         alignment = 64*1024;
6588
6589                 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6590                 if (ret) {
6591                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6592                         goto fail_locked;
6593                 }
6594
6595                 ret = i915_gem_object_put_fence(obj);
6596                 if (ret) {
6597                         DRM_ERROR("failed to release fence for cursor");
6598                         goto fail_unpin;
6599                 }
6600
6601                 addr = obj->gtt_offset;
6602         } else {
6603                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6604                 ret = i915_gem_attach_phys_object(dev, obj,
6605                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6606                                                   align);
6607                 if (ret) {
6608                         DRM_ERROR("failed to attach phys object\n");
6609                         goto fail_locked;
6610                 }
6611                 addr = obj->phys_obj->handle->busaddr;
6612         }
6613
6614         if (IS_GEN2(dev))
6615                 I915_WRITE(CURSIZE, (height << 12) | width);
6616
6617  finish:
6618         if (intel_crtc->cursor_bo) {
6619                 if (dev_priv->info->cursor_needs_physical) {
6620                         if (intel_crtc->cursor_bo != obj)
6621                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6622                 } else
6623                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6624                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6625         }
6626
6627         mutex_unlock(&dev->struct_mutex);
6628
6629         intel_crtc->cursor_addr = addr;
6630         intel_crtc->cursor_bo = obj;
6631         intel_crtc->cursor_width = width;
6632         intel_crtc->cursor_height = height;
6633
6634         intel_crtc_update_cursor(crtc, true);
6635
6636         return 0;
6637 fail_unpin:
6638         i915_gem_object_unpin(obj);
6639 fail_locked:
6640         mutex_unlock(&dev->struct_mutex);
6641 fail:
6642         drm_gem_object_unreference_unlocked(&obj->base);
6643         return ret;
6644 }
6645
6646 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6647 {
6648         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6649
6650         intel_crtc->cursor_x = x;
6651         intel_crtc->cursor_y = y;
6652
6653         intel_crtc_update_cursor(crtc, true);
6654
6655         return 0;
6656 }
6657
6658 /** Sets the color ramps on behalf of RandR */
6659 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6660                                  u16 blue, int regno)
6661 {
6662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6663
6664         intel_crtc->lut_r[regno] = red >> 8;
6665         intel_crtc->lut_g[regno] = green >> 8;
6666         intel_crtc->lut_b[regno] = blue >> 8;
6667 }
6668
6669 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6670                              u16 *blue, int regno)
6671 {
6672         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6673
6674         *red = intel_crtc->lut_r[regno] << 8;
6675         *green = intel_crtc->lut_g[regno] << 8;
6676         *blue = intel_crtc->lut_b[regno] << 8;
6677 }
6678
6679 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6680                                  u16 *blue, uint32_t start, uint32_t size)
6681 {
6682         int end = (start + size > 256) ? 256 : start + size, i;
6683         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6684
6685         for (i = start; i < end; i++) {
6686                 intel_crtc->lut_r[i] = red[i] >> 8;
6687                 intel_crtc->lut_g[i] = green[i] >> 8;
6688                 intel_crtc->lut_b[i] = blue[i] >> 8;
6689         }
6690
6691         intel_crtc_load_lut(crtc);
6692 }
6693
6694 /* VESA 640x480x72Hz mode to set on the pipe */
6695 static struct drm_display_mode load_detect_mode = {
6696         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6697                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6698 };
6699
6700 static struct drm_framebuffer *
6701 intel_framebuffer_create(struct drm_device *dev,
6702                          struct drm_mode_fb_cmd2 *mode_cmd,
6703                          struct drm_i915_gem_object *obj)
6704 {
6705         struct intel_framebuffer *intel_fb;
6706         int ret;
6707
6708         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6709         if (!intel_fb) {
6710                 drm_gem_object_unreference_unlocked(&obj->base);
6711                 return ERR_PTR(-ENOMEM);
6712         }
6713
6714         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6715         if (ret) {
6716                 drm_gem_object_unreference_unlocked(&obj->base);
6717                 kfree(intel_fb);
6718                 return ERR_PTR(ret);
6719         }
6720
6721         return &intel_fb->base;
6722 }
6723
6724 static u32
6725 intel_framebuffer_pitch_for_width(int width, int bpp)
6726 {
6727         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6728         return ALIGN(pitch, 64);
6729 }
6730
6731 static u32
6732 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6733 {
6734         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6735         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6736 }
6737
6738 static struct drm_framebuffer *
6739 intel_framebuffer_create_for_mode(struct drm_device *dev,
6740                                   struct drm_display_mode *mode,
6741                                   int depth, int bpp)
6742 {
6743         struct drm_i915_gem_object *obj;
6744         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6745
6746         obj = i915_gem_alloc_object(dev,
6747                                     intel_framebuffer_size_for_mode(mode, bpp));
6748         if (obj == NULL)
6749                 return ERR_PTR(-ENOMEM);
6750
6751         mode_cmd.width = mode->hdisplay;
6752         mode_cmd.height = mode->vdisplay;
6753         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6754                                                                 bpp);
6755         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6756
6757         return intel_framebuffer_create(dev, &mode_cmd, obj);
6758 }
6759
6760 static struct drm_framebuffer *
6761 mode_fits_in_fbdev(struct drm_device *dev,
6762                    struct drm_display_mode *mode)
6763 {
6764         struct drm_i915_private *dev_priv = dev->dev_private;
6765         struct drm_i915_gem_object *obj;
6766         struct drm_framebuffer *fb;
6767
6768         if (dev_priv->fbdev == NULL)
6769                 return NULL;
6770
6771         obj = dev_priv->fbdev->ifb.obj;
6772         if (obj == NULL)
6773                 return NULL;
6774
6775         fb = &dev_priv->fbdev->ifb.base;
6776         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6777                                                                fb->bits_per_pixel))
6778                 return NULL;
6779
6780         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6781                 return NULL;
6782
6783         return fb;
6784 }
6785
6786 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6787                                 struct drm_display_mode *mode,
6788                                 struct intel_load_detect_pipe *old)
6789 {
6790         struct intel_crtc *intel_crtc;
6791         struct intel_encoder *intel_encoder =
6792                 intel_attached_encoder(connector);
6793         struct drm_crtc *possible_crtc;
6794         struct drm_encoder *encoder = &intel_encoder->base;
6795         struct drm_crtc *crtc = NULL;
6796         struct drm_device *dev = encoder->dev;
6797         struct drm_framebuffer *fb;
6798         int i = -1;
6799
6800         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6801                       connector->base.id, drm_get_connector_name(connector),
6802                       encoder->base.id, drm_get_encoder_name(encoder));
6803
6804         /*
6805          * Algorithm gets a little messy:
6806          *
6807          *   - if the connector already has an assigned crtc, use it (but make
6808          *     sure it's on first)
6809          *
6810          *   - try to find the first unused crtc that can drive this connector,
6811          *     and use that if we find one
6812          */
6813
6814         /* See if we already have a CRTC for this connector */
6815         if (encoder->crtc) {
6816                 crtc = encoder->crtc;
6817
6818                 mutex_lock(&crtc->mutex);
6819
6820                 old->dpms_mode = connector->dpms;
6821                 old->load_detect_temp = false;
6822
6823                 /* Make sure the crtc and connector are running */
6824                 if (connector->dpms != DRM_MODE_DPMS_ON)
6825                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6826
6827                 return true;
6828         }
6829
6830         /* Find an unused one (if possible) */
6831         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6832                 i++;
6833                 if (!(encoder->possible_crtcs & (1 << i)))
6834                         continue;
6835                 if (!possible_crtc->enabled) {
6836                         crtc = possible_crtc;
6837                         break;
6838                 }
6839         }
6840
6841         /*
6842          * If we didn't find an unused CRTC, don't use any.
6843          */
6844         if (!crtc) {
6845                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6846                 return false;
6847         }
6848
6849         mutex_lock(&crtc->mutex);
6850         intel_encoder->new_crtc = to_intel_crtc(crtc);
6851         to_intel_connector(connector)->new_encoder = intel_encoder;
6852
6853         intel_crtc = to_intel_crtc(crtc);
6854         old->dpms_mode = connector->dpms;
6855         old->load_detect_temp = true;
6856         old->release_fb = NULL;
6857
6858         if (!mode)
6859                 mode = &load_detect_mode;
6860
6861         /* We need a framebuffer large enough to accommodate all accesses
6862          * that the plane may generate whilst we perform load detection.
6863          * We can not rely on the fbcon either being present (we get called
6864          * during its initialisation to detect all boot displays, or it may
6865          * not even exist) or that it is large enough to satisfy the
6866          * requested mode.
6867          */
6868         fb = mode_fits_in_fbdev(dev, mode);
6869         if (fb == NULL) {
6870                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6871                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6872                 old->release_fb = fb;
6873         } else
6874                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6875         if (IS_ERR(fb)) {
6876                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6877                 mutex_unlock(&crtc->mutex);
6878                 return false;
6879         }
6880
6881         if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6882                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6883                 if (old->release_fb)
6884                         old->release_fb->funcs->destroy(old->release_fb);
6885                 mutex_unlock(&crtc->mutex);
6886                 return false;
6887         }
6888
6889         /* let the connector get through one full cycle before testing */
6890         intel_wait_for_vblank(dev, intel_crtc->pipe);
6891         return true;
6892 }
6893
6894 void intel_release_load_detect_pipe(struct drm_connector *connector,
6895                                     struct intel_load_detect_pipe *old)
6896 {
6897         struct intel_encoder *intel_encoder =
6898                 intel_attached_encoder(connector);
6899         struct drm_encoder *encoder = &intel_encoder->base;
6900         struct drm_crtc *crtc = encoder->crtc;
6901
6902         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6903                       connector->base.id, drm_get_connector_name(connector),
6904                       encoder->base.id, drm_get_encoder_name(encoder));
6905
6906         if (old->load_detect_temp) {
6907                 to_intel_connector(connector)->new_encoder = NULL;
6908                 intel_encoder->new_crtc = NULL;
6909                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6910
6911                 if (old->release_fb) {
6912                         drm_framebuffer_unregister_private(old->release_fb);
6913                         drm_framebuffer_unreference(old->release_fb);
6914                 }
6915
6916                 mutex_unlock(&crtc->mutex);
6917                 return;
6918         }
6919
6920         /* Switch crtc and encoder back off if necessary */
6921         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6922                 connector->funcs->dpms(connector, old->dpms_mode);
6923
6924         mutex_unlock(&crtc->mutex);
6925 }
6926
6927 /* Returns the clock of the currently programmed mode of the given pipe. */
6928 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6929 {
6930         struct drm_i915_private *dev_priv = dev->dev_private;
6931         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6932         int pipe = intel_crtc->pipe;
6933         u32 dpll = I915_READ(DPLL(pipe));
6934         u32 fp;
6935         intel_clock_t clock;
6936
6937         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6938                 fp = I915_READ(FP0(pipe));
6939         else
6940                 fp = I915_READ(FP1(pipe));
6941
6942         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6943         if (IS_PINEVIEW(dev)) {
6944                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6945                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6946         } else {
6947                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6948                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6949         }
6950
6951         if (!IS_GEN2(dev)) {
6952                 if (IS_PINEVIEW(dev))
6953                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6954                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6955                 else
6956                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6957                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6958
6959                 switch (dpll & DPLL_MODE_MASK) {
6960                 case DPLLB_MODE_DAC_SERIAL:
6961                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6962                                 5 : 10;
6963                         break;
6964                 case DPLLB_MODE_LVDS:
6965                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6966                                 7 : 14;
6967                         break;
6968                 default:
6969                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6970                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6971                         return 0;
6972                 }
6973
6974                 /* XXX: Handle the 100Mhz refclk */
6975                 intel_clock(dev, 96000, &clock);
6976         } else {
6977                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6978
6979                 if (is_lvds) {
6980                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6981                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6982                         clock.p2 = 14;
6983
6984                         if ((dpll & PLL_REF_INPUT_MASK) ==
6985                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6986                                 /* XXX: might not be 66MHz */
6987                                 intel_clock(dev, 66000, &clock);
6988                         } else
6989                                 intel_clock(dev, 48000, &clock);
6990                 } else {
6991                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6992                                 clock.p1 = 2;
6993                         else {
6994                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6995                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6996                         }
6997                         if (dpll & PLL_P2_DIVIDE_BY_4)
6998                                 clock.p2 = 4;
6999                         else
7000                                 clock.p2 = 2;
7001
7002                         intel_clock(dev, 48000, &clock);
7003                 }
7004         }
7005
7006         /* XXX: It would be nice to validate the clocks, but we can't reuse
7007          * i830PllIsValid() because it relies on the xf86_config connector
7008          * configuration being accurate, which it isn't necessarily.
7009          */
7010
7011         return clock.dot;
7012 }
7013
7014 /** Returns the currently programmed mode of the given pipe. */
7015 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7016                                              struct drm_crtc *crtc)
7017 {
7018         struct drm_i915_private *dev_priv = dev->dev_private;
7019         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7020         enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7021         struct drm_display_mode *mode;
7022         int htot = I915_READ(HTOTAL(cpu_transcoder));
7023         int hsync = I915_READ(HSYNC(cpu_transcoder));
7024         int vtot = I915_READ(VTOTAL(cpu_transcoder));
7025         int vsync = I915_READ(VSYNC(cpu_transcoder));
7026
7027         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7028         if (!mode)
7029                 return NULL;
7030
7031         mode->clock = intel_crtc_clock_get(dev, crtc);
7032         mode->hdisplay = (htot & 0xffff) + 1;
7033         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7034         mode->hsync_start = (hsync & 0xffff) + 1;
7035         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7036         mode->vdisplay = (vtot & 0xffff) + 1;
7037         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7038         mode->vsync_start = (vsync & 0xffff) + 1;
7039         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7040
7041         drm_mode_set_name(mode);
7042
7043         return mode;
7044 }
7045
7046 static void intel_increase_pllclock(struct drm_crtc *crtc)
7047 {
7048         struct drm_device *dev = crtc->dev;
7049         drm_i915_private_t *dev_priv = dev->dev_private;
7050         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7051         int pipe = intel_crtc->pipe;
7052         int dpll_reg = DPLL(pipe);
7053         int dpll;
7054
7055         if (HAS_PCH_SPLIT(dev))
7056                 return;
7057
7058         if (!dev_priv->lvds_downclock_avail)
7059                 return;
7060
7061         dpll = I915_READ(dpll_reg);
7062         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7063                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7064
7065                 assert_panel_unlocked(dev_priv, pipe);
7066
7067                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7068                 I915_WRITE(dpll_reg, dpll);
7069                 intel_wait_for_vblank(dev, pipe);
7070
7071                 dpll = I915_READ(dpll_reg);
7072                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7073                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7074         }
7075 }
7076
7077 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7078 {
7079         struct drm_device *dev = crtc->dev;
7080         drm_i915_private_t *dev_priv = dev->dev_private;
7081         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7082
7083         if (HAS_PCH_SPLIT(dev))
7084                 return;
7085
7086         if (!dev_priv->lvds_downclock_avail)
7087                 return;
7088
7089         /*
7090          * Since this is called by a timer, we should never get here in
7091          * the manual case.
7092          */
7093         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7094                 int pipe = intel_crtc->pipe;
7095                 int dpll_reg = DPLL(pipe);
7096                 int dpll;
7097
7098                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7099
7100                 assert_panel_unlocked(dev_priv, pipe);
7101
7102                 dpll = I915_READ(dpll_reg);
7103                 dpll |= DISPLAY_RATE_SELECT_FPA1;
7104                 I915_WRITE(dpll_reg, dpll);
7105                 intel_wait_for_vblank(dev, pipe);
7106                 dpll = I915_READ(dpll_reg);
7107                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7108                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7109         }
7110
7111 }
7112
7113 void intel_mark_busy(struct drm_device *dev)
7114 {
7115         i915_update_gfx_val(dev->dev_private);
7116 }
7117
7118 void intel_mark_idle(struct drm_device *dev)
7119 {
7120         struct drm_crtc *crtc;
7121
7122         if (!i915_powersave)
7123                 return;
7124
7125         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7126                 if (!crtc->fb)
7127                         continue;
7128
7129                 intel_decrease_pllclock(crtc);
7130         }
7131 }
7132
7133 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
7134 {
7135         struct drm_device *dev = obj->base.dev;
7136         struct drm_crtc *crtc;
7137
7138         if (!i915_powersave)
7139                 return;
7140
7141         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7142                 if (!crtc->fb)
7143                         continue;
7144
7145                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
7146                         intel_increase_pllclock(crtc);
7147         }
7148 }
7149
7150 static void intel_crtc_destroy(struct drm_crtc *crtc)
7151 {
7152         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7153         struct drm_device *dev = crtc->dev;
7154         struct intel_unpin_work *work;
7155         unsigned long flags;
7156
7157         spin_lock_irqsave(&dev->event_lock, flags);
7158         work = intel_crtc->unpin_work;
7159         intel_crtc->unpin_work = NULL;
7160         spin_unlock_irqrestore(&dev->event_lock, flags);
7161
7162         if (work) {
7163                 cancel_work_sync(&work->work);
7164                 kfree(work);
7165         }
7166
7167         drm_crtc_cleanup(crtc);
7168
7169         kfree(intel_crtc);
7170 }
7171
7172 static void intel_unpin_work_fn(struct work_struct *__work)
7173 {
7174         struct intel_unpin_work *work =
7175                 container_of(__work, struct intel_unpin_work, work);
7176         struct drm_device *dev = work->crtc->dev;
7177
7178         mutex_lock(&dev->struct_mutex);
7179         intel_unpin_fb_obj(work->old_fb_obj);
7180         drm_gem_object_unreference(&work->pending_flip_obj->base);
7181         drm_gem_object_unreference(&work->old_fb_obj->base);
7182
7183         intel_update_fbc(dev);
7184         mutex_unlock(&dev->struct_mutex);
7185
7186         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7187         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7188
7189         kfree(work);
7190 }
7191
7192 static void do_intel_finish_page_flip(struct drm_device *dev,
7193                                       struct drm_crtc *crtc)
7194 {
7195         drm_i915_private_t *dev_priv = dev->dev_private;
7196         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7197         struct intel_unpin_work *work;
7198         unsigned long flags;
7199
7200         /* Ignore early vblank irqs */
7201         if (intel_crtc == NULL)
7202                 return;
7203
7204         spin_lock_irqsave(&dev->event_lock, flags);
7205         work = intel_crtc->unpin_work;
7206
7207         /* Ensure we don't miss a work->pending update ... */
7208         smp_rmb();
7209
7210         if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7211                 spin_unlock_irqrestore(&dev->event_lock, flags);
7212                 return;
7213         }
7214
7215         /* and that the unpin work is consistent wrt ->pending. */
7216         smp_rmb();
7217
7218         intel_crtc->unpin_work = NULL;
7219
7220         if (work->event)
7221                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7222
7223         drm_vblank_put(dev, intel_crtc->pipe);
7224
7225         spin_unlock_irqrestore(&dev->event_lock, flags);
7226
7227         wake_up_all(&dev_priv->pending_flip_queue);
7228
7229         queue_work(dev_priv->wq, &work->work);
7230
7231         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
7232 }
7233
7234 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7235 {
7236         drm_i915_private_t *dev_priv = dev->dev_private;
7237         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7238
7239         do_intel_finish_page_flip(dev, crtc);
7240 }
7241
7242 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7243 {
7244         drm_i915_private_t *dev_priv = dev->dev_private;
7245         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7246
7247         do_intel_finish_page_flip(dev, crtc);
7248 }
7249
7250 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7251 {
7252         drm_i915_private_t *dev_priv = dev->dev_private;
7253         struct intel_crtc *intel_crtc =
7254                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7255         unsigned long flags;
7256
7257         /* NB: An MMIO update of the plane base pointer will also
7258          * generate a page-flip completion irq, i.e. every modeset
7259          * is also accompanied by a spurious intel_prepare_page_flip().
7260          */
7261         spin_lock_irqsave(&dev->event_lock, flags);
7262         if (intel_crtc->unpin_work)
7263                 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7264         spin_unlock_irqrestore(&dev->event_lock, flags);
7265 }
7266
7267 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7268 {
7269         /* Ensure that the work item is consistent when activating it ... */
7270         smp_wmb();
7271         atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7272         /* and that it is marked active as soon as the irq could fire. */
7273         smp_wmb();
7274 }
7275
7276 static int intel_gen2_queue_flip(struct drm_device *dev,
7277                                  struct drm_crtc *crtc,
7278                                  struct drm_framebuffer *fb,
7279                                  struct drm_i915_gem_object *obj)
7280 {
7281         struct drm_i915_private *dev_priv = dev->dev_private;
7282         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7283         u32 flip_mask;
7284         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7285         int ret;
7286
7287         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7288         if (ret)
7289                 goto err;
7290
7291         ret = intel_ring_begin(ring, 6);
7292         if (ret)
7293                 goto err_unpin;
7294
7295         /* Can't queue multiple flips, so wait for the previous
7296          * one to finish before executing the next.
7297          */
7298         if (intel_crtc->plane)
7299                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7300         else
7301                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7302         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7303         intel_ring_emit(ring, MI_NOOP);
7304         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7305                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7306         intel_ring_emit(ring, fb->pitches[0]);
7307         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7308         intel_ring_emit(ring, 0); /* aux display base address, unused */
7309
7310         intel_mark_page_flip_active(intel_crtc);
7311         intel_ring_advance(ring);
7312         return 0;
7313
7314 err_unpin:
7315         intel_unpin_fb_obj(obj);
7316 err:
7317         return ret;
7318 }
7319
7320 static int intel_gen3_queue_flip(struct drm_device *dev,
7321                                  struct drm_crtc *crtc,
7322                                  struct drm_framebuffer *fb,
7323                                  struct drm_i915_gem_object *obj)
7324 {
7325         struct drm_i915_private *dev_priv = dev->dev_private;
7326         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7327         u32 flip_mask;
7328         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7329         int ret;
7330
7331         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7332         if (ret)
7333                 goto err;
7334
7335         ret = intel_ring_begin(ring, 6);
7336         if (ret)
7337                 goto err_unpin;
7338
7339         if (intel_crtc->plane)
7340                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7341         else
7342                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7343         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7344         intel_ring_emit(ring, MI_NOOP);
7345         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7346                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7347         intel_ring_emit(ring, fb->pitches[0]);
7348         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7349         intel_ring_emit(ring, MI_NOOP);
7350
7351         intel_mark_page_flip_active(intel_crtc);
7352         intel_ring_advance(ring);
7353         return 0;
7354
7355 err_unpin:
7356         intel_unpin_fb_obj(obj);
7357 err:
7358         return ret;
7359 }
7360
7361 static int intel_gen4_queue_flip(struct drm_device *dev,
7362                                  struct drm_crtc *crtc,
7363                                  struct drm_framebuffer *fb,
7364                                  struct drm_i915_gem_object *obj)
7365 {
7366         struct drm_i915_private *dev_priv = dev->dev_private;
7367         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7368         uint32_t pf, pipesrc;
7369         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7370         int ret;
7371
7372         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7373         if (ret)
7374                 goto err;
7375
7376         ret = intel_ring_begin(ring, 4);
7377         if (ret)
7378                 goto err_unpin;
7379
7380         /* i965+ uses the linear or tiled offsets from the
7381          * Display Registers (which do not change across a page-flip)
7382          * so we need only reprogram the base address.
7383          */
7384         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7385                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7386         intel_ring_emit(ring, fb->pitches[0]);
7387         intel_ring_emit(ring,
7388                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7389                         obj->tiling_mode);
7390
7391         /* XXX Enabling the panel-fitter across page-flip is so far
7392          * untested on non-native modes, so ignore it for now.
7393          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7394          */
7395         pf = 0;
7396         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7397         intel_ring_emit(ring, pf | pipesrc);
7398
7399         intel_mark_page_flip_active(intel_crtc);
7400         intel_ring_advance(ring);
7401         return 0;
7402
7403 err_unpin:
7404         intel_unpin_fb_obj(obj);
7405 err:
7406         return ret;
7407 }
7408
7409 static int intel_gen6_queue_flip(struct drm_device *dev,
7410                                  struct drm_crtc *crtc,
7411                                  struct drm_framebuffer *fb,
7412                                  struct drm_i915_gem_object *obj)
7413 {
7414         struct drm_i915_private *dev_priv = dev->dev_private;
7415         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7416         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7417         uint32_t pf, pipesrc;
7418         int ret;
7419
7420         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7421         if (ret)
7422                 goto err;
7423
7424         ret = intel_ring_begin(ring, 4);
7425         if (ret)
7426                 goto err_unpin;
7427
7428         intel_ring_emit(ring, MI_DISPLAY_FLIP |
7429                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7430         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7431         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7432
7433         /* Contrary to the suggestions in the documentation,
7434          * "Enable Panel Fitter" does not seem to be required when page
7435          * flipping with a non-native mode, and worse causes a normal
7436          * modeset to fail.
7437          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7438          */
7439         pf = 0;
7440         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7441         intel_ring_emit(ring, pf | pipesrc);
7442
7443         intel_mark_page_flip_active(intel_crtc);
7444         intel_ring_advance(ring);
7445         return 0;
7446
7447 err_unpin:
7448         intel_unpin_fb_obj(obj);
7449 err:
7450         return ret;
7451 }
7452
7453 /*
7454  * On gen7 we currently use the blit ring because (in early silicon at least)
7455  * the render ring doesn't give us interrpts for page flip completion, which
7456  * means clients will hang after the first flip is queued.  Fortunately the
7457  * blit ring generates interrupts properly, so use it instead.
7458  */
7459 static int intel_gen7_queue_flip(struct drm_device *dev,
7460                                  struct drm_crtc *crtc,
7461                                  struct drm_framebuffer *fb,
7462                                  struct drm_i915_gem_object *obj)
7463 {
7464         struct drm_i915_private *dev_priv = dev->dev_private;
7465         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7466         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7467         uint32_t plane_bit = 0;
7468         int ret;
7469
7470         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7471         if (ret)
7472                 goto err;
7473
7474         switch(intel_crtc->plane) {
7475         case PLANE_A:
7476                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7477                 break;
7478         case PLANE_B:
7479                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7480                 break;
7481         case PLANE_C:
7482                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7483                 break;
7484         default:
7485                 WARN_ONCE(1, "unknown plane in flip command\n");
7486                 ret = -ENODEV;
7487                 goto err_unpin;
7488         }
7489
7490         ret = intel_ring_begin(ring, 4);
7491         if (ret)
7492                 goto err_unpin;
7493
7494         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7495         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7496         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7497         intel_ring_emit(ring, (MI_NOOP));
7498
7499         intel_mark_page_flip_active(intel_crtc);
7500         intel_ring_advance(ring);
7501         return 0;
7502
7503 err_unpin:
7504         intel_unpin_fb_obj(obj);
7505 err:
7506         return ret;
7507 }
7508
7509 static int intel_default_queue_flip(struct drm_device *dev,
7510                                     struct drm_crtc *crtc,
7511                                     struct drm_framebuffer *fb,
7512                                     struct drm_i915_gem_object *obj)
7513 {
7514         return -ENODEV;
7515 }
7516
7517 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7518                                 struct drm_framebuffer *fb,
7519                                 struct drm_pending_vblank_event *event)
7520 {
7521         struct drm_device *dev = crtc->dev;
7522         struct drm_i915_private *dev_priv = dev->dev_private;
7523         struct drm_framebuffer *old_fb = crtc->fb;
7524         struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7526         struct intel_unpin_work *work;
7527         unsigned long flags;
7528         int ret;
7529
7530         /* Can't change pixel format via MI display flips. */
7531         if (fb->pixel_format != crtc->fb->pixel_format)
7532                 return -EINVAL;
7533
7534         /*
7535          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7536          * Note that pitch changes could also affect these register.
7537          */
7538         if (INTEL_INFO(dev)->gen > 3 &&
7539             (fb->offsets[0] != crtc->fb->offsets[0] ||
7540              fb->pitches[0] != crtc->fb->pitches[0]))
7541                 return -EINVAL;
7542
7543         work = kzalloc(sizeof *work, GFP_KERNEL);
7544         if (work == NULL)
7545                 return -ENOMEM;
7546
7547         work->event = event;
7548         work->crtc = crtc;
7549         work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7550         INIT_WORK(&work->work, intel_unpin_work_fn);
7551
7552         ret = drm_vblank_get(dev, intel_crtc->pipe);
7553         if (ret)
7554                 goto free_work;
7555
7556         /* We borrow the event spin lock for protecting unpin_work */
7557         spin_lock_irqsave(&dev->event_lock, flags);
7558         if (intel_crtc->unpin_work) {
7559                 spin_unlock_irqrestore(&dev->event_lock, flags);
7560                 kfree(work);
7561                 drm_vblank_put(dev, intel_crtc->pipe);
7562
7563                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7564                 return -EBUSY;
7565         }
7566         intel_crtc->unpin_work = work;
7567         spin_unlock_irqrestore(&dev->event_lock, flags);
7568
7569         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7570                 flush_workqueue(dev_priv->wq);
7571
7572         ret = i915_mutex_lock_interruptible(dev);
7573         if (ret)
7574                 goto cleanup;
7575
7576         /* Reference the objects for the scheduled work. */
7577         drm_gem_object_reference(&work->old_fb_obj->base);
7578         drm_gem_object_reference(&obj->base);
7579
7580         crtc->fb = fb;
7581
7582         work->pending_flip_obj = obj;
7583
7584         work->enable_stall_check = true;
7585
7586         atomic_inc(&intel_crtc->unpin_work_count);
7587         intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7588
7589         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7590         if (ret)
7591                 goto cleanup_pending;
7592
7593         intel_disable_fbc(dev);
7594         intel_mark_fb_busy(obj);
7595         mutex_unlock(&dev->struct_mutex);
7596
7597         trace_i915_flip_request(intel_crtc->plane, obj);
7598
7599         return 0;
7600
7601 cleanup_pending:
7602         atomic_dec(&intel_crtc->unpin_work_count);
7603         crtc->fb = old_fb;
7604         drm_gem_object_unreference(&work->old_fb_obj->base);
7605         drm_gem_object_unreference(&obj->base);
7606         mutex_unlock(&dev->struct_mutex);
7607
7608 cleanup:
7609         spin_lock_irqsave(&dev->event_lock, flags);
7610         intel_crtc->unpin_work = NULL;
7611         spin_unlock_irqrestore(&dev->event_lock, flags);
7612
7613         drm_vblank_put(dev, intel_crtc->pipe);
7614 free_work:
7615         kfree(work);
7616
7617         return ret;
7618 }
7619
7620 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7621         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7622         .load_lut = intel_crtc_load_lut,
7623 };
7624
7625 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7626 {
7627         struct intel_encoder *other_encoder;
7628         struct drm_crtc *crtc = &encoder->new_crtc->base;
7629
7630         if (WARN_ON(!crtc))
7631                 return false;
7632
7633         list_for_each_entry(other_encoder,
7634                             &crtc->dev->mode_config.encoder_list,
7635                             base.head) {
7636
7637                 if (&other_encoder->new_crtc->base != crtc ||
7638                     encoder == other_encoder)
7639                         continue;
7640                 else
7641                         return true;
7642         }
7643
7644         return false;
7645 }
7646
7647 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7648                                   struct drm_crtc *crtc)
7649 {
7650         struct drm_device *dev;
7651         struct drm_crtc *tmp;
7652         int crtc_mask = 1;
7653
7654         WARN(!crtc, "checking null crtc?\n");
7655
7656         dev = crtc->dev;
7657
7658         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7659                 if (tmp == crtc)
7660                         break;
7661                 crtc_mask <<= 1;
7662         }
7663
7664         if (encoder->possible_crtcs & crtc_mask)
7665                 return true;
7666         return false;
7667 }
7668
7669 /**
7670  * intel_modeset_update_staged_output_state
7671  *
7672  * Updates the staged output configuration state, e.g. after we've read out the
7673  * current hw state.
7674  */
7675 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7676 {
7677         struct intel_encoder *encoder;
7678         struct intel_connector *connector;
7679
7680         list_for_each_entry(connector, &dev->mode_config.connector_list,
7681                             base.head) {
7682                 connector->new_encoder =
7683                         to_intel_encoder(connector->base.encoder);
7684         }
7685
7686         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7687                             base.head) {
7688                 encoder->new_crtc =
7689                         to_intel_crtc(encoder->base.crtc);
7690         }
7691 }
7692
7693 /**
7694  * intel_modeset_commit_output_state
7695  *
7696  * This function copies the stage display pipe configuration to the real one.
7697  */
7698 static void intel_modeset_commit_output_state(struct drm_device *dev)
7699 {
7700         struct intel_encoder *encoder;
7701         struct intel_connector *connector;
7702
7703         list_for_each_entry(connector, &dev->mode_config.connector_list,
7704                             base.head) {
7705                 connector->base.encoder = &connector->new_encoder->base;
7706         }
7707
7708         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7709                             base.head) {
7710                 encoder->base.crtc = &encoder->new_crtc->base;
7711         }
7712 }
7713
7714 static int
7715 pipe_config_set_bpp(struct drm_crtc *crtc,
7716                     struct drm_framebuffer *fb,
7717                     struct intel_crtc_config *pipe_config)
7718 {
7719         struct drm_device *dev = crtc->dev;
7720         struct drm_connector *connector;
7721         int bpp;
7722
7723         switch (fb->pixel_format) {
7724         case DRM_FORMAT_C8:
7725                 bpp = 8*3; /* since we go through a colormap */
7726                 break;
7727         case DRM_FORMAT_XRGB1555:
7728         case DRM_FORMAT_ARGB1555:
7729                 /* checked in intel_framebuffer_init already */
7730                 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7731                         return -EINVAL;
7732         case DRM_FORMAT_RGB565:
7733                 bpp = 6*3; /* min is 18bpp */
7734                 break;
7735         case DRM_FORMAT_XBGR8888:
7736         case DRM_FORMAT_ABGR8888:
7737                 /* checked in intel_framebuffer_init already */
7738                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7739                         return -EINVAL;
7740         case DRM_FORMAT_XRGB8888:
7741         case DRM_FORMAT_ARGB8888:
7742                 bpp = 8*3;
7743                 break;
7744         case DRM_FORMAT_XRGB2101010:
7745         case DRM_FORMAT_ARGB2101010:
7746         case DRM_FORMAT_XBGR2101010:
7747         case DRM_FORMAT_ABGR2101010:
7748                 /* checked in intel_framebuffer_init already */
7749                 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7750                         return -EINVAL;
7751                 bpp = 10*3;
7752                 break;
7753         /* TODO: gen4+ supports 16 bpc floating point, too. */
7754         default:
7755                 DRM_DEBUG_KMS("unsupported depth\n");
7756                 return -EINVAL;
7757         }
7758
7759         pipe_config->pipe_bpp = bpp;
7760
7761         /* Clamp display bpp to EDID value */
7762         list_for_each_entry(connector, &dev->mode_config.connector_list,
7763                             head) {
7764                 if (connector->encoder && connector->encoder->crtc != crtc)
7765                         continue;
7766
7767                 /* Don't use an invalid EDID bpc value */
7768                 if (connector->display_info.bpc &&
7769                     connector->display_info.bpc * 3 < bpp) {
7770                         DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7771                                       bpp, connector->display_info.bpc*3);
7772                         pipe_config->pipe_bpp = connector->display_info.bpc*3;
7773                 }
7774
7775                 /* Clamp bpp to 8 on screens without EDID 1.4 */
7776                 if (connector->display_info.bpc == 0 && bpp > 24) {
7777                         DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7778                                       bpp);
7779                         pipe_config->pipe_bpp = 24;
7780                 }
7781         }
7782
7783         return bpp;
7784 }
7785
7786 static struct intel_crtc_config *
7787 intel_modeset_pipe_config(struct drm_crtc *crtc,
7788                           struct drm_framebuffer *fb,
7789                           struct drm_display_mode *mode)
7790 {
7791         struct drm_device *dev = crtc->dev;
7792         struct drm_encoder_helper_funcs *encoder_funcs;
7793         struct intel_encoder *encoder;
7794         struct intel_crtc_config *pipe_config;
7795         int plane_bpp, ret = -EINVAL;
7796         bool retry = true;
7797
7798         pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7799         if (!pipe_config)
7800                 return ERR_PTR(-ENOMEM);
7801
7802         drm_mode_copy(&pipe_config->adjusted_mode, mode);
7803         drm_mode_copy(&pipe_config->requested_mode, mode);
7804
7805         plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7806         if (plane_bpp < 0)
7807                 goto fail;
7808
7809 encoder_retry:
7810         /* Pass our mode to the connectors and the CRTC to give them a chance to
7811          * adjust it according to limitations or connector properties, and also
7812          * a chance to reject the mode entirely.
7813          */
7814         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7815                             base.head) {
7816
7817                 if (&encoder->new_crtc->base != crtc)
7818                         continue;
7819
7820                 if (encoder->compute_config) {
7821                         if (!(encoder->compute_config(encoder, pipe_config))) {
7822                                 DRM_DEBUG_KMS("Encoder config failure\n");
7823                                 goto fail;
7824                         }
7825
7826                         continue;
7827                 }
7828
7829                 encoder_funcs = encoder->base.helper_private;
7830                 if (!(encoder_funcs->mode_fixup(&encoder->base,
7831                                                 &pipe_config->requested_mode,
7832                                                 &pipe_config->adjusted_mode))) {
7833                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7834                         goto fail;
7835                 }
7836         }
7837
7838         ret = intel_crtc_compute_config(crtc, pipe_config);
7839         if (ret < 0) {
7840                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7841                 goto fail;
7842         }
7843
7844         if (ret == RETRY) {
7845                 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7846                         ret = -EINVAL;
7847                         goto fail;
7848                 }
7849
7850                 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7851                 retry = false;
7852                 goto encoder_retry;
7853         }
7854
7855         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7856
7857         pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7858         DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7859                       plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7860
7861         return pipe_config;
7862 fail:
7863         kfree(pipe_config);
7864         return ERR_PTR(ret);
7865 }
7866
7867 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7868  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7869 static void
7870 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7871                              unsigned *prepare_pipes, unsigned *disable_pipes)
7872 {
7873         struct intel_crtc *intel_crtc;
7874         struct drm_device *dev = crtc->dev;
7875         struct intel_encoder *encoder;
7876         struct intel_connector *connector;
7877         struct drm_crtc *tmp_crtc;
7878
7879         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7880
7881         /* Check which crtcs have changed outputs connected to them, these need
7882          * to be part of the prepare_pipes mask. We don't (yet) support global
7883          * modeset across multiple crtcs, so modeset_pipes will only have one
7884          * bit set at most. */
7885         list_for_each_entry(connector, &dev->mode_config.connector_list,
7886                             base.head) {
7887                 if (connector->base.encoder == &connector->new_encoder->base)
7888                         continue;
7889
7890                 if (connector->base.encoder) {
7891                         tmp_crtc = connector->base.encoder->crtc;
7892
7893                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7894                 }
7895
7896                 if (connector->new_encoder)
7897                         *prepare_pipes |=
7898                                 1 << connector->new_encoder->new_crtc->pipe;
7899         }
7900
7901         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7902                             base.head) {
7903                 if (encoder->base.crtc == &encoder->new_crtc->base)
7904                         continue;
7905
7906                 if (encoder->base.crtc) {
7907                         tmp_crtc = encoder->base.crtc;
7908
7909                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7910                 }
7911
7912                 if (encoder->new_crtc)
7913                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7914         }
7915
7916         /* Check for any pipes that will be fully disabled ... */
7917         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7918                             base.head) {
7919                 bool used = false;
7920
7921                 /* Don't try to disable disabled crtcs. */
7922                 if (!intel_crtc->base.enabled)
7923                         continue;
7924
7925                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7926                                     base.head) {
7927                         if (encoder->new_crtc == intel_crtc)
7928                                 used = true;
7929                 }
7930
7931                 if (!used)
7932                         *disable_pipes |= 1 << intel_crtc->pipe;
7933         }
7934
7935
7936         /* set_mode is also used to update properties on life display pipes. */
7937         intel_crtc = to_intel_crtc(crtc);
7938         if (crtc->enabled)
7939                 *prepare_pipes |= 1 << intel_crtc->pipe;
7940
7941         /*
7942          * For simplicity do a full modeset on any pipe where the output routing
7943          * changed. We could be more clever, but that would require us to be
7944          * more careful with calling the relevant encoder->mode_set functions.
7945          */
7946         if (*prepare_pipes)
7947                 *modeset_pipes = *prepare_pipes;
7948
7949         /* ... and mask these out. */
7950         *modeset_pipes &= ~(*disable_pipes);
7951         *prepare_pipes &= ~(*disable_pipes);
7952
7953         /*
7954          * HACK: We don't (yet) fully support global modesets. intel_set_config
7955          * obies this rule, but the modeset restore mode of
7956          * intel_modeset_setup_hw_state does not.
7957          */
7958         *modeset_pipes &= 1 << intel_crtc->pipe;
7959         *prepare_pipes &= 1 << intel_crtc->pipe;
7960
7961         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7962                       *modeset_pipes, *prepare_pipes, *disable_pipes);
7963 }
7964
7965 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7966 {
7967         struct drm_encoder *encoder;
7968         struct drm_device *dev = crtc->dev;
7969
7970         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7971                 if (encoder->crtc == crtc)
7972                         return true;
7973
7974         return false;
7975 }
7976
7977 static void
7978 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7979 {
7980         struct intel_encoder *intel_encoder;
7981         struct intel_crtc *intel_crtc;
7982         struct drm_connector *connector;
7983
7984         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7985                             base.head) {
7986                 if (!intel_encoder->base.crtc)
7987                         continue;
7988
7989                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7990
7991                 if (prepare_pipes & (1 << intel_crtc->pipe))
7992                         intel_encoder->connectors_active = false;
7993         }
7994
7995         intel_modeset_commit_output_state(dev);
7996
7997         /* Update computed state. */
7998         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7999                             base.head) {
8000                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8001         }
8002
8003         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8004                 if (!connector->encoder || !connector->encoder->crtc)
8005                         continue;
8006
8007                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8008
8009                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8010                         struct drm_property *dpms_property =
8011                                 dev->mode_config.dpms_property;
8012
8013                         connector->dpms = DRM_MODE_DPMS_ON;
8014                         drm_object_property_set_value(&connector->base,
8015                                                          dpms_property,
8016                                                          DRM_MODE_DPMS_ON);
8017
8018                         intel_encoder = to_intel_encoder(connector->encoder);
8019                         intel_encoder->connectors_active = true;
8020                 }
8021         }
8022
8023 }
8024
8025 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8026         list_for_each_entry((intel_crtc), \
8027                             &(dev)->mode_config.crtc_list, \
8028                             base.head) \
8029                 if (mask & (1 <<(intel_crtc)->pipe))
8030
8031 static bool
8032 intel_pipe_config_compare(struct intel_crtc_config *current_config,
8033                           struct intel_crtc_config *pipe_config)
8034 {
8035 #define PIPE_CONF_CHECK_I(name) \
8036         if (current_config->name != pipe_config->name) { \
8037                 DRM_ERROR("mismatch in " #name " " \
8038                           "(expected %i, found %i)\n", \
8039                           current_config->name, \
8040                           pipe_config->name); \
8041                 return false; \
8042         }
8043
8044 #define PIPE_CONF_CHECK_FLAGS(name, mask)       \
8045         if ((current_config->name ^ pipe_config->name) & (mask)) { \
8046                 DRM_ERROR("mismatch in " #name " " \
8047                           "(expected %i, found %i)\n", \
8048                           current_config->name & (mask), \
8049                           pipe_config->name & (mask)); \
8050                 return false; \
8051         }
8052
8053         PIPE_CONF_CHECK_I(has_pch_encoder);
8054         PIPE_CONF_CHECK_I(fdi_lanes);
8055         PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8056         PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8057         PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8058         PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8059         PIPE_CONF_CHECK_I(fdi_m_n.tu);
8060
8061         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8062         PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8063         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8064         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8065         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8066         PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8067
8068         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8069         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8070         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8071         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8072         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8073         PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8074
8075         PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8076                               DRM_MODE_FLAG_INTERLACE);
8077
8078         PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8079         PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8080
8081 #undef PIPE_CONF_CHECK_I
8082 #undef PIPE_CONF_CHECK_FLAGS
8083
8084         return true;
8085 }
8086
8087 void
8088 intel_modeset_check_state(struct drm_device *dev)
8089 {
8090         drm_i915_private_t *dev_priv = dev->dev_private;
8091         struct intel_crtc *crtc;
8092         struct intel_encoder *encoder;
8093         struct intel_connector *connector;
8094         struct intel_crtc_config pipe_config;
8095
8096         list_for_each_entry(connector, &dev->mode_config.connector_list,
8097                             base.head) {
8098                 /* This also checks the encoder/connector hw state with the
8099                  * ->get_hw_state callbacks. */
8100                 intel_connector_check_state(connector);
8101
8102                 WARN(&connector->new_encoder->base != connector->base.encoder,
8103                      "connector's staged encoder doesn't match current encoder\n");
8104         }
8105
8106         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8107                             base.head) {
8108                 bool enabled = false;
8109                 bool active = false;
8110                 enum pipe pipe, tracked_pipe;
8111
8112                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8113                               encoder->base.base.id,
8114                               drm_get_encoder_name(&encoder->base));
8115
8116                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8117                      "encoder's stage crtc doesn't match current crtc\n");
8118                 WARN(encoder->connectors_active && !encoder->base.crtc,
8119                      "encoder's active_connectors set, but no crtc\n");
8120
8121                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8122                                     base.head) {
8123                         if (connector->base.encoder != &encoder->base)
8124                                 continue;
8125                         enabled = true;
8126                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8127                                 active = true;
8128                 }
8129                 WARN(!!encoder->base.crtc != enabled,
8130                      "encoder's enabled state mismatch "
8131                      "(expected %i, found %i)\n",
8132                      !!encoder->base.crtc, enabled);
8133                 WARN(active && !encoder->base.crtc,
8134                      "active encoder with no crtc\n");
8135
8136                 WARN(encoder->connectors_active != active,
8137                      "encoder's computed active state doesn't match tracked active state "
8138                      "(expected %i, found %i)\n", active, encoder->connectors_active);
8139
8140                 active = encoder->get_hw_state(encoder, &pipe);
8141                 WARN(active != encoder->connectors_active,
8142                      "encoder's hw state doesn't match sw tracking "
8143                      "(expected %i, found %i)\n",
8144                      encoder->connectors_active, active);
8145
8146                 if (!encoder->base.crtc)
8147                         continue;
8148
8149                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8150                 WARN(active && pipe != tracked_pipe,
8151                      "active encoder's pipe doesn't match"
8152                      "(expected %i, found %i)\n",
8153                      tracked_pipe, pipe);
8154
8155         }
8156
8157         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8158                             base.head) {
8159                 bool enabled = false;
8160                 bool active = false;
8161
8162                 DRM_DEBUG_KMS("[CRTC:%d]\n",
8163                               crtc->base.base.id);
8164
8165                 WARN(crtc->active && !crtc->base.enabled,
8166                      "active crtc, but not enabled in sw tracking\n");
8167
8168                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8169                                     base.head) {
8170                         if (encoder->base.crtc != &crtc->base)
8171                                 continue;
8172                         enabled = true;
8173                         if (encoder->connectors_active)
8174                                 active = true;
8175                 }
8176                 WARN(active != crtc->active,
8177                      "crtc's computed active state doesn't match tracked active state "
8178                      "(expected %i, found %i)\n", active, crtc->active);
8179                 WARN(enabled != crtc->base.enabled,
8180                      "crtc's computed enabled state doesn't match tracked enabled state "
8181                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8182
8183                 memset(&pipe_config, 0, sizeof(pipe_config));
8184                 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
8185                 active = dev_priv->display.get_pipe_config(crtc,
8186                                                            &pipe_config);
8187                 WARN(crtc->active != active,
8188                      "crtc active state doesn't match with hw state "
8189                      "(expected %i, found %i)\n", crtc->active, active);
8190
8191                 WARN(active &&
8192                      !intel_pipe_config_compare(&crtc->config, &pipe_config),
8193                      "pipe state doesn't match!\n");
8194         }
8195 }
8196
8197 static int __intel_set_mode(struct drm_crtc *crtc,
8198                             struct drm_display_mode *mode,
8199                             int x, int y, struct drm_framebuffer *fb)
8200 {
8201         struct drm_device *dev = crtc->dev;
8202         drm_i915_private_t *dev_priv = dev->dev_private;
8203         struct drm_display_mode *saved_mode, *saved_hwmode;
8204         struct intel_crtc_config *pipe_config = NULL;
8205         struct intel_crtc *intel_crtc;
8206         unsigned disable_pipes, prepare_pipes, modeset_pipes;
8207         int ret = 0;
8208
8209         saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8210         if (!saved_mode)
8211                 return -ENOMEM;
8212         saved_hwmode = saved_mode + 1;
8213
8214         intel_modeset_affected_pipes(crtc, &modeset_pipes,
8215                                      &prepare_pipes, &disable_pipes);
8216
8217         *saved_hwmode = crtc->hwmode;
8218         *saved_mode = crtc->mode;
8219
8220         /* Hack: Because we don't (yet) support global modeset on multiple
8221          * crtcs, we don't keep track of the new mode for more than one crtc.
8222          * Hence simply check whether any bit is set in modeset_pipes in all the
8223          * pieces of code that are not yet converted to deal with mutliple crtcs
8224          * changing their mode at the same time. */
8225         if (modeset_pipes) {
8226                 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8227                 if (IS_ERR(pipe_config)) {
8228                         ret = PTR_ERR(pipe_config);
8229                         pipe_config = NULL;
8230
8231                         goto out;
8232                 }
8233         }
8234
8235         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8236                 intel_crtc_disable(&intel_crtc->base);
8237
8238         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8239                 if (intel_crtc->base.enabled)
8240                         dev_priv->display.crtc_disable(&intel_crtc->base);
8241         }
8242
8243         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8244          * to set it here already despite that we pass it down the callchain.
8245          */
8246         if (modeset_pipes) {
8247                 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
8248                 crtc->mode = *mode;
8249                 /* mode_set/enable/disable functions rely on a correct pipe
8250                  * config. */
8251                 to_intel_crtc(crtc)->config = *pipe_config;
8252                 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
8253         }
8254
8255         /* Only after disabling all output pipelines that will be changed can we
8256          * update the the output configuration. */
8257         intel_modeset_update_state(dev, prepare_pipes);
8258
8259         if (dev_priv->display.modeset_global_resources)
8260                 dev_priv->display.modeset_global_resources(dev);
8261
8262         /* Set up the DPLL and any encoders state that needs to adjust or depend
8263          * on the DPLL.
8264          */
8265         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8266                 ret = intel_crtc_mode_set(&intel_crtc->base,
8267                                           x, y, fb);
8268                 if (ret)
8269                         goto done;
8270         }
8271
8272         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8273         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8274                 dev_priv->display.crtc_enable(&intel_crtc->base);
8275
8276         if (modeset_pipes) {
8277                 /* Store real post-adjustment hardware mode. */
8278                 crtc->hwmode = pipe_config->adjusted_mode;
8279
8280                 /* Calculate and store various constants which
8281                  * are later needed by vblank and swap-completion
8282                  * timestamping. They are derived from true hwmode.
8283                  */
8284                 drm_calc_timestamping_constants(crtc);
8285         }
8286
8287         /* FIXME: add subpixel order */
8288 done:
8289         if (ret && crtc->enabled) {
8290                 crtc->hwmode = *saved_hwmode;
8291                 crtc->mode = *saved_mode;
8292         }
8293
8294 out:
8295         kfree(pipe_config);
8296         kfree(saved_mode);
8297         return ret;
8298 }
8299
8300 int intel_set_mode(struct drm_crtc *crtc,
8301                      struct drm_display_mode *mode,
8302                      int x, int y, struct drm_framebuffer *fb)
8303 {
8304         int ret;
8305
8306         ret = __intel_set_mode(crtc, mode, x, y, fb);
8307
8308         if (ret == 0)
8309                 intel_modeset_check_state(crtc->dev);
8310
8311         return ret;
8312 }
8313
8314 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8315 {
8316         intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8317 }
8318
8319 #undef for_each_intel_crtc_masked
8320
8321 static void intel_set_config_free(struct intel_set_config *config)
8322 {
8323         if (!config)
8324                 return;
8325
8326         kfree(config->save_connector_encoders);
8327         kfree(config->save_encoder_crtcs);
8328         kfree(config);
8329 }
8330
8331 static int intel_set_config_save_state(struct drm_device *dev,
8332                                        struct intel_set_config *config)
8333 {
8334         struct drm_encoder *encoder;
8335         struct drm_connector *connector;
8336         int count;
8337
8338         config->save_encoder_crtcs =
8339                 kcalloc(dev->mode_config.num_encoder,
8340                         sizeof(struct drm_crtc *), GFP_KERNEL);
8341         if (!config->save_encoder_crtcs)
8342                 return -ENOMEM;
8343
8344         config->save_connector_encoders =
8345                 kcalloc(dev->mode_config.num_connector,
8346                         sizeof(struct drm_encoder *), GFP_KERNEL);
8347         if (!config->save_connector_encoders)
8348                 return -ENOMEM;
8349
8350         /* Copy data. Note that driver private data is not affected.
8351          * Should anything bad happen only the expected state is
8352          * restored, not the drivers personal bookkeeping.
8353          */
8354         count = 0;
8355         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
8356                 config->save_encoder_crtcs[count++] = encoder->crtc;
8357         }
8358
8359         count = 0;
8360         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8361                 config->save_connector_encoders[count++] = connector->encoder;
8362         }
8363
8364         return 0;
8365 }
8366
8367 static void intel_set_config_restore_state(struct drm_device *dev,
8368                                            struct intel_set_config *config)
8369 {
8370         struct intel_encoder *encoder;
8371         struct intel_connector *connector;
8372         int count;
8373
8374         count = 0;
8375         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8376                 encoder->new_crtc =
8377                         to_intel_crtc(config->save_encoder_crtcs[count++]);
8378         }
8379
8380         count = 0;
8381         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8382                 connector->new_encoder =
8383                         to_intel_encoder(config->save_connector_encoders[count++]);
8384         }
8385 }
8386
8387 static void
8388 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8389                                       struct intel_set_config *config)
8390 {
8391
8392         /* We should be able to check here if the fb has the same properties
8393          * and then just flip_or_move it */
8394         if (set->crtc->fb != set->fb) {
8395                 /* If we have no fb then treat it as a full mode set */
8396                 if (set->crtc->fb == NULL) {
8397                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8398                         config->mode_changed = true;
8399                 } else if (set->fb == NULL) {
8400                         config->mode_changed = true;
8401                 } else if (set->fb->pixel_format !=
8402                            set->crtc->fb->pixel_format) {
8403                         config->mode_changed = true;
8404                 } else
8405                         config->fb_changed = true;
8406         }
8407
8408         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8409                 config->fb_changed = true;
8410
8411         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8412                 DRM_DEBUG_KMS("modes are different, full mode set\n");
8413                 drm_mode_debug_printmodeline(&set->crtc->mode);
8414                 drm_mode_debug_printmodeline(set->mode);
8415                 config->mode_changed = true;
8416         }
8417 }
8418
8419 static int
8420 intel_modeset_stage_output_state(struct drm_device *dev,
8421                                  struct drm_mode_set *set,
8422                                  struct intel_set_config *config)
8423 {
8424         struct drm_crtc *new_crtc;
8425         struct intel_connector *connector;
8426         struct intel_encoder *encoder;
8427         int count, ro;
8428
8429         /* The upper layers ensure that we either disable a crtc or have a list
8430          * of connectors. For paranoia, double-check this. */
8431         WARN_ON(!set->fb && (set->num_connectors != 0));
8432         WARN_ON(set->fb && (set->num_connectors == 0));
8433
8434         count = 0;
8435         list_for_each_entry(connector, &dev->mode_config.connector_list,
8436                             base.head) {
8437                 /* Otherwise traverse passed in connector list and get encoders
8438                  * for them. */
8439                 for (ro = 0; ro < set->num_connectors; ro++) {
8440                         if (set->connectors[ro] == &connector->base) {
8441                                 connector->new_encoder = connector->encoder;
8442                                 break;
8443                         }
8444                 }
8445
8446                 /* If we disable the crtc, disable all its connectors. Also, if
8447                  * the connector is on the changing crtc but not on the new
8448                  * connector list, disable it. */
8449                 if ((!set->fb || ro == set->num_connectors) &&
8450                     connector->base.encoder &&
8451                     connector->base.encoder->crtc == set->crtc) {
8452                         connector->new_encoder = NULL;
8453
8454                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8455                                 connector->base.base.id,
8456                                 drm_get_connector_name(&connector->base));
8457                 }
8458
8459
8460                 if (&connector->new_encoder->base != connector->base.encoder) {
8461                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8462                         config->mode_changed = true;
8463                 }
8464         }
8465         /* connector->new_encoder is now updated for all connectors. */
8466
8467         /* Update crtc of enabled connectors. */
8468         count = 0;
8469         list_for_each_entry(connector, &dev->mode_config.connector_list,
8470                             base.head) {
8471                 if (!connector->new_encoder)
8472                         continue;
8473
8474                 new_crtc = connector->new_encoder->base.crtc;
8475
8476                 for (ro = 0; ro < set->num_connectors; ro++) {
8477                         if (set->connectors[ro] == &connector->base)
8478                                 new_crtc = set->crtc;
8479                 }
8480
8481                 /* Make sure the new CRTC will work with the encoder */
8482                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8483                                            new_crtc)) {
8484                         return -EINVAL;
8485                 }
8486                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8487
8488                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8489                         connector->base.base.id,
8490                         drm_get_connector_name(&connector->base),
8491                         new_crtc->base.id);
8492         }
8493
8494         /* Check for any encoders that needs to be disabled. */
8495         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8496                             base.head) {
8497                 list_for_each_entry(connector,
8498                                     &dev->mode_config.connector_list,
8499                                     base.head) {
8500                         if (connector->new_encoder == encoder) {
8501                                 WARN_ON(!connector->new_encoder->new_crtc);
8502
8503                                 goto next_encoder;
8504                         }
8505                 }
8506                 encoder->new_crtc = NULL;
8507 next_encoder:
8508                 /* Only now check for crtc changes so we don't miss encoders
8509                  * that will be disabled. */
8510                 if (&encoder->new_crtc->base != encoder->base.crtc) {
8511                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8512                         config->mode_changed = true;
8513                 }
8514         }
8515         /* Now we've also updated encoder->new_crtc for all encoders. */
8516
8517         return 0;
8518 }
8519
8520 static int intel_crtc_set_config(struct drm_mode_set *set)
8521 {
8522         struct drm_device *dev;
8523         struct drm_mode_set save_set;
8524         struct intel_set_config *config;
8525         int ret;
8526
8527         BUG_ON(!set);
8528         BUG_ON(!set->crtc);
8529         BUG_ON(!set->crtc->helper_private);
8530
8531         /* Enforce sane interface api - has been abused by the fb helper. */
8532         BUG_ON(!set->mode && set->fb);
8533         BUG_ON(set->fb && set->num_connectors == 0);
8534
8535         if (set->fb) {
8536                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8537                                 set->crtc->base.id, set->fb->base.id,
8538                                 (int)set->num_connectors, set->x, set->y);
8539         } else {
8540                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8541         }
8542
8543         dev = set->crtc->dev;
8544
8545         ret = -ENOMEM;
8546         config = kzalloc(sizeof(*config), GFP_KERNEL);
8547         if (!config)
8548                 goto out_config;
8549
8550         ret = intel_set_config_save_state(dev, config);
8551         if (ret)
8552                 goto out_config;
8553
8554         save_set.crtc = set->crtc;
8555         save_set.mode = &set->crtc->mode;
8556         save_set.x = set->crtc->x;
8557         save_set.y = set->crtc->y;
8558         save_set.fb = set->crtc->fb;
8559
8560         /* Compute whether we need a full modeset, only an fb base update or no
8561          * change at all. In the future we might also check whether only the
8562          * mode changed, e.g. for LVDS where we only change the panel fitter in
8563          * such cases. */
8564         intel_set_config_compute_mode_changes(set, config);
8565
8566         ret = intel_modeset_stage_output_state(dev, set, config);
8567         if (ret)
8568                 goto fail;
8569
8570         if (config->mode_changed) {
8571                 if (set->mode) {
8572                         DRM_DEBUG_KMS("attempting to set mode from"
8573                                         " userspace\n");
8574                         drm_mode_debug_printmodeline(set->mode);
8575                 }
8576
8577                 ret = intel_set_mode(set->crtc, set->mode,
8578                                      set->x, set->y, set->fb);
8579                 if (ret) {
8580                         DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8581                                   set->crtc->base.id, ret);
8582                         goto fail;
8583                 }
8584         } else if (config->fb_changed) {
8585                 intel_crtc_wait_for_pending_flips(set->crtc);
8586
8587                 ret = intel_pipe_set_base(set->crtc,
8588                                           set->x, set->y, set->fb);
8589         }
8590
8591         intel_set_config_free(config);
8592
8593         return 0;
8594
8595 fail:
8596         intel_set_config_restore_state(dev, config);
8597
8598         /* Try to restore the config */
8599         if (config->mode_changed &&
8600             intel_set_mode(save_set.crtc, save_set.mode,
8601                            save_set.x, save_set.y, save_set.fb))
8602                 DRM_ERROR("failed to restore config after modeset failure\n");
8603
8604 out_config:
8605         intel_set_config_free(config);
8606         return ret;
8607 }
8608
8609 static const struct drm_crtc_funcs intel_crtc_funcs = {
8610         .cursor_set = intel_crtc_cursor_set,
8611         .cursor_move = intel_crtc_cursor_move,
8612         .gamma_set = intel_crtc_gamma_set,
8613         .set_config = intel_crtc_set_config,
8614         .destroy = intel_crtc_destroy,
8615         .page_flip = intel_crtc_page_flip,
8616 };
8617
8618 static void intel_cpu_pll_init(struct drm_device *dev)
8619 {
8620         if (HAS_DDI(dev))
8621                 intel_ddi_pll_init(dev);
8622 }
8623
8624 static void intel_pch_pll_init(struct drm_device *dev)
8625 {
8626         drm_i915_private_t *dev_priv = dev->dev_private;
8627         int i;
8628
8629         if (dev_priv->num_pch_pll == 0) {
8630                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8631                 return;
8632         }
8633
8634         for (i = 0; i < dev_priv->num_pch_pll; i++) {
8635                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8636                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8637                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8638         }
8639 }
8640
8641 static void intel_crtc_init(struct drm_device *dev, int pipe)
8642 {
8643         drm_i915_private_t *dev_priv = dev->dev_private;
8644         struct intel_crtc *intel_crtc;
8645         int i;
8646
8647         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8648         if (intel_crtc == NULL)
8649                 return;
8650
8651         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8652
8653         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8654         for (i = 0; i < 256; i++) {
8655                 intel_crtc->lut_r[i] = i;
8656                 intel_crtc->lut_g[i] = i;
8657                 intel_crtc->lut_b[i] = i;
8658         }
8659
8660         /* Swap pipes & planes for FBC on pre-965 */
8661         intel_crtc->pipe = pipe;
8662         intel_crtc->plane = pipe;
8663         intel_crtc->config.cpu_transcoder = pipe;
8664         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8665                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8666                 intel_crtc->plane = !pipe;
8667         }
8668
8669         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8670                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8671         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8672         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8673
8674         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8675 }
8676
8677 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8678                                 struct drm_file *file)
8679 {
8680         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8681         struct drm_mode_object *drmmode_obj;
8682         struct intel_crtc *crtc;
8683
8684         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8685                 return -ENODEV;
8686
8687         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8688                         DRM_MODE_OBJECT_CRTC);
8689
8690         if (!drmmode_obj) {
8691                 DRM_ERROR("no such CRTC id\n");
8692                 return -EINVAL;
8693         }
8694
8695         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8696         pipe_from_crtc_id->pipe = crtc->pipe;
8697
8698         return 0;
8699 }
8700
8701 static int intel_encoder_clones(struct intel_encoder *encoder)
8702 {
8703         struct drm_device *dev = encoder->base.dev;
8704         struct intel_encoder *source_encoder;
8705         int index_mask = 0;
8706         int entry = 0;
8707
8708         list_for_each_entry(source_encoder,
8709                             &dev->mode_config.encoder_list, base.head) {
8710
8711                 if (encoder == source_encoder)
8712                         index_mask |= (1 << entry);
8713
8714                 /* Intel hw has only one MUX where enocoders could be cloned. */
8715                 if (encoder->cloneable && source_encoder->cloneable)
8716                         index_mask |= (1 << entry);
8717
8718                 entry++;
8719         }
8720
8721         return index_mask;
8722 }
8723
8724 static bool has_edp_a(struct drm_device *dev)
8725 {
8726         struct drm_i915_private *dev_priv = dev->dev_private;
8727
8728         if (!IS_MOBILE(dev))
8729                 return false;
8730
8731         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8732                 return false;
8733
8734         if (IS_GEN5(dev) &&
8735             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8736                 return false;
8737
8738         return true;
8739 }
8740
8741 static void intel_setup_outputs(struct drm_device *dev)
8742 {
8743         struct drm_i915_private *dev_priv = dev->dev_private;
8744         struct intel_encoder *encoder;
8745         bool dpd_is_edp = false;
8746         bool has_lvds;
8747
8748         has_lvds = intel_lvds_init(dev);
8749         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8750                 /* disable the panel fitter on everything but LVDS */
8751                 I915_WRITE(PFIT_CONTROL, 0);
8752         }
8753
8754         if (!IS_ULT(dev))
8755                 intel_crt_init(dev);
8756
8757         if (HAS_DDI(dev)) {
8758                 int found;
8759
8760                 /* Haswell uses DDI functions to detect digital outputs */
8761                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8762                 /* DDI A only supports eDP */
8763                 if (found)
8764                         intel_ddi_init(dev, PORT_A);
8765
8766                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8767                  * register */
8768                 found = I915_READ(SFUSE_STRAP);
8769
8770                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8771                         intel_ddi_init(dev, PORT_B);
8772                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8773                         intel_ddi_init(dev, PORT_C);
8774                 if (found & SFUSE_STRAP_DDID_DETECTED)
8775                         intel_ddi_init(dev, PORT_D);
8776         } else if (HAS_PCH_SPLIT(dev)) {
8777                 int found;
8778                 dpd_is_edp = intel_dpd_is_edp(dev);
8779
8780                 if (has_edp_a(dev))
8781                         intel_dp_init(dev, DP_A, PORT_A);
8782
8783                 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
8784                         /* PCH SDVOB multiplex with HDMIB */
8785                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8786                         if (!found)
8787                                 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
8788                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8789                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8790                 }
8791
8792                 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
8793                         intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
8794
8795                 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
8796                         intel_hdmi_init(dev, PCH_HDMID, PORT_D);
8797
8798                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8799                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8800
8801                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8802                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8803         } else if (IS_VALLEYVIEW(dev)) {
8804                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8805                 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8806                         intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
8807
8808                 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
8809                         intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8810                                         PORT_B);
8811                         if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8812                                 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
8813                 }
8814         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8815                 bool found = false;
8816
8817                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8818                         DRM_DEBUG_KMS("probing SDVOB\n");
8819                         found = intel_sdvo_init(dev, GEN3_SDVOB, true);
8820                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8821                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8822                                 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
8823                         }
8824
8825                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8826                                 DRM_DEBUG_KMS("probing DP_B\n");
8827                                 intel_dp_init(dev, DP_B, PORT_B);
8828                         }
8829                 }
8830
8831                 /* Before G4X SDVOC doesn't have its own detect register */
8832
8833                 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
8834                         DRM_DEBUG_KMS("probing SDVOC\n");
8835                         found = intel_sdvo_init(dev, GEN3_SDVOC, false);
8836                 }
8837
8838                 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
8839
8840                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8841                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8842                                 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
8843                         }
8844                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8845                                 DRM_DEBUG_KMS("probing DP_C\n");
8846                                 intel_dp_init(dev, DP_C, PORT_C);
8847                         }
8848                 }
8849
8850                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8851                     (I915_READ(DP_D) & DP_DETECTED)) {
8852                         DRM_DEBUG_KMS("probing DP_D\n");
8853                         intel_dp_init(dev, DP_D, PORT_D);
8854                 }
8855         } else if (IS_GEN2(dev))
8856                 intel_dvo_init(dev);
8857
8858         if (SUPPORTS_TV(dev))
8859                 intel_tv_init(dev);
8860
8861         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8862                 encoder->base.possible_crtcs = encoder->crtc_mask;
8863                 encoder->base.possible_clones =
8864                         intel_encoder_clones(encoder);
8865         }
8866
8867         intel_init_pch_refclk(dev);
8868
8869         drm_helper_move_panel_connectors_to_head(dev);
8870 }
8871
8872 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8873 {
8874         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8875
8876         drm_framebuffer_cleanup(fb);
8877         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8878
8879         kfree(intel_fb);
8880 }
8881
8882 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8883                                                 struct drm_file *file,
8884                                                 unsigned int *handle)
8885 {
8886         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8887         struct drm_i915_gem_object *obj = intel_fb->obj;
8888
8889         return drm_gem_handle_create(file, &obj->base, handle);
8890 }
8891
8892 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8893         .destroy = intel_user_framebuffer_destroy,
8894         .create_handle = intel_user_framebuffer_create_handle,
8895 };
8896
8897 int intel_framebuffer_init(struct drm_device *dev,
8898                            struct intel_framebuffer *intel_fb,
8899                            struct drm_mode_fb_cmd2 *mode_cmd,
8900                            struct drm_i915_gem_object *obj)
8901 {
8902         int ret;
8903
8904         if (obj->tiling_mode == I915_TILING_Y) {
8905                 DRM_DEBUG("hardware does not support tiling Y\n");
8906                 return -EINVAL;
8907         }
8908
8909         if (mode_cmd->pitches[0] & 63) {
8910                 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8911                           mode_cmd->pitches[0]);
8912                 return -EINVAL;
8913         }
8914
8915         /* FIXME <= Gen4 stride limits are bit unclear */
8916         if (mode_cmd->pitches[0] > 32768) {
8917                 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8918                           mode_cmd->pitches[0]);
8919                 return -EINVAL;
8920         }
8921
8922         if (obj->tiling_mode != I915_TILING_NONE &&
8923             mode_cmd->pitches[0] != obj->stride) {
8924                 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8925                           mode_cmd->pitches[0], obj->stride);
8926                 return -EINVAL;
8927         }
8928
8929         /* Reject formats not supported by any plane early. */
8930         switch (mode_cmd->pixel_format) {
8931         case DRM_FORMAT_C8:
8932         case DRM_FORMAT_RGB565:
8933         case DRM_FORMAT_XRGB8888:
8934         case DRM_FORMAT_ARGB8888:
8935                 break;
8936         case DRM_FORMAT_XRGB1555:
8937         case DRM_FORMAT_ARGB1555:
8938                 if (INTEL_INFO(dev)->gen > 3) {
8939                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8940                         return -EINVAL;
8941                 }
8942                 break;
8943         case DRM_FORMAT_XBGR8888:
8944         case DRM_FORMAT_ABGR8888:
8945         case DRM_FORMAT_XRGB2101010:
8946         case DRM_FORMAT_ARGB2101010:
8947         case DRM_FORMAT_XBGR2101010:
8948         case DRM_FORMAT_ABGR2101010:
8949                 if (INTEL_INFO(dev)->gen < 4) {
8950                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8951                         return -EINVAL;
8952                 }
8953                 break;
8954         case DRM_FORMAT_YUYV:
8955         case DRM_FORMAT_UYVY:
8956         case DRM_FORMAT_YVYU:
8957         case DRM_FORMAT_VYUY:
8958                 if (INTEL_INFO(dev)->gen < 5) {
8959                         DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
8960                         return -EINVAL;
8961                 }
8962                 break;
8963         default:
8964                 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8965                 return -EINVAL;
8966         }
8967
8968         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8969         if (mode_cmd->offsets[0] != 0)
8970                 return -EINVAL;
8971
8972         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8973         intel_fb->obj = obj;
8974
8975         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8976         if (ret) {
8977                 DRM_ERROR("framebuffer init failed %d\n", ret);
8978                 return ret;
8979         }
8980
8981         return 0;
8982 }
8983
8984 static struct drm_framebuffer *
8985 intel_user_framebuffer_create(struct drm_device *dev,
8986                               struct drm_file *filp,
8987                               struct drm_mode_fb_cmd2 *mode_cmd)
8988 {
8989         struct drm_i915_gem_object *obj;
8990
8991         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8992                                                 mode_cmd->handles[0]));
8993         if (&obj->base == NULL)
8994                 return ERR_PTR(-ENOENT);
8995
8996         return intel_framebuffer_create(dev, mode_cmd, obj);
8997 }
8998
8999 static const struct drm_mode_config_funcs intel_mode_funcs = {
9000         .fb_create = intel_user_framebuffer_create,
9001         .output_poll_changed = intel_fb_output_poll_changed,
9002 };
9003
9004 /* Set up chip specific display functions */
9005 static void intel_init_display(struct drm_device *dev)
9006 {
9007         struct drm_i915_private *dev_priv = dev->dev_private;
9008
9009         if (HAS_DDI(dev)) {
9010                 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9011                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9012                 dev_priv->display.crtc_enable = haswell_crtc_enable;
9013                 dev_priv->display.crtc_disable = haswell_crtc_disable;
9014                 dev_priv->display.off = haswell_crtc_off;
9015                 dev_priv->display.update_plane = ironlake_update_plane;
9016         } else if (HAS_PCH_SPLIT(dev)) {
9017                 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9018                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9019                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9020                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9021                 dev_priv->display.off = ironlake_crtc_off;
9022                 dev_priv->display.update_plane = ironlake_update_plane;
9023         } else if (IS_VALLEYVIEW(dev)) {
9024                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9025                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9026                 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9027                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9028                 dev_priv->display.off = i9xx_crtc_off;
9029                 dev_priv->display.update_plane = i9xx_update_plane;
9030         } else {
9031                 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9032                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9033                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9034                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9035                 dev_priv->display.off = i9xx_crtc_off;
9036                 dev_priv->display.update_plane = i9xx_update_plane;
9037         }
9038
9039         /* Returns the core display clock speed */
9040         if (IS_VALLEYVIEW(dev))
9041                 dev_priv->display.get_display_clock_speed =
9042                         valleyview_get_display_clock_speed;
9043         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9044                 dev_priv->display.get_display_clock_speed =
9045                         i945_get_display_clock_speed;
9046         else if (IS_I915G(dev))
9047                 dev_priv->display.get_display_clock_speed =
9048                         i915_get_display_clock_speed;
9049         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9050                 dev_priv->display.get_display_clock_speed =
9051                         i9xx_misc_get_display_clock_speed;
9052         else if (IS_I915GM(dev))
9053                 dev_priv->display.get_display_clock_speed =
9054                         i915gm_get_display_clock_speed;
9055         else if (IS_I865G(dev))
9056                 dev_priv->display.get_display_clock_speed =
9057                         i865_get_display_clock_speed;
9058         else if (IS_I85X(dev))
9059                 dev_priv->display.get_display_clock_speed =
9060                         i855_get_display_clock_speed;
9061         else /* 852, 830 */
9062                 dev_priv->display.get_display_clock_speed =
9063                         i830_get_display_clock_speed;
9064
9065         if (HAS_PCH_SPLIT(dev)) {
9066                 if (IS_GEN5(dev)) {
9067                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9068                         dev_priv->display.write_eld = ironlake_write_eld;
9069                 } else if (IS_GEN6(dev)) {
9070                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9071                         dev_priv->display.write_eld = ironlake_write_eld;
9072                 } else if (IS_IVYBRIDGE(dev)) {
9073                         /* FIXME: detect B0+ stepping and use auto training */
9074                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9075                         dev_priv->display.write_eld = ironlake_write_eld;
9076                         dev_priv->display.modeset_global_resources =
9077                                 ivb_modeset_global_resources;
9078                 } else if (IS_HASWELL(dev)) {
9079                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9080                         dev_priv->display.write_eld = haswell_write_eld;
9081                         dev_priv->display.modeset_global_resources =
9082                                 haswell_modeset_global_resources;
9083                 }
9084         } else if (IS_G4X(dev)) {
9085                 dev_priv->display.write_eld = g4x_write_eld;
9086         }
9087
9088         /* Default just returns -ENODEV to indicate unsupported */
9089         dev_priv->display.queue_flip = intel_default_queue_flip;
9090
9091         switch (INTEL_INFO(dev)->gen) {
9092         case 2:
9093                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9094                 break;
9095
9096         case 3:
9097                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9098                 break;
9099
9100         case 4:
9101         case 5:
9102                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9103                 break;
9104
9105         case 6:
9106                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9107                 break;
9108         case 7:
9109                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9110                 break;
9111         }
9112 }
9113
9114 /*
9115  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9116  * resume, or other times.  This quirk makes sure that's the case for
9117  * affected systems.
9118  */
9119 static void quirk_pipea_force(struct drm_device *dev)
9120 {
9121         struct drm_i915_private *dev_priv = dev->dev_private;
9122
9123         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9124         DRM_INFO("applying pipe a force quirk\n");
9125 }
9126
9127 /*
9128  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9129  */
9130 static void quirk_ssc_force_disable(struct drm_device *dev)
9131 {
9132         struct drm_i915_private *dev_priv = dev->dev_private;
9133         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9134         DRM_INFO("applying lvds SSC disable quirk\n");
9135 }
9136
9137 /*
9138  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9139  * brightness value
9140  */
9141 static void quirk_invert_brightness(struct drm_device *dev)
9142 {
9143         struct drm_i915_private *dev_priv = dev->dev_private;
9144         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9145         DRM_INFO("applying inverted panel brightness quirk\n");
9146 }
9147
9148 struct intel_quirk {
9149         int device;
9150         int subsystem_vendor;
9151         int subsystem_device;
9152         void (*hook)(struct drm_device *dev);
9153 };
9154
9155 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9156 struct intel_dmi_quirk {
9157         void (*hook)(struct drm_device *dev);
9158         const struct dmi_system_id (*dmi_id_list)[];
9159 };
9160
9161 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9162 {
9163         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9164         return 1;
9165 }
9166
9167 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9168         {
9169                 .dmi_id_list = &(const struct dmi_system_id[]) {
9170                         {
9171                                 .callback = intel_dmi_reverse_brightness,
9172                                 .ident = "NCR Corporation",
9173                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9174                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
9175                                 },
9176                         },
9177                         { }  /* terminating entry */
9178                 },
9179                 .hook = quirk_invert_brightness,
9180         },
9181 };
9182
9183 static struct intel_quirk intel_quirks[] = {
9184         /* HP Mini needs pipe A force quirk (LP: #322104) */
9185         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9186
9187         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9188         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9189
9190         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9191         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9192
9193         /* 830/845 need to leave pipe A & dpll A up */
9194         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9195         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9196
9197         /* Lenovo U160 cannot use SSC on LVDS */
9198         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9199
9200         /* Sony Vaio Y cannot use SSC on LVDS */
9201         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9202
9203         /* Acer Aspire 5734Z must invert backlight brightness */
9204         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9205
9206         /* Acer/eMachines G725 */
9207         { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9208
9209         /* Acer/eMachines e725 */
9210         { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9211
9212         /* Acer/Packard Bell NCL20 */
9213         { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9214
9215         /* Acer Aspire 4736Z */
9216         { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9217 };
9218
9219 static void intel_init_quirks(struct drm_device *dev)
9220 {
9221         struct pci_dev *d = dev->pdev;
9222         int i;
9223
9224         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9225                 struct intel_quirk *q = &intel_quirks[i];
9226
9227                 if (d->device == q->device &&
9228                     (d->subsystem_vendor == q->subsystem_vendor ||
9229                      q->subsystem_vendor == PCI_ANY_ID) &&
9230                     (d->subsystem_device == q->subsystem_device ||
9231                      q->subsystem_device == PCI_ANY_ID))
9232                         q->hook(dev);
9233         }
9234         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9235                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9236                         intel_dmi_quirks[i].hook(dev);
9237         }
9238 }
9239
9240 /* Disable the VGA plane that we never use */
9241 static void i915_disable_vga(struct drm_device *dev)
9242 {
9243         struct drm_i915_private *dev_priv = dev->dev_private;
9244         u8 sr1;
9245         u32 vga_reg = i915_vgacntrl_reg(dev);
9246
9247         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9248         outb(SR01, VGA_SR_INDEX);
9249         sr1 = inb(VGA_SR_DATA);
9250         outb(sr1 | 1<<5, VGA_SR_DATA);
9251         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9252         udelay(300);
9253
9254         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9255         POSTING_READ(vga_reg);
9256 }
9257
9258 void intel_modeset_init_hw(struct drm_device *dev)
9259 {
9260         intel_init_power_well(dev);
9261
9262         intel_prepare_ddi(dev);
9263
9264         intel_init_clock_gating(dev);
9265
9266         mutex_lock(&dev->struct_mutex);
9267         intel_enable_gt_powersave(dev);
9268         mutex_unlock(&dev->struct_mutex);
9269 }
9270
9271 void intel_modeset_init(struct drm_device *dev)
9272 {
9273         struct drm_i915_private *dev_priv = dev->dev_private;
9274         int i, j, ret;
9275
9276         drm_mode_config_init(dev);
9277
9278         dev->mode_config.min_width = 0;
9279         dev->mode_config.min_height = 0;
9280
9281         dev->mode_config.preferred_depth = 24;
9282         dev->mode_config.prefer_shadow = 1;
9283
9284         dev->mode_config.funcs = &intel_mode_funcs;
9285
9286         intel_init_quirks(dev);
9287
9288         intel_init_pm(dev);
9289
9290         if (INTEL_INFO(dev)->num_pipes == 0)
9291                 return;
9292
9293         intel_init_display(dev);
9294
9295         if (IS_GEN2(dev)) {
9296                 dev->mode_config.max_width = 2048;
9297                 dev->mode_config.max_height = 2048;
9298         } else if (IS_GEN3(dev)) {
9299                 dev->mode_config.max_width = 4096;
9300                 dev->mode_config.max_height = 4096;
9301         } else {
9302                 dev->mode_config.max_width = 8192;
9303                 dev->mode_config.max_height = 8192;
9304         }
9305         dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9306
9307         DRM_DEBUG_KMS("%d display pipe%s available.\n",
9308                       INTEL_INFO(dev)->num_pipes,
9309                       INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9310
9311         for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9312                 intel_crtc_init(dev, i);
9313                 for (j = 0; j < dev_priv->num_plane; j++) {
9314                         ret = intel_plane_init(dev, i, j);
9315                         if (ret)
9316                                 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9317                                               pipe_name(i), sprite_name(i, j), ret);
9318                 }
9319         }
9320
9321         intel_cpu_pll_init(dev);
9322         intel_pch_pll_init(dev);
9323
9324         /* Just disable it once at startup */
9325         i915_disable_vga(dev);
9326         intel_setup_outputs(dev);
9327
9328         /* Just in case the BIOS is doing something questionable. */
9329         intel_disable_fbc(dev);
9330 }
9331
9332 static void
9333 intel_connector_break_all_links(struct intel_connector *connector)
9334 {
9335         connector->base.dpms = DRM_MODE_DPMS_OFF;
9336         connector->base.encoder = NULL;
9337         connector->encoder->connectors_active = false;
9338         connector->encoder->base.crtc = NULL;
9339 }
9340
9341 static void intel_enable_pipe_a(struct drm_device *dev)
9342 {
9343         struct intel_connector *connector;
9344         struct drm_connector *crt = NULL;
9345         struct intel_load_detect_pipe load_detect_temp;
9346
9347         /* We can't just switch on the pipe A, we need to set things up with a
9348          * proper mode and output configuration. As a gross hack, enable pipe A
9349          * by enabling the load detect pipe once. */
9350         list_for_each_entry(connector,
9351                             &dev->mode_config.connector_list,
9352                             base.head) {
9353                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9354                         crt = &connector->base;
9355                         break;
9356                 }
9357         }
9358
9359         if (!crt)
9360                 return;
9361
9362         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9363                 intel_release_load_detect_pipe(crt, &load_detect_temp);
9364
9365
9366 }
9367
9368 static bool
9369 intel_check_plane_mapping(struct intel_crtc *crtc)
9370 {
9371         struct drm_device *dev = crtc->base.dev;
9372         struct drm_i915_private *dev_priv = dev->dev_private;
9373         u32 reg, val;
9374
9375         if (INTEL_INFO(dev)->num_pipes == 1)
9376                 return true;
9377
9378         reg = DSPCNTR(!crtc->plane);
9379         val = I915_READ(reg);
9380
9381         if ((val & DISPLAY_PLANE_ENABLE) &&
9382             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9383                 return false;
9384
9385         return true;
9386 }
9387
9388 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9389 {
9390         struct drm_device *dev = crtc->base.dev;
9391         struct drm_i915_private *dev_priv = dev->dev_private;
9392         u32 reg;
9393
9394         /* Clear any frame start delays used for debugging left by the BIOS */
9395         reg = PIPECONF(crtc->config.cpu_transcoder);
9396         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9397
9398         /* We need to sanitize the plane -> pipe mapping first because this will
9399          * disable the crtc (and hence change the state) if it is wrong. Note
9400          * that gen4+ has a fixed plane -> pipe mapping.  */
9401         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9402                 struct intel_connector *connector;
9403                 bool plane;
9404
9405                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9406                               crtc->base.base.id);
9407
9408                 /* Pipe has the wrong plane attached and the plane is active.
9409                  * Temporarily change the plane mapping and disable everything
9410                  * ...  */
9411                 plane = crtc->plane;
9412                 crtc->plane = !plane;
9413                 dev_priv->display.crtc_disable(&crtc->base);
9414                 crtc->plane = plane;
9415
9416                 /* ... and break all links. */
9417                 list_for_each_entry(connector, &dev->mode_config.connector_list,
9418                                     base.head) {
9419                         if (connector->encoder->base.crtc != &crtc->base)
9420                                 continue;
9421
9422                         intel_connector_break_all_links(connector);
9423                 }
9424
9425                 WARN_ON(crtc->active);
9426                 crtc->base.enabled = false;
9427         }
9428
9429         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9430             crtc->pipe == PIPE_A && !crtc->active) {
9431                 /* BIOS forgot to enable pipe A, this mostly happens after
9432                  * resume. Force-enable the pipe to fix this, the update_dpms
9433                  * call below we restore the pipe to the right state, but leave
9434                  * the required bits on. */
9435                 intel_enable_pipe_a(dev);
9436         }
9437
9438         /* Adjust the state of the output pipe according to whether we
9439          * have active connectors/encoders. */
9440         intel_crtc_update_dpms(&crtc->base);
9441
9442         if (crtc->active != crtc->base.enabled) {
9443                 struct intel_encoder *encoder;
9444
9445                 /* This can happen either due to bugs in the get_hw_state
9446                  * functions or because the pipe is force-enabled due to the
9447                  * pipe A quirk. */
9448                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9449                               crtc->base.base.id,
9450                               crtc->base.enabled ? "enabled" : "disabled",
9451                               crtc->active ? "enabled" : "disabled");
9452
9453                 crtc->base.enabled = crtc->active;
9454
9455                 /* Because we only establish the connector -> encoder ->
9456                  * crtc links if something is active, this means the
9457                  * crtc is now deactivated. Break the links. connector
9458                  * -> encoder links are only establish when things are
9459                  *  actually up, hence no need to break them. */
9460                 WARN_ON(crtc->active);
9461
9462                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9463                         WARN_ON(encoder->connectors_active);
9464                         encoder->base.crtc = NULL;
9465                 }
9466         }
9467 }
9468
9469 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9470 {
9471         struct intel_connector *connector;
9472         struct drm_device *dev = encoder->base.dev;
9473
9474         /* We need to check both for a crtc link (meaning that the
9475          * encoder is active and trying to read from a pipe) and the
9476          * pipe itself being active. */
9477         bool has_active_crtc = encoder->base.crtc &&
9478                 to_intel_crtc(encoder->base.crtc)->active;
9479
9480         if (encoder->connectors_active && !has_active_crtc) {
9481                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9482                               encoder->base.base.id,
9483                               drm_get_encoder_name(&encoder->base));
9484
9485                 /* Connector is active, but has no active pipe. This is
9486                  * fallout from our resume register restoring. Disable
9487                  * the encoder manually again. */
9488                 if (encoder->base.crtc) {
9489                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9490                                       encoder->base.base.id,
9491                                       drm_get_encoder_name(&encoder->base));
9492                         encoder->disable(encoder);
9493                 }
9494
9495                 /* Inconsistent output/port/pipe state happens presumably due to
9496                  * a bug in one of the get_hw_state functions. Or someplace else
9497                  * in our code, like the register restore mess on resume. Clamp
9498                  * things to off as a safer default. */
9499                 list_for_each_entry(connector,
9500                                     &dev->mode_config.connector_list,
9501                                     base.head) {
9502                         if (connector->encoder != encoder)
9503                                 continue;
9504
9505                         intel_connector_break_all_links(connector);
9506                 }
9507         }
9508         /* Enabled encoders without active connectors will be fixed in
9509          * the crtc fixup. */
9510 }
9511
9512 void i915_redisable_vga(struct drm_device *dev)
9513 {
9514         struct drm_i915_private *dev_priv = dev->dev_private;
9515         u32 vga_reg = i915_vgacntrl_reg(dev);
9516
9517         if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9518                 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9519                 i915_disable_vga(dev);
9520         }
9521 }
9522
9523 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9524  * and i915 state tracking structures. */
9525 void intel_modeset_setup_hw_state(struct drm_device *dev,
9526                                   bool force_restore)
9527 {
9528         struct drm_i915_private *dev_priv = dev->dev_private;
9529         enum pipe pipe;
9530         u32 tmp;
9531         struct drm_plane *plane;
9532         struct intel_crtc *crtc;
9533         struct intel_encoder *encoder;
9534         struct intel_connector *connector;
9535
9536         if (HAS_DDI(dev)) {
9537                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9538
9539                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9540                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9541                         case TRANS_DDI_EDP_INPUT_A_ON:
9542                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
9543                                 pipe = PIPE_A;
9544                                 break;
9545                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
9546                                 pipe = PIPE_B;
9547                                 break;
9548                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
9549                                 pipe = PIPE_C;
9550                                 break;
9551                         default:
9552                                 /* A bogus value has been programmed, disable
9553                                  * the transcoder */
9554                                 WARN(1, "Bogus eDP source %08x\n", tmp);
9555                                 intel_ddi_disable_transcoder_func(dev_priv,
9556                                                 TRANSCODER_EDP);
9557                                 goto setup_pipes;
9558                         }
9559
9560                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9561                         crtc->config.cpu_transcoder = TRANSCODER_EDP;
9562
9563                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9564                                       pipe_name(pipe));
9565                 }
9566         }
9567
9568 setup_pipes:
9569         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9570                             base.head) {
9571                 enum transcoder tmp = crtc->config.cpu_transcoder;
9572                 memset(&crtc->config, 0, sizeof(crtc->config));
9573                 crtc->config.cpu_transcoder = tmp;
9574
9575                 crtc->active = dev_priv->display.get_pipe_config(crtc,
9576                                                                  &crtc->config);
9577
9578                 crtc->base.enabled = crtc->active;
9579
9580                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9581                               crtc->base.base.id,
9582                               crtc->active ? "enabled" : "disabled");
9583         }
9584
9585         if (HAS_DDI(dev))
9586                 intel_ddi_setup_hw_pll_state(dev);
9587
9588         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9589                             base.head) {
9590                 pipe = 0;
9591
9592                 if (encoder->get_hw_state(encoder, &pipe)) {
9593                         encoder->base.crtc =
9594                                 dev_priv->pipe_to_crtc_mapping[pipe];
9595                 } else {
9596                         encoder->base.crtc = NULL;
9597                 }
9598
9599                 encoder->connectors_active = false;
9600                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9601                               encoder->base.base.id,
9602                               drm_get_encoder_name(&encoder->base),
9603                               encoder->base.crtc ? "enabled" : "disabled",
9604                               pipe);
9605         }
9606
9607         list_for_each_entry(connector, &dev->mode_config.connector_list,
9608                             base.head) {
9609                 if (connector->get_hw_state(connector)) {
9610                         connector->base.dpms = DRM_MODE_DPMS_ON;
9611                         connector->encoder->connectors_active = true;
9612                         connector->base.encoder = &connector->encoder->base;
9613                 } else {
9614                         connector->base.dpms = DRM_MODE_DPMS_OFF;
9615                         connector->base.encoder = NULL;
9616                 }
9617                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9618                               connector->base.base.id,
9619                               drm_get_connector_name(&connector->base),
9620                               connector->base.encoder ? "enabled" : "disabled");
9621         }
9622
9623         /* HW state is read out, now we need to sanitize this mess. */
9624         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9625                             base.head) {
9626                 intel_sanitize_encoder(encoder);
9627         }
9628
9629         for_each_pipe(pipe) {
9630                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9631                 intel_sanitize_crtc(crtc);
9632         }
9633
9634         if (force_restore) {
9635                 /*
9636                  * We need to use raw interfaces for restoring state to avoid
9637                  * checking (bogus) intermediate states.
9638                  */
9639                 for_each_pipe(pipe) {
9640                         struct drm_crtc *crtc =
9641                                 dev_priv->pipe_to_crtc_mapping[pipe];
9642
9643                         __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9644                                          crtc->fb);
9645                 }
9646                 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9647                         intel_plane_restore(plane);
9648
9649                 i915_redisable_vga(dev);
9650         } else {
9651                 intel_modeset_update_staged_output_state(dev);
9652         }
9653
9654         intel_modeset_check_state(dev);
9655
9656         drm_mode_config_reset(dev);
9657 }
9658
9659 void intel_modeset_gem_init(struct drm_device *dev)
9660 {
9661         intel_modeset_init_hw(dev);
9662
9663         intel_setup_overlay(dev);
9664
9665         intel_modeset_setup_hw_state(dev, false);
9666 }
9667
9668 void intel_modeset_cleanup(struct drm_device *dev)
9669 {
9670         struct drm_i915_private *dev_priv = dev->dev_private;
9671         struct drm_crtc *crtc;
9672         struct intel_crtc *intel_crtc;
9673
9674         /*
9675          * Interrupts and polling as the first thing to avoid creating havoc.
9676          * Too much stuff here (turning of rps, connectors, ...) would
9677          * experience fancy races otherwise.
9678          */
9679         drm_irq_uninstall(dev);
9680         cancel_work_sync(&dev_priv->hotplug_work);
9681         /*
9682          * Due to the hpd irq storm handling the hotplug work can re-arm the
9683          * poll handlers. Hence disable polling after hpd handling is shut down.
9684          */
9685         drm_kms_helper_poll_fini(dev);
9686
9687         mutex_lock(&dev->struct_mutex);
9688
9689         intel_unregister_dsm_handler();
9690
9691         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9692                 /* Skip inactive CRTCs */
9693                 if (!crtc->fb)
9694                         continue;
9695
9696                 intel_crtc = to_intel_crtc(crtc);
9697                 intel_increase_pllclock(crtc);
9698         }
9699
9700         intel_disable_fbc(dev);
9701
9702         intel_disable_gt_powersave(dev);
9703
9704         ironlake_teardown_rc6(dev);
9705
9706         mutex_unlock(&dev->struct_mutex);
9707
9708         /* flush any delayed tasks or pending work */
9709         flush_scheduled_work();
9710
9711         /* destroy backlight, if any, before the connectors */
9712         intel_panel_destroy_backlight(dev);
9713
9714         drm_mode_config_cleanup(dev);
9715
9716         intel_cleanup_overlay(dev);
9717 }
9718
9719 /*
9720  * Return which encoder is currently attached for connector.
9721  */
9722 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9723 {
9724         return &intel_attached_encoder(connector)->base;
9725 }
9726
9727 void intel_connector_attach_encoder(struct intel_connector *connector,
9728                                     struct intel_encoder *encoder)
9729 {
9730         connector->encoder = encoder;
9731         drm_mode_connector_attach_encoder(&connector->base,
9732                                           &encoder->base);
9733 }
9734
9735 /*
9736  * set vga decode state - true == enable VGA decode
9737  */
9738 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9739 {
9740         struct drm_i915_private *dev_priv = dev->dev_private;
9741         u16 gmch_ctrl;
9742
9743         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9744         if (state)
9745                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9746         else
9747                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9748         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9749         return 0;
9750 }
9751
9752 #ifdef CONFIG_DEBUG_FS
9753 #include <linux/seq_file.h>
9754
9755 struct intel_display_error_state {
9756         struct intel_cursor_error_state {
9757                 u32 control;
9758                 u32 position;
9759                 u32 base;
9760                 u32 size;
9761         } cursor[I915_MAX_PIPES];
9762
9763         struct intel_pipe_error_state {
9764                 u32 conf;
9765                 u32 source;
9766
9767                 u32 htotal;
9768                 u32 hblank;
9769                 u32 hsync;
9770                 u32 vtotal;
9771                 u32 vblank;
9772                 u32 vsync;
9773         } pipe[I915_MAX_PIPES];
9774
9775         struct intel_plane_error_state {
9776                 u32 control;
9777                 u32 stride;
9778                 u32 size;
9779                 u32 pos;
9780                 u32 addr;
9781                 u32 surface;
9782                 u32 tile_offset;
9783         } plane[I915_MAX_PIPES];
9784 };
9785
9786 struct intel_display_error_state *
9787 intel_display_capture_error_state(struct drm_device *dev)
9788 {
9789         drm_i915_private_t *dev_priv = dev->dev_private;
9790         struct intel_display_error_state *error;
9791         enum transcoder cpu_transcoder;
9792         int i;
9793
9794         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9795         if (error == NULL)
9796                 return NULL;
9797
9798         for_each_pipe(i) {
9799                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9800
9801                 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9802                         error->cursor[i].control = I915_READ(CURCNTR(i));
9803                         error->cursor[i].position = I915_READ(CURPOS(i));
9804                         error->cursor[i].base = I915_READ(CURBASE(i));
9805                 } else {
9806                         error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9807                         error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9808                         error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9809                 }
9810
9811                 error->plane[i].control = I915_READ(DSPCNTR(i));
9812                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9813                 if (INTEL_INFO(dev)->gen <= 3) {
9814                         error->plane[i].size = I915_READ(DSPSIZE(i));
9815                         error->plane[i].pos = I915_READ(DSPPOS(i));
9816                 }
9817                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9818                         error->plane[i].addr = I915_READ(DSPADDR(i));
9819                 if (INTEL_INFO(dev)->gen >= 4) {
9820                         error->plane[i].surface = I915_READ(DSPSURF(i));
9821                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9822                 }
9823
9824                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9825                 error->pipe[i].source = I915_READ(PIPESRC(i));
9826                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9827                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9828                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9829                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9830                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9831                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9832         }
9833
9834         return error;
9835 }
9836
9837 void
9838 intel_display_print_error_state(struct seq_file *m,
9839                                 struct drm_device *dev,
9840                                 struct intel_display_error_state *error)
9841 {
9842         int i;
9843
9844         seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
9845         for_each_pipe(i) {
9846                 seq_printf(m, "Pipe [%d]:\n", i);
9847                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9848                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9849                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9850                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9851                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9852                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9853                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9854                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9855
9856                 seq_printf(m, "Plane [%d]:\n", i);
9857                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9858                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9859                 if (INTEL_INFO(dev)->gen <= 3) {
9860                         seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9861                         seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9862                 }
9863                 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9864                         seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9865                 if (INTEL_INFO(dev)->gen >= 4) {
9866                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9867                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9868                 }
9869
9870                 seq_printf(m, "Cursor [%d]:\n", i);
9871                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9872                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9873                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9874         }
9875 }
9876 #endif