drivers/gpu/drm/radeon/cik.c

   1 /*
   2  * Copyright 2012 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include <linux/module.h>
  28 #include "drmP.h"
  29 #include "radeon.h"
  30 #include "radeon_asic.h"
  31 #include "cikd.h"
  32 #include "atom.h"
  33 #include "cik_blit_shaders.h"
  34
  35 /* GFX */
  36 #define CIK_PFP_UCODE_SIZE 2144
  37 #define CIK_ME_UCODE_SIZE 2144
  38 #define CIK_CE_UCODE_SIZE 2144
  39 /* compute */
  40 #define CIK_MEC_UCODE_SIZE 4192
  41 /* interrupts */
  42 #define BONAIRE_RLC_UCODE_SIZE 2048
  43 #define KB_RLC_UCODE_SIZE 2560
  44 #define KV_RLC_UCODE_SIZE 2560
  45 /* gddr controller */
  46 #define CIK_MC_UCODE_SIZE 7866
  47 /* sdma */
  48 #define CIK_SDMA_UCODE_SIZE 1050
  49 #define CIK_SDMA_UCODE_VERSION 64
  50
  51 MODULE_FIRMWARE("radeon/BONAIRE_pfp.bin");
  52 MODULE_FIRMWARE("radeon/BONAIRE_me.bin");
  53 MODULE_FIRMWARE("radeon/BONAIRE_ce.bin");
  54 MODULE_FIRMWARE("radeon/BONAIRE_mec.bin");
  55 MODULE_FIRMWARE("radeon/BONAIRE_mc.bin");
  56 MODULE_FIRMWARE("radeon/BONAIRE_rlc.bin");
  57 MODULE_FIRMWARE("radeon/BONAIRE_sdma.bin");
  58 MODULE_FIRMWARE("radeon/KAVERI_pfp.bin");
  59 MODULE_FIRMWARE("radeon/KAVERI_me.bin");
  60 MODULE_FIRMWARE("radeon/KAVERI_ce.bin");
  61 MODULE_FIRMWARE("radeon/KAVERI_mec.bin");
  62 MODULE_FIRMWARE("radeon/KAVERI_rlc.bin");
  63 MODULE_FIRMWARE("radeon/KAVERI_sdma.bin");
  64 MODULE_FIRMWARE("radeon/KABINI_pfp.bin");
  65 MODULE_FIRMWARE("radeon/KABINI_me.bin");
  66 MODULE_FIRMWARE("radeon/KABINI_ce.bin");
  67 MODULE_FIRMWARE("radeon/KABINI_mec.bin");
  68 MODULE_FIRMWARE("radeon/KABINI_rlc.bin");
  69 MODULE_FIRMWARE("radeon/KABINI_sdma.bin");
  70
  71 extern int r600_ih_ring_alloc(struct radeon_device *rdev);
  72 extern void r600_ih_ring_fini(struct radeon_device *rdev);
  73 extern void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
  74 extern void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
  75 extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
  76
  77 #define BONAIRE_IO_MC_REGS_SIZE 36
  78
  79 static const u32 bonaire_io_mc_regs[BONAIRE_IO_MC_REGS_SIZE][2] =
  80 {
  81         {0x00000070, 0x04400000},
  82         {0x00000071, 0x80c01803},
  83         {0x00000072, 0x00004004},
  84         {0x00000073, 0x00000100},
  85         {0x00000074, 0x00ff0000},
  86         {0x00000075, 0x34000000},
  87         {0x00000076, 0x08000014},
  88         {0x00000077, 0x00cc08ec},
  89         {0x00000078, 0x00000400},
  90         {0x00000079, 0x00000000},
  91         {0x0000007a, 0x04090000},
  92         {0x0000007c, 0x00000000},
  93         {0x0000007e, 0x4408a8e8},
  94         {0x0000007f, 0x00000304},
  95         {0x00000080, 0x00000000},
  96         {0x00000082, 0x00000001},
  97         {0x00000083, 0x00000002},
  98         {0x00000084, 0xf3e4f400},
  99         {0x00000085, 0x052024e3},
 100         {0x00000087, 0x00000000},
 101         {0x00000088, 0x01000000},
 102         {0x0000008a, 0x1c0a0000},
 103         {0x0000008b, 0xff010000},
 104         {0x0000008d, 0xffffefff},
 105         {0x0000008e, 0xfff3efff},
 106         {0x0000008f, 0xfff3efbf},
 107         {0x00000092, 0xf7ffffff},
 108         {0x00000093, 0xffffff7f},
 109         {0x00000095, 0x00101101},
 110         {0x00000096, 0x00000fff},
 111         {0x00000097, 0x00116fff},
 112         {0x00000098, 0x60010000},
 113         {0x00000099, 0x10010000},
 114         {0x0000009a, 0x00006000},
 115         {0x0000009b, 0x00001000},
 116         {0x0000009f, 0x00b48000}
 117 };
 118
 119 /* ucode loading */
 120 /**
 121  * ci_mc_load_microcode - load MC ucode into the hw
 122  *
 123  * @rdev: radeon_device pointer
 124  *
 125  * Load the GDDR MC ucode into the hw (CIK).
 126  * Returns 0 on success, error on failure.
 127  */
 128 static int ci_mc_load_microcode(struct radeon_device *rdev)
 129 {
 130         const __be32 *fw_data;
 131         u32 running, blackout = 0;
 132         u32 *io_mc_regs;
 133         int i, ucode_size, regs_size;
 134
 135         if (!rdev->mc_fw)
 136                 return -EINVAL;
 137
 138         switch (rdev->family) {
 139         case CHIP_BONAIRE:
 140         default:
 141                 io_mc_regs = (u32 *)&bonaire_io_mc_regs;
 142                 ucode_size = CIK_MC_UCODE_SIZE;
 143                 regs_size = BONAIRE_IO_MC_REGS_SIZE;
 144                 break;
 145         }
 146
 147         running = RREG32(MC_SEQ_SUP_CNTL) & RUN_MASK;
 148
 149         if (running == 0) {
 150                 if (running) {
 151                         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
 152                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
 153                 }
 154
 155                 /* reset the engine and set to writable */
 156                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 157                 WREG32(MC_SEQ_SUP_CNTL, 0x00000010);
 158
 159                 /* load mc io regs */
 160                 for (i = 0; i < regs_size; i++) {
 161                         WREG32(MC_SEQ_IO_DEBUG_INDEX, io_mc_regs[(i << 1)]);
 162                         WREG32(MC_SEQ_IO_DEBUG_DATA, io_mc_regs[(i << 1) + 1]);
 163                 }
 164                 /* load the MC ucode */
 165                 fw_data = (const __be32 *)rdev->mc_fw->data;
 166                 for (i = 0; i < ucode_size; i++)
 167                         WREG32(MC_SEQ_SUP_PGM, be32_to_cpup(fw_data++));
 168
 169                 /* put the engine back into the active state */
 170                 WREG32(MC_SEQ_SUP_CNTL, 0x00000008);
 171                 WREG32(MC_SEQ_SUP_CNTL, 0x00000004);
 172                 WREG32(MC_SEQ_SUP_CNTL, 0x00000001);
 173
 174                 /* wait for training to complete */
 175                 for (i = 0; i < rdev->usec_timeout; i++) {
 176                         if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D0)
 177                                 break;
 178                         udelay(1);
 179                 }
 180                 for (i = 0; i < rdev->usec_timeout; i++) {
 181                         if (RREG32(MC_SEQ_TRAIN_WAKEUP_CNTL) & TRAIN_DONE_D1)
 182                                 break;
 183                         udelay(1);
 184                 }
 185
 186                 if (running)
 187                         WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);
 188         }
 189
 190         return 0;
 191 }
 192
 193 /**
 194  * cik_init_microcode - load ucode images from disk
 195  *
 196  * @rdev: radeon_device pointer
 197  *
 198  * Use the firmware interface to load the ucode images into
 199  * the driver (not loaded into hw).
 200  * Returns 0 on success, error on failure.
 201  */
 202 static int cik_init_microcode(struct radeon_device *rdev)
 203 {
 204         struct platform_device *pdev;
 205         const char *chip_name;
 206         size_t pfp_req_size, me_req_size, ce_req_size,
 207                 mec_req_size, rlc_req_size, mc_req_size,
 208                 sdma_req_size;
 209         char fw_name[30];
 210         int err;
 211
 212         DRM_DEBUG("\n");
 213
 214         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
 215         err = IS_ERR(pdev);
 216         if (err) {
 217                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
 218                 return -EINVAL;
 219         }
 220
 221         switch (rdev->family) {
 222         case CHIP_BONAIRE:
 223                 chip_name = "BONAIRE";
 224                 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
 225                 me_req_size = CIK_ME_UCODE_SIZE * 4;
 226                 ce_req_size = CIK_CE_UCODE_SIZE * 4;
 227                 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
 228                 rlc_req_size = BONAIRE_RLC_UCODE_SIZE * 4;
 229                 mc_req_size = CIK_MC_UCODE_SIZE * 4;
 230                 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
 231                 break;
 232         case CHIP_KAVERI:
 233                 chip_name = "KAVERI";
 234                 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
 235                 me_req_size = CIK_ME_UCODE_SIZE * 4;
 236                 ce_req_size = CIK_CE_UCODE_SIZE * 4;
 237                 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
 238                 rlc_req_size = KV_RLC_UCODE_SIZE * 4;
 239                 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
 240                 break;
 241         case CHIP_KABINI:
 242                 chip_name = "KABINI";
 243                 pfp_req_size = CIK_PFP_UCODE_SIZE * 4;
 244                 me_req_size = CIK_ME_UCODE_SIZE * 4;
 245                 ce_req_size = CIK_CE_UCODE_SIZE * 4;
 246                 mec_req_size = CIK_MEC_UCODE_SIZE * 4;
 247                 rlc_req_size = KB_RLC_UCODE_SIZE * 4;
 248                 sdma_req_size = CIK_SDMA_UCODE_SIZE * 4;
 249                 break;
 250         default: BUG();
 251         }
 252
 253         DRM_INFO("Loading %s Microcode\n", chip_name);
 254
 255         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
 256         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
 257         if (err)
 258                 goto out;
 259         if (rdev->pfp_fw->size != pfp_req_size) {
 260                 printk(KERN_ERR
 261                        "cik_cp: Bogus length %zu in firmware \"%s\"\n",
 262                        rdev->pfp_fw->size, fw_name);
 263                 err = -EINVAL;
 264                 goto out;
 265         }
 266
 267         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
 268         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
 269         if (err)
 270                 goto out;
 271         if (rdev->me_fw->size != me_req_size) {
 272                 printk(KERN_ERR
 273                        "cik_cp: Bogus length %zu in firmware \"%s\"\n",
 274                        rdev->me_fw->size, fw_name);
 275                 err = -EINVAL;
 276         }
 277
 278         snprintf(fw_name, sizeof(fw_name), "radeon/%s_ce.bin", chip_name);
 279         err = request_firmware(&rdev->ce_fw, fw_name, &pdev->dev);
 280         if (err)
 281                 goto out;
 282         if (rdev->ce_fw->size != ce_req_size) {
 283                 printk(KERN_ERR
 284                        "cik_cp: Bogus length %zu in firmware \"%s\"\n",
 285                        rdev->ce_fw->size, fw_name);
 286                 err = -EINVAL;
 287         }
 288
 289         snprintf(fw_name, sizeof(fw_name), "radeon/%s_mec.bin", chip_name);
 290         err = request_firmware(&rdev->mec_fw, fw_name, &pdev->dev);
 291         if (err)
 292                 goto out;
 293         if (rdev->mec_fw->size != mec_req_size) {
 294                 printk(KERN_ERR
 295                        "cik_cp: Bogus length %zu in firmware \"%s\"\n",
 296                        rdev->mec_fw->size, fw_name);
 297                 err = -EINVAL;
 298         }
 299
 300         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", chip_name);
 301         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
 302         if (err)
 303                 goto out;
 304         if (rdev->rlc_fw->size != rlc_req_size) {
 305                 printk(KERN_ERR
 306                        "cik_rlc: Bogus length %zu in firmware \"%s\"\n",
 307                        rdev->rlc_fw->size, fw_name);
 308                 err = -EINVAL;
 309         }
 310
 311         snprintf(fw_name, sizeof(fw_name), "radeon/%s_sdma.bin", chip_name);
 312         err = request_firmware(&rdev->sdma_fw, fw_name, &pdev->dev);
 313         if (err)
 314                 goto out;
 315         if (rdev->sdma_fw->size != sdma_req_size) {
 316                 printk(KERN_ERR
 317                        "cik_sdma: Bogus length %zu in firmware \"%s\"\n",
 318                        rdev->sdma_fw->size, fw_name);
 319                 err = -EINVAL;
 320         }
 321
 322         /* No MC ucode on APUs */
 323         if (!(rdev->flags & RADEON_IS_IGP)) {
 324                 snprintf(fw_name, sizeof(fw_name), "radeon/%s_mc.bin", chip_name);
 325                 err = request_firmware(&rdev->mc_fw, fw_name, &pdev->dev);
 326                 if (err)
 327                         goto out;
 328                 if (rdev->mc_fw->size != mc_req_size) {
 329                         printk(KERN_ERR
 330                                "cik_mc: Bogus length %zu in firmware \"%s\"\n",
 331                                rdev->mc_fw->size, fw_name);
 332                         err = -EINVAL;
 333                 }
 334         }
 335
 336 out:
 337         platform_device_unregister(pdev);
 338
 339         if (err) {
 340                 if (err != -EINVAL)
 341                         printk(KERN_ERR
 342                                "cik_cp: Failed to load firmware \"%s\"\n",
 343                                fw_name);
 344                 release_firmware(rdev->pfp_fw);
 345                 rdev->pfp_fw = NULL;
 346                 release_firmware(rdev->me_fw);
 347                 rdev->me_fw = NULL;
 348                 release_firmware(rdev->ce_fw);
 349                 rdev->ce_fw = NULL;
 350                 release_firmware(rdev->rlc_fw);
 351                 rdev->rlc_fw = NULL;
 352                 release_firmware(rdev->mc_fw);
 353                 rdev->mc_fw = NULL;
 354         }
 355         return err;
 356 }
 357
 358 /*
 359  * Core functions
 360  */
 361 /**
 362  * cik_tiling_mode_table_init - init the hw tiling table
 363  *
 364  * @rdev: radeon_device pointer
 365  *
 366  * Starting with SI, the tiling setup is done globally in a
 367  * set of 32 tiling modes.  Rather than selecting each set of
 368  * parameters per surface as on older asics, we just select
 369  * which index in the tiling table we want to use, and the
 370  * surface uses those parameters (CIK).
 371  */
 372 static void cik_tiling_mode_table_init(struct radeon_device *rdev)
 373 {
 374         const u32 num_tile_mode_states = 32;
 375         const u32 num_secondary_tile_mode_states = 16;
 376         u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
 377         u32 num_pipe_configs;
 378         u32 num_rbs = rdev->config.cik.max_backends_per_se *
 379                 rdev->config.cik.max_shader_engines;
 380
 381         switch (rdev->config.cik.mem_row_size_in_kb) {
 382         case 1:
 383                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_1KB;
 384                 break;
 385         case 2:
 386         default:
 387                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_2KB;
 388                 break;
 389         case 4:
 390                 split_equal_to_row_size = ADDR_SURF_TILE_SPLIT_4KB;
 391                 break;
 392         }
 393
 394         num_pipe_configs = rdev->config.cik.max_tile_pipes;
 395         if (num_pipe_configs > 8)
 396                 num_pipe_configs = 8; /* ??? */
 397
 398         if (num_pipe_configs == 8) {
 399                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 400                         switch (reg_offset) {
 401                         case 0:
 402                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 403                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 404                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 405                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
 406                                 break;
 407                         case 1:
 408                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 409                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 410                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 411                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
 412                                 break;
 413                         case 2:
 414                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 415                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 416                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 417                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 418                                 break;
 419                         case 3:
 420                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 421                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 422                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 423                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
 424                                 break;
 425                         case 4:
 426                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 427                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 428                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 429                                                  TILE_SPLIT(split_equal_to_row_size));
 430                                 break;
 431                         case 5:
 432                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 433                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 434                                 break;
 435                         case 6:
 436                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 437                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 438                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 439                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 440                                 break;
 441                         case 7:
 442                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 443                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 444                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 445                                                  TILE_SPLIT(split_equal_to_row_size));
 446                                 break;
 447                         case 8:
 448                                 gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 449                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
 450                                 break;
 451                         case 9:
 452                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 453                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
 454                                 break;
 455                         case 10:
 456                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 457                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 458                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 459                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 460                                 break;
 461                         case 11:
 462                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 463                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 464                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 465                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 466                                 break;
 467                         case 12:
 468                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 469                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 470                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 471                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 472                                 break;
 473                         case 13:
 474                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 475                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
 476                                 break;
 477                         case 14:
 478                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 479                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 480                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 481                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 482                                 break;
 483                         case 16:
 484                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 485                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 486                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 487                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 488                                 break;
 489                         case 17:
 490                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 491                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 492                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 493                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 494                                 break;
 495                         case 27:
 496                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 497                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
 498                                 break;
 499                         case 28:
 500                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 501                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 502                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 503                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 504                                 break;
 505                         case 29:
 506                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 507                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 508                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 509                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 510                                 break;
 511                         case 30:
 512                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 513                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 514                                                  PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
 515                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 516                                 break;
 517                         default:
 518                                 gb_tile_moden = 0;
 519                                 break;
 520                         }
 521                         WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 522                 }
 523                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
 524                         switch (reg_offset) {
 525                         case 0:
 526                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 527                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 528                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 529                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 530                                 break;
 531                         case 1:
 532                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 533                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 534                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 535                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 536                                 break;
 537                         case 2:
 538                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 539                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 540                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 541                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 542                                 break;
 543                         case 3:
 544                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 545                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 546                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 547                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 548                                 break;
 549                         case 4:
 550                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 551                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 552                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 553                                                  NUM_BANKS(ADDR_SURF_8_BANK));
 554                                 break;
 555                         case 5:
 556                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 557                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 558                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 559                                                  NUM_BANKS(ADDR_SURF_4_BANK));
 560                                 break;
 561                         case 6:
 562                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 563                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 564                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 565                                                  NUM_BANKS(ADDR_SURF_2_BANK));
 566                                 break;
 567                         case 8:
 568                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 569                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
 570                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 571                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 572                                 break;
 573                         case 9:
 574                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 575                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 576                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 577                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 578                                 break;
 579                         case 10:
 580                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 581                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 582                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 583                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 584                                 break;
 585                         case 11:
 586                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 587                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 588                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 589                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 590                                 break;
 591                         case 12:
 592                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 593                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 594                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 595                                                  NUM_BANKS(ADDR_SURF_8_BANK));
 596                                 break;
 597                         case 13:
 598                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 599                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 600                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 601                                                  NUM_BANKS(ADDR_SURF_4_BANK));
 602                                 break;
 603                         case 14:
 604                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 605                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 606                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 607                                                  NUM_BANKS(ADDR_SURF_2_BANK));
 608                                 break;
 609                         default:
 610                                 gb_tile_moden = 0;
 611                                 break;
 612                         }
 613                         WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 614                 }
 615         } else if (num_pipe_configs == 4) {
 616                 if (num_rbs == 4) {
 617                         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 618                                 switch (reg_offset) {
 619                                 case 0:
 620                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 621                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 622                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 623                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
 624                                         break;
 625                                 case 1:
 626                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 627                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 628                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 629                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
 630                                         break;
 631                                 case 2:
 632                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 633                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 634                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 635                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 636                                         break;
 637                                 case 3:
 638                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 639                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 640                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 641                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
 642                                         break;
 643                                 case 4:
 644                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 645                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 646                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 647                                                          TILE_SPLIT(split_equal_to_row_size));
 648                                         break;
 649                                 case 5:
 650                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 651                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 652                                         break;
 653                                 case 6:
 654                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 655                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 656                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 657                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 658                                         break;
 659                                 case 7:
 660                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 661                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 662                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 663                                                          TILE_SPLIT(split_equal_to_row_size));
 664                                         break;
 665                                 case 8:
 666                                         gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 667                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16));
 668                                         break;
 669                                 case 9:
 670                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 671                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
 672                                         break;
 673                                 case 10:
 674                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 675                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 676                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 677                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 678                                         break;
 679                                 case 11:
 680                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 681                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 682                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 683                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 684                                         break;
 685                                 case 12:
 686                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 687                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 688                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 689                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 690                                         break;
 691                                 case 13:
 692                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 693                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
 694                                         break;
 695                                 case 14:
 696                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 697                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 698                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 699                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 700                                         break;
 701                                 case 16:
 702                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 703                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 704                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 705                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 706                                         break;
 707                                 case 17:
 708                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 709                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 710                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 711                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 712                                         break;
 713                                 case 27:
 714                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 715                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
 716                                         break;
 717                                 case 28:
 718                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 719                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 720                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 721                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 722                                         break;
 723                                 case 29:
 724                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 725                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 726                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 727                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 728                                         break;
 729                                 case 30:
 730                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 731                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 732                                                          PIPE_CONFIG(ADDR_SURF_P4_16x16) |
 733                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 734                                         break;
 735                                 default:
 736                                         gb_tile_moden = 0;
 737                                         break;
 738                                 }
 739                                 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 740                         }
 741                 } else if (num_rbs < 4) {
 742                         for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 743                                 switch (reg_offset) {
 744                                 case 0:
 745                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 746                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 747                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 748                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
 749                                         break;
 750                                 case 1:
 751                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 752                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 753                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 754                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
 755                                         break;
 756                                 case 2:
 757                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 758                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 759                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 760                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 761                                         break;
 762                                 case 3:
 763                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 764                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 765                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 766                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
 767                                         break;
 768                                 case 4:
 769                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 770                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 771                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 772                                                          TILE_SPLIT(split_equal_to_row_size));
 773                                         break;
 774                                 case 5:
 775                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 776                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 777                                         break;
 778                                 case 6:
 779                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 780                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 781                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 782                                                          TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 783                                         break;
 784                                 case 7:
 785                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 786                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 787                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 788                                                          TILE_SPLIT(split_equal_to_row_size));
 789                                         break;
 790                                 case 8:
 791                                         gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
 792                                                  PIPE_CONFIG(ADDR_SURF_P4_8x16));
 793                                         break;
 794                                 case 9:
 795                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 796                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
 797                                         break;
 798                                 case 10:
 799                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 800                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 801                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 802                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 803                                         break;
 804                                 case 11:
 805                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 806                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 807                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 808                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 809                                         break;
 810                                 case 12:
 811                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 812                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
 813                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 814                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 815                                         break;
 816                                 case 13:
 817                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 818                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
 819                                         break;
 820                                 case 14:
 821                                         gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 822                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 823                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 824                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 825                                         break;
 826                                 case 16:
 827                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 828                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 829                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 830                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 831                                         break;
 832                                 case 17:
 833                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 834                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
 835                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 836                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 837                                         break;
 838                                 case 27:
 839                                         gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 840                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
 841                                         break;
 842                                 case 28:
 843                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 844                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 845                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 846                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 847                                         break;
 848                                 case 29:
 849                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
 850                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 851                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 852                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 853                                         break;
 854                                 case 30:
 855                                         gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 856                                                          MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
 857                                                          PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 858                                                          SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
 859                                         break;
 860                                 default:
 861                                         gb_tile_moden = 0;
 862                                         break;
 863                                 }
 864                                 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 865                         }
 866                 }
 867                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
 868                         switch (reg_offset) {
 869                         case 0:
 870                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 871                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 872                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 873                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 874                                 break;
 875                         case 1:
 876                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 877                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 878                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 879                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 880                                 break;
 881                         case 2:
 882                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 883                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 884                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 885                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 886                                 break;
 887                         case 3:
 888                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 889                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 890                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 891                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 892                                 break;
 893                         case 4:
 894                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 895                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 896                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 897                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 898                                 break;
 899                         case 5:
 900                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 901                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 902                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 903                                                  NUM_BANKS(ADDR_SURF_8_BANK));
 904                                 break;
 905                         case 6:
 906                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 907                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 908                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 909                                                  NUM_BANKS(ADDR_SURF_4_BANK));
 910                                 break;
 911                         case 8:
 912                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 913                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
 914                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 915                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 916                                 break;
 917                         case 9:
 918                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 919                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 920                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 921                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 922                                 break;
 923                         case 10:
 924                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 925                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
 926                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 927                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 928                                 break;
 929                         case 11:
 930                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 931                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
 932                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
 933                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 934                                 break;
 935                         case 12:
 936                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 937                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 938                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 939                                                  NUM_BANKS(ADDR_SURF_16_BANK));
 940                                 break;
 941                         case 13:
 942                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 943                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 944                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
 945                                                  NUM_BANKS(ADDR_SURF_8_BANK));
 946                                 break;
 947                         case 14:
 948                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 949                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
 950                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
 951                                                  NUM_BANKS(ADDR_SURF_4_BANK));
 952                                 break;
 953                         default:
 954                                 gb_tile_moden = 0;
 955                                 break;
 956                         }
 957                         WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
 958                 }
 959         } else if (num_pipe_configs == 2) {
 960                 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 961                         switch (reg_offset) {
 962                         case 0:
 963                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 964                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 965                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 966                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
 967                                 break;
 968                         case 1:
 969                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 970                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 971                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 972                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
 973                                 break;
 974                         case 2:
 975                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 976                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 977                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 978                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
 979                                 break;
 980                         case 3:
 981                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 982                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 983                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 984                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
 985                                 break;
 986                         case 4:
 987                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
 988                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 989                                                  PIPE_CONFIG(ADDR_SURF_P2) |
 990                                                  TILE_SPLIT(split_equal_to_row_size));
 991                                 break;
 992                         case 5:
 993                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
 994                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
 995                                 break;
 996                         case 6:
 997                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
 998                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
 999                                                  PIPE_CONFIG(ADDR_SURF_P2) |
1000                                                  TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
1001                                 break;
1002                         case 7:
1003                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1004                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
1005                                                  PIPE_CONFIG(ADDR_SURF_P2) |
1006                                                  TILE_SPLIT(split_equal_to_row_size));
1007                                 break;
1008                         case 8:
1009                                 gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED);
1010                                 break;
1011                         case 9:
1012                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1013                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
1014                                 break;
1015                         case 10:
1016                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1017                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1018                                                  PIPE_CONFIG(ADDR_SURF_P2) |
1019                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1020                                 break;
1021                         case 11:
1022                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1023                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1024                                                  PIPE_CONFIG(ADDR_SURF_P2) |
1025                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1026                                 break;
1027                         case 12:
1028                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1029                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
1030                                                  PIPE_CONFIG(ADDR_SURF_P2) |
1031                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1032                                 break;
1033                         case 13:
1034                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1035                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
1036                                 break;
1037                         case 14:
1038                                 gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
1039                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1040                                                  PIPE_CONFIG(ADDR_SURF_P2) |
1041                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1042                                 break;
1043                         case 16:
1044                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1045                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1046                                                  PIPE_CONFIG(ADDR_SURF_P2) |
1047                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1048                                 break;
1049                         case 17:
1050                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1051                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
1052                                                  PIPE_CONFIG(ADDR_SURF_P2) |
1053                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1054                                 break;
1055                         case 27:
1056                                 gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
1057                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
1058                                 break;
1059                         case 28:
1060                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1061                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1062                                                  PIPE_CONFIG(ADDR_SURF_P2) |
1063                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1064                                 break;
1065                         case 29:
1066                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
1067                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1068                                                  PIPE_CONFIG(ADDR_SURF_P2) |
1069                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1070                                 break;
1071                         case 30:
1072                                 gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
1073                                                  MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
1074                                                  PIPE_CONFIG(ADDR_SURF_P2) |
1075                                                  SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
1076                                 break;
1077                         default:
1078                                 gb_tile_moden = 0;
1079                                 break;
1080                         }
1081                         WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1082                 }
1083                 for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
1084                         switch (reg_offset) {
1085                         case 0:
1086                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1087                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1088                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1089                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1090                                 break;
1091                         case 1:
1092                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1093                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1094                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1095                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1096                                 break;
1097                         case 2:
1098                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1099                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1100                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1101                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1102                                 break;
1103                         case 3:
1104                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1105                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1106                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1107                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1108                                 break;
1109                         case 4:
1110                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1111                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1112                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1113                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1114                                 break;
1115                         case 5:
1116                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1117                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1118                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1119                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1120                                 break;
1121                         case 6:
1122                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1123                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1124                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1125                                                  NUM_BANKS(ADDR_SURF_8_BANK));
1126                                 break;
1127                         case 8:
1128                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1129                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
1130                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1131                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1132                                 break;
1133                         case 9:
1134                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
1135                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1136                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1137                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1138                                 break;
1139                         case 10:
1140                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1141                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
1142                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1143                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1144                                 break;
1145                         case 11:
1146                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
1147                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1148                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1149                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1150                                 break;
1151                         case 12:
1152                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1153                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
1154                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1155                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1156                                 break;
1157                         case 13:
1158                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1159                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1160                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
1161                                                  NUM_BANKS(ADDR_SURF_16_BANK));
1162                                 break;
1163                         case 14:
1164                                 gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
1165                                                  BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
1166                                                  MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
1167                                                  NUM_BANKS(ADDR_SURF_8_BANK));
1168                                 break;
1169                         default:
1170                                 gb_tile_moden = 0;
1171                                 break;
1172                         }
1173                         WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
1174                 }
1175         } else
1176                 DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
1177 }
1178
1179 /**
1180  * cik_select_se_sh - select which SE, SH to address
1181  *
1182  * @rdev: radeon_device pointer
1183  * @se_num: shader engine to address
1184  * @sh_num: sh block to address
1185  *
1186  * Select which SE, SH combinations to address. Certain
1187  * registers are instanced per SE or SH.  0xffffffff means
1188  * broadcast to all SEs or SHs (CIK).
1189  */
1190 static void cik_select_se_sh(struct radeon_device *rdev,
1191                              u32 se_num, u32 sh_num)
1192 {
1193         u32 data = INSTANCE_BROADCAST_WRITES;
1194
1195         if ((se_num == 0xffffffff) && (sh_num == 0xffffffff))
1196                 data = SH_BROADCAST_WRITES | SE_BROADCAST_WRITES;
1197         else if (se_num == 0xffffffff)
1198                 data |= SE_BROADCAST_WRITES | SH_INDEX(sh_num);
1199         else if (sh_num == 0xffffffff)
1200                 data |= SH_BROADCAST_WRITES | SE_INDEX(se_num);
1201         else
1202                 data |= SH_INDEX(sh_num) | SE_INDEX(se_num);
1203         WREG32(GRBM_GFX_INDEX, data);
1204 }
1205
1206 /**
1207  * cik_create_bitmask - create a bitmask
1208  *
1209  * @bit_width: length of the mask
1210  *
1211  * create a variable length bit mask (CIK).
1212  * Returns the bitmask.
1213  */
1214 static u32 cik_create_bitmask(u32 bit_width)
1215 {
1216         u32 i, mask = 0;
1217
1218         for (i = 0; i < bit_width; i++) {
1219                 mask <<= 1;
1220                 mask |= 1;
1221         }
1222         return mask;
1223 }
1224
1225 /**
1226  * cik_select_se_sh - select which SE, SH to address
1227  *
1228  * @rdev: radeon_device pointer
1229  * @max_rb_num: max RBs (render backends) for the asic
1230  * @se_num: number of SEs (shader engines) for the asic
1231  * @sh_per_se: number of SH blocks per SE for the asic
1232  *
1233  * Calculates the bitmask of disabled RBs (CIK).
1234  * Returns the disabled RB bitmask.
1235  */
1236 static u32 cik_get_rb_disabled(struct radeon_device *rdev,
1237                               u32 max_rb_num, u32 se_num,
1238                               u32 sh_per_se)
1239 {
1240         u32 data, mask;
1241
1242         data = RREG32(CC_RB_BACKEND_DISABLE);
1243         if (data & 1)
1244                 data &= BACKEND_DISABLE_MASK;
1245         else
1246                 data = 0;
1247         data |= RREG32(GC_USER_RB_BACKEND_DISABLE);
1248
1249         data >>= BACKEND_DISABLE_SHIFT;
1250
1251         mask = cik_create_bitmask(max_rb_num / se_num / sh_per_se);
1252
1253         return data & mask;
1254 }
1255
1256 /**
1257  * cik_setup_rb - setup the RBs on the asic
1258  *
1259  * @rdev: radeon_device pointer
1260  * @se_num: number of SEs (shader engines) for the asic
1261  * @sh_per_se: number of SH blocks per SE for the asic
1262  * @max_rb_num: max RBs (render backends) for the asic
1263  *
1264  * Configures per-SE/SH RB registers (CIK).
1265  */
1266 static void cik_setup_rb(struct radeon_device *rdev,
1267                          u32 se_num, u32 sh_per_se,
1268                          u32 max_rb_num)
1269 {
1270         int i, j;
1271         u32 data, mask;
1272         u32 disabled_rbs = 0;
1273         u32 enabled_rbs = 0;
1274
1275         for (i = 0; i < se_num; i++) {
1276                 for (j = 0; j < sh_per_se; j++) {
1277                         cik_select_se_sh(rdev, i, j);
1278                         data = cik_get_rb_disabled(rdev, max_rb_num, se_num, sh_per_se);
1279                         disabled_rbs |= data << ((i * sh_per_se + j) * CIK_RB_BITMAP_WIDTH_PER_SH);
1280                 }
1281         }
1282         cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1283
1284         mask = 1;
1285         for (i = 0; i < max_rb_num; i++) {
1286                 if (!(disabled_rbs & mask))
1287                         enabled_rbs |= mask;
1288                 mask <<= 1;
1289         }
1290
1291         for (i = 0; i < se_num; i++) {
1292                 cik_select_se_sh(rdev, i, 0xffffffff);
1293                 data = 0;
1294                 for (j = 0; j < sh_per_se; j++) {
1295                         switch (enabled_rbs & 3) {
1296                         case 1:
1297                                 data |= (RASTER_CONFIG_RB_MAP_0 << (i * sh_per_se + j) * 2);
1298                                 break;
1299                         case 2:
1300                                 data |= (RASTER_CONFIG_RB_MAP_3 << (i * sh_per_se + j) * 2);
1301                                 break;
1302                         case 3:
1303                         default:
1304                                 data |= (RASTER_CONFIG_RB_MAP_2 << (i * sh_per_se + j) * 2);
1305                                 break;
1306                         }
1307                         enabled_rbs >>= 2;
1308                 }
1309                 WREG32(PA_SC_RASTER_CONFIG, data);
1310         }
1311         cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
1312 }
1313
1314 /**
1315  * cik_gpu_init - setup the 3D engine
1316  *
1317  * @rdev: radeon_device pointer
1318  *
1319  * Configures the 3D engine and tiling configuration
1320  * registers so that the 3D engine is usable.
1321  */
1322 static void cik_gpu_init(struct radeon_device *rdev)
1323 {
1324         u32 gb_addr_config = RREG32(GB_ADDR_CONFIG);
1325         u32 mc_shared_chmap, mc_arb_ramcfg;
1326         u32 hdp_host_path_cntl;
1327         u32 tmp;
1328         int i, j;
1329
1330         switch (rdev->family) {
1331         case CHIP_BONAIRE:
1332                 rdev->config.cik.max_shader_engines = 2;
1333                 rdev->config.cik.max_tile_pipes = 4;
1334                 rdev->config.cik.max_cu_per_sh = 7;
1335                 rdev->config.cik.max_sh_per_se = 1;
1336                 rdev->config.cik.max_backends_per_se = 2;
1337                 rdev->config.cik.max_texture_channel_caches = 4;
1338                 rdev->config.cik.max_gprs = 256;
1339                 rdev->config.cik.max_gs_threads = 32;
1340                 rdev->config.cik.max_hw_contexts = 8;
1341
1342                 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
1343                 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
1344                 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
1345                 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
1346                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
1347                 break;
1348         case CHIP_KAVERI:
1349                 /* TODO */
1350                 break;
1351         case CHIP_KABINI:
1352         default:
1353                 rdev->config.cik.max_shader_engines = 1;
1354                 rdev->config.cik.max_tile_pipes = 2;
1355                 rdev->config.cik.max_cu_per_sh = 2;
1356                 rdev->config.cik.max_sh_per_se = 1;
1357                 rdev->config.cik.max_backends_per_se = 1;
1358                 rdev->config.cik.max_texture_channel_caches = 2;
1359                 rdev->config.cik.max_gprs = 256;
1360                 rdev->config.cik.max_gs_threads = 16;
1361                 rdev->config.cik.max_hw_contexts = 8;
1362
1363                 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
1364                 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
1365                 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
1366                 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
1367                 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
1368                 break;
1369         }
1370
1371         /* Initialize HDP */
1372         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1373                 WREG32((0x2c14 + j), 0x00000000);
1374                 WREG32((0x2c18 + j), 0x00000000);
1375                 WREG32((0x2c1c + j), 0x00000000);
1376                 WREG32((0x2c20 + j), 0x00000000);
1377                 WREG32((0x2c24 + j), 0x00000000);
1378         }
1379
1380         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1381
1382         WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1383
1384         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1385         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1386
1387         rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes;
1388         rdev->config.cik.mem_max_burst_length_bytes = 256;
1389         tmp = (mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT;
1390         rdev->config.cik.mem_row_size_in_kb = (4 * (1 << (8 + tmp))) / 1024;
1391         if (rdev->config.cik.mem_row_size_in_kb > 4)
1392                 rdev->config.cik.mem_row_size_in_kb = 4;
1393         /* XXX use MC settings? */
1394         rdev->config.cik.shader_engine_tile_size = 32;
1395         rdev->config.cik.num_gpus = 1;
1396         rdev->config.cik.multi_gpu_tile_size = 64;
1397
1398         /* fix up row size */
1399         gb_addr_config &= ~ROW_SIZE_MASK;
1400         switch (rdev->config.cik.mem_row_size_in_kb) {
1401         case 1:
1402         default:
1403                 gb_addr_config |= ROW_SIZE(0);
1404                 break;
1405         case 2:
1406                 gb_addr_config |= ROW_SIZE(1);
1407                 break;
1408         case 4:
1409                 gb_addr_config |= ROW_SIZE(2);
1410                 break;
1411         }
1412
1413         /* setup tiling info dword.  gb_addr_config is not adequate since it does
1414          * not have bank info, so create a custom tiling dword.
1415          * bits 3:0   num_pipes
1416          * bits 7:4   num_banks
1417          * bits 11:8  group_size
1418          * bits 15:12 row_size
1419          */
1420         rdev->config.cik.tile_config = 0;
1421         switch (rdev->config.cik.num_tile_pipes) {
1422         case 1:
1423                 rdev->config.cik.tile_config |= (0 << 0);
1424                 break;
1425         case 2:
1426                 rdev->config.cik.tile_config |= (1 << 0);
1427                 break;
1428         case 4:
1429                 rdev->config.cik.tile_config |= (2 << 0);
1430                 break;
1431         case 8:
1432         default:
1433                 /* XXX what about 12? */
1434                 rdev->config.cik.tile_config |= (3 << 0);
1435                 break;
1436         }
1437         if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
1438                 rdev->config.cik.tile_config |= 1 << 4;
1439         else
1440                 rdev->config.cik.tile_config |= 0 << 4;
1441         rdev->config.cik.tile_config |=
1442                 ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
1443         rdev->config.cik.tile_config |=
1444                 ((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
1445
1446         WREG32(GB_ADDR_CONFIG, gb_addr_config);
1447         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1448         WREG32(DMIF_ADDR_CALC, gb_addr_config);
1449         WREG32(SDMA0_TILING_CONFIG + SDMA0_REGISTER_OFFSET, gb_addr_config & 0x70);
1450         WREG32(SDMA0_TILING_CONFIG + SDMA1_REGISTER_OFFSET, gb_addr_config & 0x70);
1451
1452         cik_tiling_mode_table_init(rdev);
1453
1454         cik_setup_rb(rdev, rdev->config.cik.max_shader_engines,
1455                      rdev->config.cik.max_sh_per_se,
1456                      rdev->config.cik.max_backends_per_se);
1457
1458         /* set HW defaults for 3D engine */
1459         WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
1460
1461         WREG32(SX_DEBUG_1, 0x20);
1462
1463         WREG32(TA_CNTL_AUX, 0x00010000);
1464
1465         tmp = RREG32(SPI_CONFIG_CNTL);
1466         tmp |= 0x03000000;
1467         WREG32(SPI_CONFIG_CNTL, tmp);
1468
1469         WREG32(SQ_CONFIG, 1);
1470
1471         WREG32(DB_DEBUG, 0);
1472
1473         tmp = RREG32(DB_DEBUG2) & ~0xf00fffff;
1474         tmp |= 0x00000400;
1475         WREG32(DB_DEBUG2, tmp);
1476
1477         tmp = RREG32(DB_DEBUG3) & ~0x0002021c;
1478         tmp |= 0x00020200;
1479         WREG32(DB_DEBUG3, tmp);
1480
1481         tmp = RREG32(CB_HW_CONTROL) & ~0x00010000;
1482         tmp |= 0x00018208;
1483         WREG32(CB_HW_CONTROL, tmp);
1484
1485         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1486
1487         WREG32(PA_SC_FIFO_SIZE, (SC_FRONTEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_frontend) |
1488                                  SC_BACKEND_PRIM_FIFO_SIZE(rdev->config.cik.sc_prim_fifo_size_backend) |
1489                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.cik.sc_hiz_tile_fifo_size) |
1490                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.cik.sc_earlyz_tile_fifo_size)));
1491
1492         WREG32(VGT_NUM_INSTANCES, 1);
1493
1494         WREG32(CP_PERFMON_CNTL, 0);
1495
1496         WREG32(SQ_CONFIG, 0);
1497
1498         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1499                                           FORCE_EOV_MAX_REZ_CNT(255)));
1500
1501         WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC) |
1502                AUTO_INVLD_EN(ES_AND_GS_AUTO));
1503
1504         WREG32(VGT_GS_VERTEX_REUSE, 16);
1505         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1506
1507         tmp = RREG32(HDP_MISC_CNTL);
1508         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
1509         WREG32(HDP_MISC_CNTL, tmp);
1510
1511         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1512         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1513
1514         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1515         WREG32(PA_SC_ENHANCE, ENABLE_PA_SC_OUT_OF_ORDER);
1516
1517         udelay(50);
1518 }
1519
1520 /*
1521  * GPU scratch registers helpers function.
1522  */
1523 /**
1524  * cik_scratch_init - setup driver info for CP scratch regs
1525  *
1526  * @rdev: radeon_device pointer
1527  *
1528  * Set up the number and offset of the CP scratch registers.
1529  * NOTE: use of CP scratch registers is a legacy inferface and
1530  * is not used by default on newer asics (r6xx+).  On newer asics,
1531  * memory buffers are used for fences rather than scratch regs.
1532  */
1533 static void cik_scratch_init(struct radeon_device *rdev)
1534 {
1535         int i;
1536
1537         rdev->scratch.num_reg = 7;
1538         rdev->scratch.reg_base = SCRATCH_REG0;
1539         for (i = 0; i < rdev->scratch.num_reg; i++) {
1540                 rdev->scratch.free[i] = true;
1541                 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
1542         }
1543 }
1544
1545 /**
1546  * cik_ring_test - basic gfx ring test
1547  *
1548  * @rdev: radeon_device pointer
1549  * @ring: radeon_ring structure holding ring information
1550  *
1551  * Allocate a scratch register and write to it using the gfx ring (CIK).
1552  * Provides a basic gfx ring test to verify that the ring is working.
1553  * Used by cik_cp_gfx_resume();
1554  * Returns 0 on success, error on failure.
1555  */
1556 int cik_ring_test(struct radeon_device *rdev, struct radeon_ring *ring)
1557 {
1558         uint32_t scratch;
1559         uint32_t tmp = 0;
1560         unsigned i;
1561         int r;
1562
1563         r = radeon_scratch_get(rdev, &scratch);
1564         if (r) {
1565                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1566                 return r;
1567         }
1568         WREG32(scratch, 0xCAFEDEAD);
1569         r = radeon_ring_lock(rdev, ring, 3);
1570         if (r) {
1571                 DRM_ERROR("radeon: cp failed to lock ring %d (%d).\n", ring->idx, r);
1572                 radeon_scratch_free(rdev, scratch);
1573                 return r;
1574         }
1575         radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
1576         radeon_ring_write(ring, ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2));
1577         radeon_ring_write(ring, 0xDEADBEEF);
1578         radeon_ring_unlock_commit(rdev, ring);
1579         for (i = 0; i < rdev->usec_timeout; i++) {
1580                 tmp = RREG32(scratch);
1581                 if (tmp == 0xDEADBEEF)
1582                         break;
1583                 DRM_UDELAY(1);
1584         }
1585         if (i < rdev->usec_timeout) {
1586                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
1587         } else {
1588                 DRM_ERROR("radeon: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
1589                           ring->idx, scratch, tmp);
1590                 r = -EINVAL;
1591         }
1592         radeon_scratch_free(rdev, scratch);
1593         return r;
1594 }
1595
1596 /**
1597  * cik_fence_ring_emit - emit a fence on the gfx ring
1598  *
1599  * @rdev: radeon_device pointer
1600  * @fence: radeon fence object
1601  *
1602  * Emits a fence sequnce number on the gfx ring and flushes
1603  * GPU caches.
1604  */
1605 void cik_fence_ring_emit(struct radeon_device *rdev,
1606                          struct radeon_fence *fence)
1607 {
1608         struct radeon_ring *ring = &rdev->ring[fence->ring];
1609         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
1610
1611         /* EVENT_WRITE_EOP - flush caches, send int */
1612         radeon_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
1613         radeon_ring_write(ring, (EOP_TCL1_ACTION_EN |
1614                                  EOP_TC_ACTION_EN |
1615                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
1616                                  EVENT_INDEX(5)));
1617         radeon_ring_write(ring, addr & 0xfffffffc);
1618         radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2));
1619         radeon_ring_write(ring, fence->seq);
1620         radeon_ring_write(ring, 0);
1621         /* HDP flush */
1622         /* We should be using the new WAIT_REG_MEM special op packet here
1623          * but it causes the CP to hang
1624          */
1625         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1626         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
1627                                  WRITE_DATA_DST_SEL(0)));
1628         radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
1629         radeon_ring_write(ring, 0);
1630         radeon_ring_write(ring, 0);
1631 }
1632
1633 void cik_semaphore_ring_emit(struct radeon_device *rdev,
1634                              struct radeon_ring *ring,
1635                              struct radeon_semaphore *semaphore,
1636                              bool emit_wait)
1637 {
1638         uint64_t addr = semaphore->gpu_addr;
1639         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
1640
1641         radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
1642         radeon_ring_write(ring, addr & 0xffffffff);
1643         radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
1644 }
1645
1646 /*
1647  * IB stuff
1648  */
1649 /**
1650  * cik_ring_ib_execute - emit an IB (Indirect Buffer) on the gfx ring
1651  *
1652  * @rdev: radeon_device pointer
1653  * @ib: radeon indirect buffer object
1654  *
1655  * Emits an DE (drawing engine) or CE (constant engine) IB
1656  * on the gfx ring.  IBs are usually generated by userspace
1657  * acceleration drivers and submitted to the kernel for
1658  * sheduling on the ring.  This function schedules the IB
1659  * on the gfx ring for execution by the GPU.
1660  */
1661 void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1662 {
1663         struct radeon_ring *ring = &rdev->ring[ib->ring];
1664         u32 header, control = INDIRECT_BUFFER_VALID;
1665
1666         if (ib->is_const_ib) {
1667                 /* set switch buffer packet before const IB */
1668                 radeon_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
1669                 radeon_ring_write(ring, 0);
1670
1671                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
1672         } else {
1673                 u32 next_rptr;
1674                 if (ring->rptr_save_reg) {
1675                         next_rptr = ring->wptr + 3 + 4;
1676                         radeon_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
1677                         radeon_ring_write(ring, ((ring->rptr_save_reg -
1678                                                   PACKET3_SET_UCONFIG_REG_START) >> 2));
1679                         radeon_ring_write(ring, next_rptr);
1680                 } else if (rdev->wb.enabled) {
1681                         next_rptr = ring->wptr + 5 + 4;
1682                         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
1683                         radeon_ring_write(ring, WRITE_DATA_DST_SEL(1));
1684                         radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
1685                         radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
1686                         radeon_ring_write(ring, next_rptr);
1687                 }
1688
1689                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
1690         }
1691
1692         control |= ib->length_dw |
1693                 (ib->vm ? (ib->vm->id << 24) : 0);
1694
1695         radeon_ring_write(ring, header);
1696         radeon_ring_write(ring,
1697 #ifdef __BIG_ENDIAN
1698                           (2 << 0) |
1699 #endif
1700                           (ib->gpu_addr & 0xFFFFFFFC));
1701         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFFFF);
1702         radeon_ring_write(ring, control);
1703 }
1704
1705 /**
1706  * cik_ib_test - basic gfx ring IB test
1707  *
1708  * @rdev: radeon_device pointer
1709  * @ring: radeon_ring structure holding ring information
1710  *
1711  * Allocate an IB and execute it on the gfx ring (CIK).
1712  * Provides a basic gfx ring test to verify that IBs are working.
1713  * Returns 0 on success, error on failure.
1714  */
1715 int cik_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
1716 {
1717         struct radeon_ib ib;
1718         uint32_t scratch;
1719         uint32_t tmp = 0;
1720         unsigned i;
1721         int r;
1722
1723         r = radeon_scratch_get(rdev, &scratch);
1724         if (r) {
1725                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
1726                 return r;
1727         }
1728         WREG32(scratch, 0xCAFEDEAD);
1729         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
1730         if (r) {
1731                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
1732                 return r;
1733         }
1734         ib.ptr[0] = PACKET3(PACKET3_SET_UCONFIG_REG, 1);
1735         ib.ptr[1] = ((scratch - PACKET3_SET_UCONFIG_REG_START) >> 2);
1736         ib.ptr[2] = 0xDEADBEEF;
1737         ib.length_dw = 3;
1738         r = radeon_ib_schedule(rdev, &ib, NULL);
1739         if (r) {
1740                 radeon_scratch_free(rdev, scratch);
1741                 radeon_ib_free(rdev, &ib);
1742                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
1743                 return r;
1744         }
1745         r = radeon_fence_wait(ib.fence, false);
1746         if (r) {
1747                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
1748                 return r;
1749         }
1750         for (i = 0; i < rdev->usec_timeout; i++) {
1751                 tmp = RREG32(scratch);
1752                 if (tmp == 0xDEADBEEF)
1753                         break;
1754                 DRM_UDELAY(1);
1755         }
1756         if (i < rdev->usec_timeout) {
1757                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
1758         } else {
1759                 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
1760                           scratch, tmp);
1761                 r = -EINVAL;
1762         }
1763         radeon_scratch_free(rdev, scratch);
1764         radeon_ib_free(rdev, &ib);
1765         return r;
1766 }
1767
1768 /*
1769  * CP.
1770  * On CIK, gfx and compute now have independant command processors.
1771  *
1772  * GFX
1773  * Gfx consists of a single ring and can process both gfx jobs and
1774  * compute jobs.  The gfx CP consists of three microengines (ME):
1775  * PFP - Pre-Fetch Parser
1776  * ME - Micro Engine
1777  * CE - Constant Engine
1778  * The PFP and ME make up what is considered the Drawing Engine (DE).
1779  * The CE is an asynchronous engine used for updating buffer desciptors
1780  * used by the DE so that they can be loaded into cache in parallel
1781  * while the DE is processing state update packets.
1782  *
1783  * Compute
1784  * The compute CP consists of two microengines (ME):
1785  * MEC1 - Compute MicroEngine 1
1786  * MEC2 - Compute MicroEngine 2
1787  * Each MEC supports 4 compute pipes and each pipe supports 8 queues.
1788  * The queues are exposed to userspace and are programmed directly
1789  * by the compute runtime.
1790  */
1791 /**
1792  * cik_cp_gfx_enable - enable/disable the gfx CP MEs
1793  *
1794  * @rdev: radeon_device pointer
1795  * @enable: enable or disable the MEs
1796  *
1797  * Halts or unhalts the gfx MEs.
1798  */
1799 static void cik_cp_gfx_enable(struct radeon_device *rdev, bool enable)
1800 {
1801         if (enable)
1802                 WREG32(CP_ME_CNTL, 0);
1803         else {
1804                 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT));
1805                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1806         }
1807         udelay(50);
1808 }
1809
1810 /**
1811  * cik_cp_gfx_load_microcode - load the gfx CP ME ucode
1812  *
1813  * @rdev: radeon_device pointer
1814  *
1815  * Loads the gfx PFP, ME, and CE ucode.
1816  * Returns 0 for success, -EINVAL if the ucode is not available.
1817  */
1818 static int cik_cp_gfx_load_microcode(struct radeon_device *rdev)
1819 {
1820         const __be32 *fw_data;
1821         int i;
1822
1823         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->ce_fw)
1824                 return -EINVAL;
1825
1826         cik_cp_gfx_enable(rdev, false);
1827
1828         /* PFP */
1829         fw_data = (const __be32 *)rdev->pfp_fw->data;
1830         WREG32(CP_PFP_UCODE_ADDR, 0);
1831         for (i = 0; i < CIK_PFP_UCODE_SIZE; i++)
1832                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1833         WREG32(CP_PFP_UCODE_ADDR, 0);
1834
1835         /* CE */
1836         fw_data = (const __be32 *)rdev->ce_fw->data;
1837         WREG32(CP_CE_UCODE_ADDR, 0);
1838         for (i = 0; i < CIK_CE_UCODE_SIZE; i++)
1839                 WREG32(CP_CE_UCODE_DATA, be32_to_cpup(fw_data++));
1840         WREG32(CP_CE_UCODE_ADDR, 0);
1841
1842         /* ME */
1843         fw_data = (const __be32 *)rdev->me_fw->data;
1844         WREG32(CP_ME_RAM_WADDR, 0);
1845         for (i = 0; i < CIK_ME_UCODE_SIZE; i++)
1846                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1847         WREG32(CP_ME_RAM_WADDR, 0);
1848
1849         WREG32(CP_PFP_UCODE_ADDR, 0);
1850         WREG32(CP_CE_UCODE_ADDR, 0);
1851         WREG32(CP_ME_RAM_WADDR, 0);
1852         WREG32(CP_ME_RAM_RADDR, 0);
1853         return 0;
1854 }
1855
1856 /**
1857  * cik_cp_gfx_start - start the gfx ring
1858  *
1859  * @rdev: radeon_device pointer
1860  *
1861  * Enables the ring and loads the clear state context and other
1862  * packets required to init the ring.
1863  * Returns 0 for success, error for failure.
1864  */
1865 static int cik_cp_gfx_start(struct radeon_device *rdev)
1866 {
1867         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1868         int r, i;
1869
1870         /* init the CP */
1871         WREG32(CP_MAX_CONTEXT, rdev->config.cik.max_hw_contexts - 1);
1872         WREG32(CP_ENDIAN_SWAP, 0);
1873         WREG32(CP_DEVICE_ID, 1);
1874
1875         cik_cp_gfx_enable(rdev, true);
1876
1877         r = radeon_ring_lock(rdev, ring, cik_default_size + 17);
1878         if (r) {
1879                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1880                 return r;
1881         }
1882
1883         /* init the CE partitions.  CE only used for gfx on CIK */
1884         radeon_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
1885         radeon_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
1886         radeon_ring_write(ring, 0xc000);
1887         radeon_ring_write(ring, 0xc000);
1888
1889         /* setup clear context state */
1890         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1891         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1892
1893         radeon_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
1894         radeon_ring_write(ring, 0x80000000);
1895         radeon_ring_write(ring, 0x80000000);
1896
1897         for (i = 0; i < cik_default_size; i++)
1898                 radeon_ring_write(ring, cik_default_state[i]);
1899
1900         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1901         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1902
1903         /* set clear context state */
1904         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1905         radeon_ring_write(ring, 0);
1906
1907         radeon_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1908         radeon_ring_write(ring, 0x00000316);
1909         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1910         radeon_ring_write(ring, 0x00000010); /* VGT_OUT_DEALLOC_CNTL */
1911
1912         radeon_ring_unlock_commit(rdev, ring);
1913
1914         return 0;
1915 }
1916
1917 /**
1918  * cik_cp_gfx_fini - stop the gfx ring
1919  *
1920  * @rdev: radeon_device pointer
1921  *
1922  * Stop the gfx ring and tear down the driver ring
1923  * info.
1924  */
1925 static void cik_cp_gfx_fini(struct radeon_device *rdev)
1926 {
1927         cik_cp_gfx_enable(rdev, false);
1928         radeon_ring_fini(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1929 }
1930
1931 /**
1932  * cik_cp_gfx_resume - setup the gfx ring buffer registers
1933  *
1934  * @rdev: radeon_device pointer
1935  *
1936  * Program the location and size of the gfx ring buffer
1937  * and test it to make sure it's working.
1938  * Returns 0 for success, error for failure.
1939  */
1940 static int cik_cp_gfx_resume(struct radeon_device *rdev)
1941 {
1942         struct radeon_ring *ring;
1943         u32 tmp;
1944         u32 rb_bufsz;
1945         u64 rb_addr;
1946         int r;
1947
1948         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1949         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1950
1951         /* Set the write pointer delay */
1952         WREG32(CP_RB_WPTR_DELAY, 0);
1953
1954         /* set the RB to use vmid 0 */
1955         WREG32(CP_RB_VMID, 0);
1956
1957         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1958
1959         /* ring 0 - compute and gfx */
1960         /* Set ring buffer size */
1961         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1962         rb_bufsz = drm_order(ring->ring_size / 8);
1963         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1964 #ifdef __BIG_ENDIAN
1965         tmp |= BUF_SWAP_32BIT;
1966 #endif
1967         WREG32(CP_RB0_CNTL, tmp);
1968
1969         /* Initialize the ring buffer's read and write pointers */
1970         WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1971         ring->wptr = 0;
1972         WREG32(CP_RB0_WPTR, ring->wptr);
1973
1974         /* set the wb address wether it's enabled or not */
1975         WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1976         WREG32(CP_RB0_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1977
1978         /* scratch register shadowing is no longer supported */
1979         WREG32(SCRATCH_UMSK, 0);
1980
1981         if (!rdev->wb.enabled)
1982                 tmp |= RB_NO_UPDATE;
1983
1984         mdelay(1);
1985         WREG32(CP_RB0_CNTL, tmp);
1986
1987         rb_addr = ring->gpu_addr >> 8;
1988         WREG32(CP_RB0_BASE, rb_addr);
1989         WREG32(CP_RB0_BASE_HI, upper_32_bits(rb_addr));
1990
1991         ring->rptr = RREG32(CP_RB0_RPTR);
1992
1993         /* start the ring */
1994         cik_cp_gfx_start(rdev);
1995         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = true;
1996         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
1997         if (r) {
1998                 rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ready = false;
1999                 return r;
2000         }
2001         return 0;
2002 }
2003
2004 /**
2005  * cik_cp_compute_enable - enable/disable the compute CP MEs
2006  *
2007  * @rdev: radeon_device pointer
2008  * @enable: enable or disable the MEs
2009  *
2010  * Halts or unhalts the compute MEs.
2011  */
2012 static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable)
2013 {
2014         if (enable)
2015                 WREG32(CP_MEC_CNTL, 0);
2016         else
2017                 WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT));
2018         udelay(50);
2019 }
2020
2021 /**
2022  * cik_cp_compute_load_microcode - load the compute CP ME ucode
2023  *
2024  * @rdev: radeon_device pointer
2025  *
2026  * Loads the compute MEC1&2 ucode.
2027  * Returns 0 for success, -EINVAL if the ucode is not available.
2028  */
2029 static int cik_cp_compute_load_microcode(struct radeon_device *rdev)
2030 {
2031         const __be32 *fw_data;
2032         int i;
2033
2034         if (!rdev->mec_fw)
2035                 return -EINVAL;
2036
2037         cik_cp_compute_enable(rdev, false);
2038
2039         /* MEC1 */
2040         fw_data = (const __be32 *)rdev->mec_fw->data;
2041         WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
2042         for (i = 0; i < CIK_MEC_UCODE_SIZE; i++)
2043                 WREG32(CP_MEC_ME1_UCODE_DATA, be32_to_cpup(fw_data++));
2044         WREG32(CP_MEC_ME1_UCODE_ADDR, 0);
2045
2046         if (rdev->family == CHIP_KAVERI) {
2047                 /* MEC2 */
2048                 fw_data = (const __be32 *)rdev->mec_fw->data;
2049                 WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
2050                 for (i = 0; i < CIK_MEC_UCODE_SIZE; i++)
2051                         WREG32(CP_MEC_ME2_UCODE_DATA, be32_to_cpup(fw_data++));
2052                 WREG32(CP_MEC_ME2_UCODE_ADDR, 0);
2053         }
2054
2055         return 0;
2056 }
2057
2058 /**
2059  * cik_cp_compute_start - start the compute queues
2060  *
2061  * @rdev: radeon_device pointer
2062  *
2063  * Enable the compute queues.
2064  * Returns 0 for success, error for failure.
2065  */
2066 static int cik_cp_compute_start(struct radeon_device *rdev)
2067 {
2068         //todo
2069         return 0;
2070 }
2071
2072 /**
2073  * cik_cp_compute_fini - stop the compute queues
2074  *
2075  * @rdev: radeon_device pointer
2076  *
2077  * Stop the compute queues and tear down the driver queue
2078  * info.
2079  */
2080 static void cik_cp_compute_fini(struct radeon_device *rdev)
2081 {
2082         cik_cp_compute_enable(rdev, false);
2083         //todo
2084 }
2085
2086 /**
2087  * cik_cp_compute_resume - setup the compute queue registers
2088  *
2089  * @rdev: radeon_device pointer
2090  *
2091  * Program the compute queues and test them to make sure they
2092  * are working.
2093  * Returns 0 for success, error for failure.
2094  */
2095 static int cik_cp_compute_resume(struct radeon_device *rdev)
2096 {
2097         int r;
2098
2099         //todo
2100         r = cik_cp_compute_start(rdev);
2101         if (r)
2102                 return r;
2103         return 0;
2104 }
2105
2106 /* XXX temporary wrappers to handle both compute and gfx */
2107 /* XXX */
2108 static void cik_cp_enable(struct radeon_device *rdev, bool enable)
2109 {
2110         cik_cp_gfx_enable(rdev, enable);
2111         cik_cp_compute_enable(rdev, enable);
2112 }
2113
2114 /* XXX */
2115 static int cik_cp_load_microcode(struct radeon_device *rdev)
2116 {
2117         int r;
2118
2119         r = cik_cp_gfx_load_microcode(rdev);
2120         if (r)
2121                 return r;
2122         r = cik_cp_compute_load_microcode(rdev);
2123         if (r)
2124                 return r;
2125
2126         return 0;
2127 }
2128
2129 /* XXX */
2130 static void cik_cp_fini(struct radeon_device *rdev)
2131 {
2132         cik_cp_gfx_fini(rdev);
2133         cik_cp_compute_fini(rdev);
2134 }
2135
2136 /* XXX */
2137 static int cik_cp_resume(struct radeon_device *rdev)
2138 {
2139         int r;
2140
2141         /* Reset all cp blocks */
2142         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2143         RREG32(GRBM_SOFT_RESET);
2144         mdelay(15);
2145         WREG32(GRBM_SOFT_RESET, 0);
2146         RREG32(GRBM_SOFT_RESET);
2147
2148         r = cik_cp_load_microcode(rdev);
2149         if (r)
2150                 return r;
2151
2152         r = cik_cp_gfx_resume(rdev);
2153         if (r)
2154                 return r;
2155         r = cik_cp_compute_resume(rdev);
2156         if (r)
2157                 return r;
2158
2159         return 0;
2160 }
2161
2162 /*
2163  * sDMA - System DMA
2164  * Starting with CIK, the GPU has new asynchronous
2165  * DMA engines.  These engines are used for compute
2166  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
2167  * and each one supports 1 ring buffer used for gfx
2168  * and 2 queues used for compute.
2169  *
2170  * The programming model is very similar to the CP
2171  * (ring buffer, IBs, etc.), but sDMA has it's own
2172  * packet format that is different from the PM4 format
2173  * used by the CP. sDMA supports copying data, writing
2174  * embedded data, solid fills, and a number of other
2175  * things.  It also has support for tiling/detiling of
2176  * buffers.
2177  */
2178 /**
2179  * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine
2180  *
2181  * @rdev: radeon_device pointer
2182  * @ib: IB object to schedule
2183  *
2184  * Schedule an IB in the DMA ring (CIK).
2185  */
2186 void cik_sdma_ring_ib_execute(struct radeon_device *rdev,
2187                               struct radeon_ib *ib)
2188 {
2189         struct radeon_ring *ring = &rdev->ring[ib->ring];
2190         u32 extra_bits = (ib->vm ? ib->vm->id : 0) & 0xf;
2191
2192         if (rdev->wb.enabled) {
2193                 u32 next_rptr = ring->wptr + 5;
2194                 while ((next_rptr & 7) != 4)
2195                         next_rptr++;
2196                 next_rptr += 4;
2197                 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
2198                 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
2199                 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
2200                 radeon_ring_write(ring, 1); /* number of DWs to follow */
2201                 radeon_ring_write(ring, next_rptr);
2202         }
2203
2204         /* IB packet must end on a 8 DW boundary */
2205         while ((ring->wptr & 7) != 4)
2206                 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
2207         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
2208         radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
2209         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff);
2210         radeon_ring_write(ring, ib->length_dw);
2211
2212 }
2213
2214 /**
2215  * cik_sdma_fence_ring_emit - emit a fence on the DMA ring
2216  *
2217  * @rdev: radeon_device pointer
2218  * @fence: radeon fence object
2219  *
2220  * Add a DMA fence packet to the ring to write
2221  * the fence seq number and DMA trap packet to generate
2222  * an interrupt if needed (CIK).
2223  */
2224 void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
2225                               struct radeon_fence *fence)
2226 {
2227         struct radeon_ring *ring = &rdev->ring[fence->ring];
2228         u64 addr = rdev->fence_drv[fence->ring].gpu_addr;
2229         u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
2230                           SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
2231         u32 ref_and_mask;
2232
2233         if (fence->ring == R600_RING_TYPE_DMA_INDEX)
2234                 ref_and_mask = SDMA0;
2235         else
2236                 ref_and_mask = SDMA1;
2237
2238         /* write the fence */
2239         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
2240         radeon_ring_write(ring, addr & 0xffffffff);
2241         radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2242         radeon_ring_write(ring, fence->seq);
2243         /* generate an interrupt */
2244         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
2245         /* flush HDP */
2246         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
2247         radeon_ring_write(ring, GPU_HDP_FLUSH_DONE);
2248         radeon_ring_write(ring, GPU_HDP_FLUSH_REQ);
2249         radeon_ring_write(ring, ref_and_mask); /* REFERENCE */
2250         radeon_ring_write(ring, ref_and_mask); /* MASK */
2251         radeon_ring_write(ring, (4 << 16) | 10); /* RETRY_COUNT, POLL_INTERVAL */
2252 }
2253
2254 /**
2255  * cik_sdma_semaphore_ring_emit - emit a semaphore on the dma ring
2256  *
2257  * @rdev: radeon_device pointer
2258  * @ring: radeon_ring structure holding ring information
2259  * @semaphore: radeon semaphore object
2260  * @emit_wait: wait or signal semaphore
2261  *
2262  * Add a DMA semaphore packet to the ring wait on or signal
2263  * other rings (CIK).
2264  */
2265 void cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
2266                                   struct radeon_ring *ring,
2267                                   struct radeon_semaphore *semaphore,
2268                                   bool emit_wait)
2269 {
2270         u64 addr = semaphore->gpu_addr;
2271         u32 extra_bits = emit_wait ? 0 : SDMA_SEMAPHORE_EXTRA_S;
2272
2273         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
2274         radeon_ring_write(ring, addr & 0xfffffff8);
2275         radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
2276 }
2277
2278 /**
2279  * cik_sdma_gfx_stop - stop the gfx async dma engines
2280  *
2281  * @rdev: radeon_device pointer
2282  *
2283  * Stop the gfx async dma ring buffers (CIK).
2284  */
2285 static void cik_sdma_gfx_stop(struct radeon_device *rdev)
2286 {
2287         u32 rb_cntl, reg_offset;
2288         int i;
2289
2290         radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
2291
2292         for (i = 0; i < 2; i++) {
2293                 if (i == 0)
2294                         reg_offset = SDMA0_REGISTER_OFFSET;
2295                 else
2296                         reg_offset = SDMA1_REGISTER_OFFSET;
2297                 rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset);
2298                 rb_cntl &= ~SDMA_RB_ENABLE;
2299                 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
2300                 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, 0);
2301         }
2302 }
2303
2304 /**
2305  * cik_sdma_rlc_stop - stop the compute async dma engines
2306  *
2307  * @rdev: radeon_device pointer
2308  *
2309  * Stop the compute async dma queues (CIK).
2310  */
2311 static void cik_sdma_rlc_stop(struct radeon_device *rdev)
2312 {
2313         /* XXX todo */
2314 }
2315
2316 /**
2317  * cik_sdma_enable - stop the async dma engines
2318  *
2319  * @rdev: radeon_device pointer
2320  * @enable: enable/disable the DMA MEs.
2321  *
2322  * Halt or unhalt the async dma engines (CIK).
2323  */
2324 static void cik_sdma_enable(struct radeon_device *rdev, bool enable)
2325 {
2326         u32 me_cntl, reg_offset;
2327         int i;
2328
2329         for (i = 0; i < 2; i++) {
2330                 if (i == 0)
2331                         reg_offset = SDMA0_REGISTER_OFFSET;
2332                 else
2333                         reg_offset = SDMA1_REGISTER_OFFSET;
2334                 me_cntl = RREG32(SDMA0_ME_CNTL + reg_offset);
2335                 if (enable)
2336                         me_cntl &= ~SDMA_HALT;
2337                 else
2338                         me_cntl |= SDMA_HALT;
2339                 WREG32(SDMA0_ME_CNTL + reg_offset, me_cntl);
2340         }
2341 }
2342
2343 /**
2344  * cik_sdma_gfx_resume - setup and start the async dma engines
2345  *
2346  * @rdev: radeon_device pointer
2347  *
2348  * Set up the gfx DMA ring buffers and enable them (CIK).
2349  * Returns 0 for success, error for failure.
2350  */
2351 static int cik_sdma_gfx_resume(struct radeon_device *rdev)
2352 {
2353         struct radeon_ring *ring;
2354         u32 rb_cntl, ib_cntl;
2355         u32 rb_bufsz;
2356         u32 reg_offset, wb_offset;
2357         int i, r;
2358
2359         for (i = 0; i < 2; i++) {
2360                 if (i == 0) {
2361                         ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2362                         reg_offset = SDMA0_REGISTER_OFFSET;
2363                         wb_offset = R600_WB_DMA_RPTR_OFFSET;
2364                 } else {
2365                         ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX];
2366                         reg_offset = SDMA1_REGISTER_OFFSET;
2367                         wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET;
2368                 }
2369
2370                 WREG32(SDMA0_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0);
2371                 WREG32(SDMA0_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
2372
2373                 /* Set ring buffer size in dwords */
2374                 rb_bufsz = drm_order(ring->ring_size / 4);
2375                 rb_cntl = rb_bufsz << 1;
2376 #ifdef __BIG_ENDIAN
2377                 rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE;
2378 #endif
2379                 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl);
2380
2381                 /* Initialize the ring buffer's read and write pointers */
2382                 WREG32(SDMA0_GFX_RB_RPTR + reg_offset, 0);
2383                 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, 0);
2384
2385                 /* set the wb address whether it's enabled or not */
2386                 WREG32(SDMA0_GFX_RB_RPTR_ADDR_HI + reg_offset,
2387                        upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
2388                 WREG32(SDMA0_GFX_RB_RPTR_ADDR_LO + reg_offset,
2389                        ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC));
2390
2391                 if (rdev->wb.enabled)
2392                         rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE;
2393
2394                 WREG32(SDMA0_GFX_RB_BASE + reg_offset, ring->gpu_addr >> 8);
2395                 WREG32(SDMA0_GFX_RB_BASE_HI + reg_offset, ring->gpu_addr >> 40);
2396
2397                 ring->wptr = 0;
2398                 WREG32(SDMA0_GFX_RB_WPTR + reg_offset, ring->wptr << 2);
2399
2400                 ring->rptr = RREG32(SDMA0_GFX_RB_RPTR + reg_offset) >> 2;
2401
2402                 /* enable DMA RB */
2403                 WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE);
2404
2405                 ib_cntl = SDMA_IB_ENABLE;
2406 #ifdef __BIG_ENDIAN
2407                 ib_cntl |= SDMA_IB_SWAP_ENABLE;
2408 #endif
2409                 /* enable DMA IBs */
2410                 WREG32(SDMA0_GFX_IB_CNTL + reg_offset, ib_cntl);
2411
2412                 ring->ready = true;
2413
2414                 r = radeon_ring_test(rdev, ring->idx, ring);
2415                 if (r) {
2416                         ring->ready = false;
2417                         return r;
2418                 }
2419         }
2420
2421         radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
2422
2423         return 0;
2424 }
2425
2426 /**
2427  * cik_sdma_rlc_resume - setup and start the async dma engines
2428  *
2429  * @rdev: radeon_device pointer
2430  *
2431  * Set up the compute DMA queues and enable them (CIK).
2432  * Returns 0 for success, error for failure.
2433  */
2434 static int cik_sdma_rlc_resume(struct radeon_device *rdev)
2435 {
2436         /* XXX todo */
2437         return 0;
2438 }
2439
2440 /**
2441  * cik_sdma_load_microcode - load the sDMA ME ucode
2442  *
2443  * @rdev: radeon_device pointer
2444  *
2445  * Loads the sDMA0/1 ucode.
2446  * Returns 0 for success, -EINVAL if the ucode is not available.
2447  */
2448 static int cik_sdma_load_microcode(struct radeon_device *rdev)
2449 {
2450         const __be32 *fw_data;
2451         int i;
2452
2453         if (!rdev->sdma_fw)
2454                 return -EINVAL;
2455
2456         /* stop the gfx rings and rlc compute queues */
2457         cik_sdma_gfx_stop(rdev);
2458         cik_sdma_rlc_stop(rdev);
2459
2460         /* halt the MEs */
2461         cik_sdma_enable(rdev, false);
2462
2463         /* sdma0 */
2464         fw_data = (const __be32 *)rdev->sdma_fw->data;
2465         WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
2466         for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
2467                 WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, be32_to_cpup(fw_data++));
2468         WREG32(SDMA0_UCODE_DATA + SDMA0_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
2469
2470         /* sdma1 */
2471         fw_data = (const __be32 *)rdev->sdma_fw->data;
2472         WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
2473         for (i = 0; i < CIK_SDMA_UCODE_SIZE; i++)
2474                 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, be32_to_cpup(fw_data++));
2475         WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION);
2476
2477         WREG32(SDMA0_UCODE_ADDR + SDMA0_REGISTER_OFFSET, 0);
2478         WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0);
2479         return 0;
2480 }
2481
2482 /**
2483  * cik_sdma_resume - setup and start the async dma engines
2484  *
2485  * @rdev: radeon_device pointer
2486  *
2487  * Set up the DMA engines and enable them (CIK).
2488  * Returns 0 for success, error for failure.
2489  */
2490 static int cik_sdma_resume(struct radeon_device *rdev)
2491 {
2492         int r;
2493
2494         /* Reset dma */
2495         WREG32(SRBM_SOFT_RESET, SOFT_RESET_SDMA | SOFT_RESET_SDMA1);
2496         RREG32(SRBM_SOFT_RESET);
2497         udelay(50);
2498         WREG32(SRBM_SOFT_RESET, 0);
2499         RREG32(SRBM_SOFT_RESET);
2500
2501         r = cik_sdma_load_microcode(rdev);
2502         if (r)
2503                 return r;
2504
2505         /* unhalt the MEs */
2506         cik_sdma_enable(rdev, true);
2507
2508         /* start the gfx rings and rlc compute queues */
2509         r = cik_sdma_gfx_resume(rdev);
2510         if (r)
2511                 return r;
2512         r = cik_sdma_rlc_resume(rdev);
2513         if (r)
2514                 return r;
2515
2516         return 0;
2517 }
2518
2519 /**
2520  * cik_sdma_fini - tear down the async dma engines
2521  *
2522  * @rdev: radeon_device pointer
2523  *
2524  * Stop the async dma engines and free the rings (CIK).
2525  */
2526 static void cik_sdma_fini(struct radeon_device *rdev)
2527 {
2528         /* stop the gfx rings and rlc compute queues */
2529         cik_sdma_gfx_stop(rdev);
2530         cik_sdma_rlc_stop(rdev);
2531         /* halt the MEs */
2532         cik_sdma_enable(rdev, false);
2533         radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]);
2534         radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]);
2535         /* XXX - compute dma queue tear down */
2536 }
2537
2538 /**
2539  * cik_copy_dma - copy pages using the DMA engine
2540  *
2541  * @rdev: radeon_device pointer
2542  * @src_offset: src GPU address
2543  * @dst_offset: dst GPU address
2544  * @num_gpu_pages: number of GPU pages to xfer
2545  * @fence: radeon fence object
2546  *
2547  * Copy GPU paging using the DMA engine (CIK).
2548  * Used by the radeon ttm implementation to move pages if
2549  * registered as the asic copy callback.
2550  */
2551 int cik_copy_dma(struct radeon_device *rdev,
2552                  uint64_t src_offset, uint64_t dst_offset,
2553                  unsigned num_gpu_pages,
2554                  struct radeon_fence **fence)
2555 {
2556         struct radeon_semaphore *sem = NULL;
2557         int ring_index = rdev->asic->copy.dma_ring_index;
2558         struct radeon_ring *ring = &rdev->ring[ring_index];
2559         u32 size_in_bytes, cur_size_in_bytes;
2560         int i, num_loops;
2561         int r = 0;
2562
2563         r = radeon_semaphore_create(rdev, &sem);
2564         if (r) {
2565                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2566                 return r;
2567         }
2568
2569         size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT);
2570         num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff);
2571         r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14);
2572         if (r) {
2573                 DRM_ERROR("radeon: moving bo (%d).\n", r);
2574                 radeon_semaphore_free(rdev, &sem, NULL);
2575                 return r;
2576         }
2577
2578         if (radeon_fence_need_sync(*fence, ring->idx)) {
2579                 radeon_semaphore_sync_rings(rdev, sem, (*fence)->ring,
2580                                             ring->idx);
2581                 radeon_fence_note_sync(*fence, ring->idx);
2582         } else {
2583                 radeon_semaphore_free(rdev, &sem, NULL);
2584         }
2585
2586         for (i = 0; i < num_loops; i++) {
2587                 cur_size_in_bytes = size_in_bytes;
2588                 if (cur_size_in_bytes > 0x1fffff)
2589                         cur_size_in_bytes = 0x1fffff;
2590                 size_in_bytes -= cur_size_in_bytes;
2591                 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));
2592                 radeon_ring_write(ring, cur_size_in_bytes);
2593                 radeon_ring_write(ring, 0); /* src/dst endian swap */
2594                 radeon_ring_write(ring, src_offset & 0xffffffff);
2595                 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xffffffff);
2596                 radeon_ring_write(ring, dst_offset & 0xfffffffc);
2597                 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xffffffff);
2598                 src_offset += cur_size_in_bytes;
2599                 dst_offset += cur_size_in_bytes;
2600         }
2601
2602         r = radeon_fence_emit(rdev, fence, ring->idx);
2603         if (r) {
2604                 radeon_ring_unlock_undo(rdev, ring);
2605                 return r;
2606         }
2607
2608         radeon_ring_unlock_commit(rdev, ring);
2609         radeon_semaphore_free(rdev, &sem, *fence);
2610
2611         return r;
2612 }
2613
2614 /**
2615  * cik_sdma_ring_test - simple async dma engine test
2616  *
2617  * @rdev: radeon_device pointer
2618  * @ring: radeon_ring structure holding ring information
2619  *
2620  * Test the DMA engine by writing using it to write an
2621  * value to memory. (CIK).
2622  * Returns 0 for success, error for failure.
2623  */
2624 int cik_sdma_ring_test(struct radeon_device *rdev,
2625                        struct radeon_ring *ring)
2626 {
2627         unsigned i;
2628         int r;
2629         void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
2630         u32 tmp;
2631
2632         if (!ptr) {
2633                 DRM_ERROR("invalid vram scratch pointer\n");
2634                 return -EINVAL;
2635         }
2636
2637         tmp = 0xCAFEDEAD;
2638         writel(tmp, ptr);
2639
2640         r = radeon_ring_lock(rdev, ring, 4);
2641         if (r) {
2642                 DRM_ERROR("radeon: dma failed to lock ring %d (%d).\n", ring->idx, r);
2643                 return r;
2644         }
2645         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
2646         radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
2647         radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff);
2648         radeon_ring_write(ring, 1); /* number of DWs to follow */
2649         radeon_ring_write(ring, 0xDEADBEEF);
2650         radeon_ring_unlock_commit(rdev, ring);
2651
2652         for (i = 0; i < rdev->usec_timeout; i++) {
2653                 tmp = readl(ptr);
2654                 if (tmp == 0xDEADBEEF)
2655                         break;
2656                 DRM_UDELAY(1);
2657         }
2658
2659         if (i < rdev->usec_timeout) {
2660                 DRM_INFO("ring test on %d succeeded in %d usecs\n", ring->idx, i);
2661         } else {
2662                 DRM_ERROR("radeon: ring %d test failed (0x%08X)\n",
2663                           ring->idx, tmp);
2664                 r = -EINVAL;
2665         }
2666         return r;
2667 }
2668
2669 /**
2670  * cik_sdma_ib_test - test an IB on the DMA engine
2671  *
2672  * @rdev: radeon_device pointer
2673  * @ring: radeon_ring structure holding ring information
2674  *
2675  * Test a simple IB in the DMA ring (CIK).
2676  * Returns 0 on success, error on failure.
2677  */
2678 int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
2679 {
2680         struct radeon_ib ib;
2681         unsigned i;
2682         int r;
2683         void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
2684         u32 tmp = 0;
2685
2686         if (!ptr) {
2687                 DRM_ERROR("invalid vram scratch pointer\n");
2688                 return -EINVAL;
2689         }
2690
2691         tmp = 0xCAFEDEAD;
2692         writel(tmp, ptr);
2693
2694         r = radeon_ib_get(rdev, ring->idx, &ib, NULL, 256);
2695         if (r) {
2696                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2697                 return r;
2698         }
2699
2700         ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
2701         ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
2702         ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff;
2703         ib.ptr[3] = 1;
2704         ib.ptr[4] = 0xDEADBEEF;
2705         ib.length_dw = 5;
2706
2707         r = radeon_ib_schedule(rdev, &ib, NULL);
2708         if (r) {
2709                 radeon_ib_free(rdev, &ib);
2710                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2711                 return r;
2712         }
2713         r = radeon_fence_wait(ib.fence, false);
2714         if (r) {
2715                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2716                 return r;
2717         }
2718         for (i = 0; i < rdev->usec_timeout; i++) {
2719                 tmp = readl(ptr);
2720                 if (tmp == 0xDEADBEEF)
2721                         break;
2722                 DRM_UDELAY(1);
2723         }
2724         if (i < rdev->usec_timeout) {
2725                 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib.fence->ring, i);
2726         } else {
2727                 DRM_ERROR("radeon: ib test failed (0x%08X)\n", tmp);
2728                 r = -EINVAL;
2729         }
2730         radeon_ib_free(rdev, &ib);
2731         return r;
2732 }
2733
2734 /**
2735  * cik_gpu_is_lockup - check if the 3D engine is locked up
2736  *
2737  * @rdev: radeon_device pointer
2738  * @ring: radeon_ring structure holding ring information
2739  *
2740  * Check if the 3D engine is locked up (CIK).
2741  * Returns true if the engine is locked, false if not.
2742  */
2743 bool cik_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2744 {
2745         u32 srbm_status, srbm_status2;
2746         u32 grbm_status, grbm_status2;
2747         u32 grbm_status_se0, grbm_status_se1, grbm_status_se2, grbm_status_se3;
2748
2749         srbm_status = RREG32(SRBM_STATUS);
2750         srbm_status2 = RREG32(SRBM_STATUS2);
2751         grbm_status = RREG32(GRBM_STATUS);
2752         grbm_status2 = RREG32(GRBM_STATUS2);
2753         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2754         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2755         grbm_status_se2 = RREG32(GRBM_STATUS_SE2);
2756         grbm_status_se3 = RREG32(GRBM_STATUS_SE3);
2757         if (!(grbm_status & GUI_ACTIVE)) {
2758                 radeon_ring_lockup_update(ring);
2759                 return false;
2760         }
2761         /* force CP activities */
2762         radeon_ring_force_activity(rdev, ring);
2763         return radeon_ring_test_lockup(rdev, ring);
2764 }
2765
2766 /**
2767  * cik_gfx_gpu_soft_reset - soft reset the 3D engine and CPG
2768  *
2769  * @rdev: radeon_device pointer
2770  *
2771  * Soft reset the GFX engine and CPG blocks (CIK).
2772  * XXX: deal with reseting RLC and CPF
2773  * Returns 0 for success.
2774  */
2775 static int cik_gfx_gpu_soft_reset(struct radeon_device *rdev)
2776 {
2777         struct evergreen_mc_save save;
2778         u32 grbm_reset = 0;
2779
2780         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2781                 return 0;
2782
2783         dev_info(rdev->dev, "GPU GFX softreset \n");
2784         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2785                 RREG32(GRBM_STATUS));
2786         dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
2787                 RREG32(GRBM_STATUS2));
2788         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2789                 RREG32(GRBM_STATUS_SE0));
2790         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2791                 RREG32(GRBM_STATUS_SE1));
2792         dev_info(rdev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
2793                 RREG32(GRBM_STATUS_SE2));
2794         dev_info(rdev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
2795                 RREG32(GRBM_STATUS_SE3));
2796         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2797                 RREG32(SRBM_STATUS));
2798         dev_info(rdev->dev, "  SRBM_STATUS2=0x%08X\n",
2799                 RREG32(SRBM_STATUS2));
2800         evergreen_mc_stop(rdev, &save);
2801         if (radeon_mc_wait_for_idle(rdev)) {
2802                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2803         }
2804         /* Disable CP parsing/prefetching */
2805         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
2806
2807         /* reset all the gfx block and all CPG blocks */
2808         grbm_reset = SOFT_RESET_CPG | SOFT_RESET_GFX;
2809
2810         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2811         WREG32(GRBM_SOFT_RESET, grbm_reset);
2812         (void)RREG32(GRBM_SOFT_RESET);
2813         udelay(50);
2814         WREG32(GRBM_SOFT_RESET, 0);
2815         (void)RREG32(GRBM_SOFT_RESET);
2816         /* Wait a little for things to settle down */
2817         udelay(50);
2818         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2819                 RREG32(GRBM_STATUS));
2820         dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
2821                 RREG32(GRBM_STATUS2));
2822         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2823                 RREG32(GRBM_STATUS_SE0));
2824         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2825                 RREG32(GRBM_STATUS_SE1));
2826         dev_info(rdev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
2827                 RREG32(GRBM_STATUS_SE2));
2828         dev_info(rdev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
2829                 RREG32(GRBM_STATUS_SE3));
2830         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2831                 RREG32(SRBM_STATUS));
2832         dev_info(rdev->dev, "  SRBM_STATUS2=0x%08X\n",
2833                 RREG32(SRBM_STATUS2));
2834         evergreen_mc_resume(rdev, &save);
2835         return 0;
2836 }
2837
2838 /**
2839  * cik_compute_gpu_soft_reset - soft reset CPC
2840  *
2841  * @rdev: radeon_device pointer
2842  *
2843  * Soft reset the CPC blocks (CIK).
2844  * XXX: deal with reseting RLC and CPF
2845  * Returns 0 for success.
2846  */
2847 static int cik_compute_gpu_soft_reset(struct radeon_device *rdev)
2848 {
2849         struct evergreen_mc_save save;
2850         u32 grbm_reset = 0;
2851
2852         dev_info(rdev->dev, "GPU compute softreset \n");
2853         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2854                 RREG32(GRBM_STATUS));
2855         dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
2856                 RREG32(GRBM_STATUS2));
2857         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2858                 RREG32(GRBM_STATUS_SE0));
2859         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2860                 RREG32(GRBM_STATUS_SE1));
2861         dev_info(rdev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
2862                 RREG32(GRBM_STATUS_SE2));
2863         dev_info(rdev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
2864                 RREG32(GRBM_STATUS_SE3));
2865         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2866                 RREG32(SRBM_STATUS));
2867         dev_info(rdev->dev, "  SRBM_STATUS2=0x%08X\n",
2868                 RREG32(SRBM_STATUS2));
2869         evergreen_mc_stop(rdev, &save);
2870         if (radeon_mc_wait_for_idle(rdev)) {
2871                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2872         }
2873         /* Disable CP parsing/prefetching */
2874         WREG32(CP_MEC_CNTL, MEC_ME1_HALT | MEC_ME2_HALT);
2875
2876         /* reset all the CPC blocks */
2877         grbm_reset = SOFT_RESET_CPG;
2878
2879         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2880         WREG32(GRBM_SOFT_RESET, grbm_reset);
2881         (void)RREG32(GRBM_SOFT_RESET);
2882         udelay(50);
2883         WREG32(GRBM_SOFT_RESET, 0);
2884         (void)RREG32(GRBM_SOFT_RESET);
2885         /* Wait a little for things to settle down */
2886         udelay(50);
2887         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2888                 RREG32(GRBM_STATUS));
2889         dev_info(rdev->dev, "  GRBM_STATUS2=0x%08X\n",
2890                 RREG32(GRBM_STATUS2));
2891         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2892                 RREG32(GRBM_STATUS_SE0));
2893         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2894                 RREG32(GRBM_STATUS_SE1));
2895         dev_info(rdev->dev, "  GRBM_STATUS_SE2=0x%08X\n",
2896                 RREG32(GRBM_STATUS_SE2));
2897         dev_info(rdev->dev, "  GRBM_STATUS_SE3=0x%08X\n",
2898                 RREG32(GRBM_STATUS_SE3));
2899         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2900                 RREG32(SRBM_STATUS));
2901         dev_info(rdev->dev, "  SRBM_STATUS2=0x%08X\n",
2902                 RREG32(SRBM_STATUS2));
2903         evergreen_mc_resume(rdev, &save);
2904         return 0;
2905 }
2906
2907 /**
2908  * cik_asic_reset - soft reset compute and gfx
2909  *
2910  * @rdev: radeon_device pointer
2911  *
2912  * Soft reset the CPC blocks (CIK).
2913  * XXX: make this more fine grained and only reset
2914  * what is necessary.
2915  * Returns 0 for success.
2916  */
2917 int cik_asic_reset(struct radeon_device *rdev)
2918 {
2919         int r;
2920
2921         r = cik_compute_gpu_soft_reset(rdev);
2922         if (r)
2923                 dev_info(rdev->dev, "Compute reset failed!\n");
2924
2925         return cik_gfx_gpu_soft_reset(rdev);
2926 }
2927
2928 /**
2929  * cik_sdma_is_lockup - Check if the DMA engine is locked up
2930  *
2931  * @rdev: radeon_device pointer
2932  * @ring: radeon_ring structure holding ring information
2933  *
2934  * Check if the async DMA engine is locked up (CIK).
2935  * Returns true if the engine appears to be locked up, false if not.
2936  */
2937 bool cik_sdma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2938 {
2939         u32 dma_status_reg;
2940
2941         if (ring->idx == R600_RING_TYPE_DMA_INDEX)
2942                 dma_status_reg = RREG32(SDMA0_STATUS_REG + SDMA0_REGISTER_OFFSET);
2943         else
2944                 dma_status_reg = RREG32(SDMA0_STATUS_REG + SDMA1_REGISTER_OFFSET);
2945         if (dma_status_reg & SDMA_IDLE) {
2946                 radeon_ring_lockup_update(ring);
2947                 return false;
2948         }
2949         /* force ring activities */
2950         radeon_ring_force_activity(rdev, ring);
2951         return radeon_ring_test_lockup(rdev, ring);
2952 }
2953
2954 /* MC */
2955 /**
2956  * cik_mc_program - program the GPU memory controller
2957  *
2958  * @rdev: radeon_device pointer
2959  *
2960  * Set the location of vram, gart, and AGP in the GPU's
2961  * physical address space (CIK).
2962  */
2963 static void cik_mc_program(struct radeon_device *rdev)
2964 {
2965         struct evergreen_mc_save save;
2966         u32 tmp;
2967         int i, j;
2968
2969         /* Initialize HDP */
2970         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
2971                 WREG32((0x2c14 + j), 0x00000000);
2972                 WREG32((0x2c18 + j), 0x00000000);
2973                 WREG32((0x2c1c + j), 0x00000000);
2974                 WREG32((0x2c20 + j), 0x00000000);
2975                 WREG32((0x2c24 + j), 0x00000000);
2976         }
2977         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
2978
2979         evergreen_mc_stop(rdev, &save);
2980         if (radeon_mc_wait_for_idle(rdev)) {
2981                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2982         }
2983         /* Lockout access through VGA aperture*/
2984         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
2985         /* Update configuration */
2986         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
2987                rdev->mc.vram_start >> 12);
2988         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
2989                rdev->mc.vram_end >> 12);
2990         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR,
2991                rdev->vram_scratch.gpu_addr >> 12);
2992         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
2993         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
2994         WREG32(MC_VM_FB_LOCATION, tmp);
2995         /* XXX double check these! */
2996         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
2997         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
2998         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
2999         WREG32(MC_VM_AGP_BASE, 0);
3000         WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
3001         WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
3002         if (radeon_mc_wait_for_idle(rdev)) {
3003                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
3004         }
3005         evergreen_mc_resume(rdev, &save);
3006         /* we need to own VRAM, so turn off the VGA renderer here
3007          * to stop it overwriting our objects */
3008         rv515_vga_render_disable(rdev);
3009 }
3010
3011 /**
3012  * cik_mc_init - initialize the memory controller driver params
3013  *
3014  * @rdev: radeon_device pointer
3015  *
3016  * Look up the amount of vram, vram width, and decide how to place
3017  * vram and gart within the GPU's physical address space (CIK).
3018  * Returns 0 for success.
3019  */
3020 static int cik_mc_init(struct radeon_device *rdev)
3021 {
3022         u32 tmp;
3023         int chansize, numchan;
3024
3025         /* Get VRAM informations */
3026         rdev->mc.vram_is_ddr = true;
3027         tmp = RREG32(MC_ARB_RAMCFG);
3028         if (tmp & CHANSIZE_MASK) {
3029                 chansize = 64;
3030         } else {
3031                 chansize = 32;
3032         }
3033         tmp = RREG32(MC_SHARED_CHMAP);
3034         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
3035         case 0:
3036         default:
3037                 numchan = 1;
3038                 break;
3039         case 1:
3040                 numchan = 2;
3041                 break;
3042         case 2:
3043                 numchan = 4;
3044                 break;
3045         case 3:
3046                 numchan = 8;
3047                 break;
3048         case 4:
3049                 numchan = 3;
3050                 break;
3051         case 5:
3052                 numchan = 6;
3053                 break;
3054         case 6:
3055                 numchan = 10;
3056                 break;
3057         case 7:
3058                 numchan = 12;
3059                 break;
3060         case 8:
3061                 numchan = 16;
3062                 break;
3063         }
3064         rdev->mc.vram_width = numchan * chansize;
3065         /* Could aper size report 0 ? */
3066         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
3067         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
3068         /* size in MB on si */
3069         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
3070         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
3071         rdev->mc.visible_vram_size = rdev->mc.aper_size;
3072         si_vram_gtt_location(rdev, &rdev->mc);
3073         radeon_update_bandwidth_info(rdev);
3074
3075         return 0;
3076 }
3077
3078 /*
3079  * GART
3080  * VMID 0 is the physical GPU addresses as used by the kernel.
3081  * VMIDs 1-15 are used for userspace clients and are handled
3082  * by the radeon vm/hsa code.
3083  */
3084 /**
3085  * cik_pcie_gart_tlb_flush - gart tlb flush callback
3086  *
3087  * @rdev: radeon_device pointer
3088  *
3089  * Flush the TLB for the VMID 0 page table (CIK).
3090  */
3091 void cik_pcie_gart_tlb_flush(struct radeon_device *rdev)
3092 {
3093         /* flush hdp cache */
3094         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0);
3095
3096         /* bits 0-15 are the VM contexts0-15 */
3097         WREG32(VM_INVALIDATE_REQUEST, 0x1);
3098 }
3099
3100 /**
3101  * cik_pcie_gart_enable - gart enable
3102  *
3103  * @rdev: radeon_device pointer
3104  *
3105  * This sets up the TLBs, programs the page tables for VMID0,
3106  * sets up the hw for VMIDs 1-15 which are allocated on
3107  * demand, and sets up the global locations for the LDS, GDS,
3108  * and GPUVM for FSA64 clients (CIK).
3109  * Returns 0 for success, errors for failure.
3110  */
3111 static int cik_pcie_gart_enable(struct radeon_device *rdev)
3112 {
3113         int r, i;
3114
3115         if (rdev->gart.robj == NULL) {
3116                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
3117                 return -EINVAL;
3118         }
3119         r = radeon_gart_table_vram_pin(rdev);
3120         if (r)
3121                 return r;
3122         radeon_gart_restore(rdev);
3123         /* Setup TLB control */
3124         WREG32(MC_VM_MX_L1_TLB_CNTL,
3125                (0xA << 7) |
3126                ENABLE_L1_TLB |
3127                SYSTEM_ACCESS_MODE_NOT_IN_SYS |
3128                ENABLE_ADVANCED_DRIVER_MODEL |
3129                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
3130         /* Setup L2 cache */
3131         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE |
3132                ENABLE_L2_FRAGMENT_PROCESSING |
3133                ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
3134                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
3135                EFFECTIVE_L2_QUEUE_SIZE(7) |
3136                CONTEXT1_IDENTITY_ACCESS_MODE(1));
3137         WREG32(VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS | INVALIDATE_L2_CACHE);
3138         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
3139                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
3140         /* setup context0 */
3141         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
3142         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
3143         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
3144         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
3145                         (u32)(rdev->dummy_page.addr >> 12));
3146         WREG32(VM_CONTEXT0_CNTL2, 0);
3147         WREG32(VM_CONTEXT0_CNTL, (ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
3148                                   RANGE_PROTECTION_FAULT_ENABLE_DEFAULT));
3149
3150         WREG32(0x15D4, 0);
3151         WREG32(0x15D8, 0);
3152         WREG32(0x15DC, 0);
3153
3154         /* empty context1-15 */
3155         /* FIXME start with 4G, once using 2 level pt switch to full
3156          * vm size space
3157          */
3158         /* set vm size, must be a multiple of 4 */
3159         WREG32(VM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
3160         WREG32(VM_CONTEXT1_PAGE_TABLE_END_ADDR, rdev->vm_manager.max_pfn);
3161         for (i = 1; i < 16; i++) {
3162                 if (i < 8)
3163                         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (i << 2),
3164                                rdev->gart.table_addr >> 12);
3165                 else
3166                         WREG32(VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((i - 8) << 2),
3167                                rdev->gart.table_addr >> 12);
3168         }
3169
3170         /* enable context1-15 */
3171         WREG32(VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR,
3172                (u32)(rdev->dummy_page.addr >> 12));
3173         WREG32(VM_CONTEXT1_CNTL2, 4);
3174         WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
3175                                 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
3176                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
3177                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
3178                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT |
3179                                 PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT |
3180                                 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT |
3181                                 VALID_PROTECTION_FAULT_ENABLE_INTERRUPT |
3182                                 VALID_PROTECTION_FAULT_ENABLE_DEFAULT |
3183                                 READ_PROTECTION_FAULT_ENABLE_INTERRUPT |
3184                                 READ_PROTECTION_FAULT_ENABLE_DEFAULT |
3185                                 WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT |
3186                                 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT);
3187
3188         /* TC cache setup ??? */
3189         WREG32(TC_CFG_L1_LOAD_POLICY0, 0);
3190         WREG32(TC_CFG_L1_LOAD_POLICY1, 0);
3191         WREG32(TC_CFG_L1_STORE_POLICY, 0);
3192
3193         WREG32(TC_CFG_L2_LOAD_POLICY0, 0);
3194         WREG32(TC_CFG_L2_LOAD_POLICY1, 0);
3195         WREG32(TC_CFG_L2_STORE_POLICY0, 0);
3196         WREG32(TC_CFG_L2_STORE_POLICY1, 0);
3197         WREG32(TC_CFG_L2_ATOMIC_POLICY, 0);
3198
3199         WREG32(TC_CFG_L1_VOLATILE, 0);
3200         WREG32(TC_CFG_L2_VOLATILE, 0);
3201
3202         if (rdev->family == CHIP_KAVERI) {
3203                 u32 tmp = RREG32(CHUB_CONTROL);
3204                 tmp &= ~BYPASS_VM;
3205                 WREG32(CHUB_CONTROL, tmp);
3206         }
3207
3208         /* XXX SH_MEM regs */
3209         /* where to put LDS, scratch, GPUVM in FSA64 space */
3210         for (i = 0; i < 16; i++) {
3211                 WREG32(SRBM_GFX_CNTL, VMID(i));
3212                 /* CP and shaders */
3213                 WREG32(SH_MEM_CONFIG, 0);
3214                 WREG32(SH_MEM_APE1_BASE, 1);
3215                 WREG32(SH_MEM_APE1_LIMIT, 0);
3216                 WREG32(SH_MEM_BASES, 0);
3217                 /* SDMA GFX */
3218                 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA0_REGISTER_OFFSET, 0);
3219                 WREG32(SDMA0_GFX_APE1_CNTL + SDMA0_REGISTER_OFFSET, 0);
3220                 WREG32(SDMA0_GFX_VIRTUAL_ADDR + SDMA1_REGISTER_OFFSET, 0);
3221                 WREG32(SDMA0_GFX_APE1_CNTL + SDMA1_REGISTER_OFFSET, 0);
3222                 /* XXX SDMA RLC - todo */
3223         }
3224         WREG32(SRBM_GFX_CNTL, 0);
3225
3226         cik_pcie_gart_tlb_flush(rdev);
3227         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
3228                  (unsigned)(rdev->mc.gtt_size >> 20),
3229                  (unsigned long long)rdev->gart.table_addr);
3230         rdev->gart.ready = true;
3231         return 0;
3232 }
3233
3234 /**
3235  * cik_pcie_gart_disable - gart disable
3236  *
3237  * @rdev: radeon_device pointer
3238  *
3239  * This disables all VM page table (CIK).
3240  */
3241 static void cik_pcie_gart_disable(struct radeon_device *rdev)
3242 {
3243         /* Disable all tables */
3244         WREG32(VM_CONTEXT0_CNTL, 0);
3245         WREG32(VM_CONTEXT1_CNTL, 0);
3246         /* Setup TLB control */
3247         WREG32(MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE_NOT_IN_SYS |
3248                SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU);
3249         /* Setup L2 cache */
3250         WREG32(VM_L2_CNTL,
3251                ENABLE_L2_FRAGMENT_PROCESSING |
3252                ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
3253                ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE |
3254                EFFECTIVE_L2_QUEUE_SIZE(7) |
3255                CONTEXT1_IDENTITY_ACCESS_MODE(1));
3256         WREG32(VM_L2_CNTL2, 0);
3257         WREG32(VM_L2_CNTL3, L2_CACHE_BIGK_ASSOCIATIVITY |
3258                L2_CACHE_BIGK_FRAGMENT_SIZE(6));
3259         radeon_gart_table_vram_unpin(rdev);
3260 }
3261
3262 /**
3263  * cik_pcie_gart_fini - vm fini callback
3264  *
3265  * @rdev: radeon_device pointer
3266  *
3267  * Tears down the driver GART/VM setup (CIK).
3268  */
3269 static void cik_pcie_gart_fini(struct radeon_device *rdev)
3270 {
3271         cik_pcie_gart_disable(rdev);
3272         radeon_gart_table_vram_free(rdev);
3273         radeon_gart_fini(rdev);
3274 }
3275
3276 /* vm parser */
3277 /**
3278  * cik_ib_parse - vm ib_parse callback
3279  *
3280  * @rdev: radeon_device pointer
3281  * @ib: indirect buffer pointer
3282  *
3283  * CIK uses hw IB checking so this is a nop (CIK).
3284  */
3285 int cik_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
3286 {
3287         return 0;
3288 }
3289
3290 /*
3291  * vm
3292  * VMID 0 is the physical GPU addresses as used by the kernel.
3293  * VMIDs 1-15 are used for userspace clients and are handled
3294  * by the radeon vm/hsa code.
3295  */
3296 /**
3297  * cik_vm_init - cik vm init callback
3298  *
3299  * @rdev: radeon_device pointer
3300  *
3301  * Inits cik specific vm parameters (number of VMs, base of vram for
3302  * VMIDs 1-15) (CIK).
3303  * Returns 0 for success.
3304  */
3305 int cik_vm_init(struct radeon_device *rdev)
3306 {
3307         /* number of VMs */
3308         rdev->vm_manager.nvm = 16;
3309         /* base offset of vram pages */
3310         if (rdev->flags & RADEON_IS_IGP) {
3311                 u64 tmp = RREG32(MC_VM_FB_OFFSET);
3312                 tmp <<= 22;
3313                 rdev->vm_manager.vram_base_offset = tmp;
3314         } else
3315                 rdev->vm_manager.vram_base_offset = 0;
3316
3317         return 0;
3318 }
3319
3320 /**
3321  * cik_vm_fini - cik vm fini callback
3322  *
3323  * @rdev: radeon_device pointer
3324  *
3325  * Tear down any asic specific VM setup (CIK).
3326  */
3327 void cik_vm_fini(struct radeon_device *rdev)
3328 {
3329 }
3330
3331 /**
3332  * cik_vm_flush - cik vm flush using the CP
3333  *
3334  * @rdev: radeon_device pointer
3335  *
3336  * Update the page table base and flush the VM TLB
3337  * using the CP (CIK).
3338  */
3339 void cik_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm)
3340 {
3341         struct radeon_ring *ring = &rdev->ring[ridx];
3342
3343         if (vm == NULL)
3344                 return;
3345
3346         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3347         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3348                                  WRITE_DATA_DST_SEL(0)));
3349         if (vm->id < 8) {
3350                 radeon_ring_write(ring,
3351                                   (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2);
3352         } else {
3353                 radeon_ring_write(ring,
3354                                   (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2);
3355         }
3356         radeon_ring_write(ring, 0);
3357         radeon_ring_write(ring, vm->pd_gpu_addr >> 12);
3358
3359         /* update SH_MEM_* regs */
3360         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3361         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3362                                  WRITE_DATA_DST_SEL(0)));
3363         radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
3364         radeon_ring_write(ring, 0);
3365         radeon_ring_write(ring, VMID(vm->id));
3366
3367         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 6));
3368         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3369                                  WRITE_DATA_DST_SEL(0)));
3370         radeon_ring_write(ring, SH_MEM_BASES >> 2);
3371         radeon_ring_write(ring, 0);
3372
3373         radeon_ring_write(ring, 0); /* SH_MEM_BASES */
3374         radeon_ring_write(ring, 0); /* SH_MEM_CONFIG */
3375         radeon_ring_write(ring, 1); /* SH_MEM_APE1_BASE */
3376         radeon_ring_write(ring, 0); /* SH_MEM_APE1_LIMIT */
3377
3378         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3379         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3380                                  WRITE_DATA_DST_SEL(0)));
3381         radeon_ring_write(ring, SRBM_GFX_CNTL >> 2);
3382         radeon_ring_write(ring, 0);
3383         radeon_ring_write(ring, VMID(0));
3384
3385         /* HDP flush */
3386         /* We should be using the WAIT_REG_MEM packet here like in
3387          * cik_fence_ring_emit(), but it causes the CP to hang in this
3388          * context...
3389          */
3390         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3391         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3392                                  WRITE_DATA_DST_SEL(0)));
3393         radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
3394         radeon_ring_write(ring, 0);
3395         radeon_ring_write(ring, 0);
3396
3397         /* bits 0-15 are the VM contexts0-15 */
3398         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3399         radeon_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
3400                                  WRITE_DATA_DST_SEL(0)));
3401         radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2);
3402         radeon_ring_write(ring, 0);
3403         radeon_ring_write(ring, 1 << vm->id);
3404
3405         /* sync PFP to ME, otherwise we might get invalid PFP reads */
3406         radeon_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
3407         radeon_ring_write(ring, 0x0);
3408 }
3409
3410 /*
3411  * RLC
3412  * The RLC is a multi-purpose microengine that handles a
3413  * variety of functions, the most important of which is
3414  * the interrupt controller.
3415  */
3416 /**
3417  * cik_rlc_stop - stop the RLC ME
3418  *
3419  * @rdev: radeon_device pointer
3420  *
3421  * Halt the RLC ME (MicroEngine) (CIK).
3422  */
3423 static void cik_rlc_stop(struct radeon_device *rdev)
3424 {
3425         int i, j, k;
3426         u32 mask, tmp;
3427
3428         tmp = RREG32(CP_INT_CNTL_RING0);
3429         tmp &= ~(CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3430         WREG32(CP_INT_CNTL_RING0, tmp);
3431
3432         RREG32(CB_CGTT_SCLK_CTRL);
3433         RREG32(CB_CGTT_SCLK_CTRL);
3434         RREG32(CB_CGTT_SCLK_CTRL);
3435         RREG32(CB_CGTT_SCLK_CTRL);
3436
3437         tmp = RREG32(RLC_CGCG_CGLS_CTRL) & 0xfffffffc;
3438         WREG32(RLC_CGCG_CGLS_CTRL, tmp);
3439
3440         WREG32(RLC_CNTL, 0);
3441
3442         for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
3443                 for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
3444                         cik_select_se_sh(rdev, i, j);
3445                         for (k = 0; k < rdev->usec_timeout; k++) {
3446                                 if (RREG32(RLC_SERDES_CU_MASTER_BUSY) == 0)
3447                                         break;
3448                                 udelay(1);
3449                         }
3450                 }
3451         }
3452         cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3453
3454         mask = SE_MASTER_BUSY_MASK | GC_MASTER_BUSY | TC0_MASTER_BUSY | TC1_MASTER_BUSY;
3455         for (k = 0; k < rdev->usec_timeout; k++) {
3456                 if ((RREG32(RLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
3457                         break;
3458                 udelay(1);
3459         }
3460 }
3461
3462 /**
3463  * cik_rlc_start - start the RLC ME
3464  *
3465  * @rdev: radeon_device pointer
3466  *
3467  * Unhalt the RLC ME (MicroEngine) (CIK).
3468  */
3469 static void cik_rlc_start(struct radeon_device *rdev)
3470 {
3471         u32 tmp;
3472
3473         WREG32(RLC_CNTL, RLC_ENABLE);
3474
3475         tmp = RREG32(CP_INT_CNTL_RING0);
3476         tmp |= (CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3477         WREG32(CP_INT_CNTL_RING0, tmp);
3478
3479         udelay(50);
3480 }
3481
3482 /**
3483  * cik_rlc_resume - setup the RLC hw
3484  *
3485  * @rdev: radeon_device pointer
3486  *
3487  * Initialize the RLC registers, load the ucode,
3488  * and start the RLC (CIK).
3489  * Returns 0 for success, -EINVAL if the ucode is not available.
3490  */
3491 static int cik_rlc_resume(struct radeon_device *rdev)
3492 {
3493         u32 i, size;
3494         u32 clear_state_info[3];
3495         const __be32 *fw_data;
3496
3497         if (!rdev->rlc_fw)
3498                 return -EINVAL;
3499
3500         switch (rdev->family) {
3501         case CHIP_BONAIRE:
3502         default:
3503                 size = BONAIRE_RLC_UCODE_SIZE;
3504                 break;
3505         case CHIP_KAVERI:
3506                 size = KV_RLC_UCODE_SIZE;
3507                 break;
3508         case CHIP_KABINI:
3509                 size = KB_RLC_UCODE_SIZE;
3510                 break;
3511         }
3512
3513         cik_rlc_stop(rdev);
3514
3515         WREG32(GRBM_SOFT_RESET, SOFT_RESET_RLC);
3516         RREG32(GRBM_SOFT_RESET);
3517         udelay(50);
3518         WREG32(GRBM_SOFT_RESET, 0);
3519         RREG32(GRBM_SOFT_RESET);
3520         udelay(50);
3521
3522         WREG32(RLC_LB_CNTR_INIT, 0);
3523         WREG32(RLC_LB_CNTR_MAX, 0x00008000);
3524
3525         cik_select_se_sh(rdev, 0xffffffff, 0xffffffff);
3526         WREG32(RLC_LB_INIT_CU_MASK, 0xffffffff);
3527         WREG32(RLC_LB_PARAMS, 0x00600408);
3528         WREG32(RLC_LB_CNTL, 0x80000004);
3529
3530         WREG32(RLC_MC_CNTL, 0);
3531         WREG32(RLC_UCODE_CNTL, 0);
3532
3533         fw_data = (const __be32 *)rdev->rlc_fw->data;
3534                 WREG32(RLC_GPM_UCODE_ADDR, 0);
3535         for (i = 0; i < size; i++)
3536                 WREG32(RLC_GPM_UCODE_DATA, be32_to_cpup(fw_data++));
3537         WREG32(RLC_GPM_UCODE_ADDR, 0);
3538
3539         /* XXX */
3540         clear_state_info[0] = 0;//upper_32_bits(rdev->rlc.save_restore_gpu_addr);
3541         clear_state_info[1] = 0;//rdev->rlc.save_restore_gpu_addr;
3542         clear_state_info[2] = 0;//cik_default_size;
3543         WREG32(RLC_GPM_SCRATCH_ADDR, 0x3d);
3544         for (i = 0; i < 3; i++)
3545                 WREG32(RLC_GPM_SCRATCH_DATA, clear_state_info[i]);
3546         WREG32(RLC_DRIVER_DMA_STATUS, 0);
3547
3548         cik_rlc_start(rdev);
3549
3550         return 0;
3551 }
3552
3553 /*
3554  * Interrupts
3555  * Starting with r6xx, interrupts are handled via a ring buffer.
3556  * Ring buffers are areas of GPU accessible memory that the GPU
3557  * writes interrupt vectors into and the host reads vectors out of.
3558  * There is a rptr (read pointer) that determines where the
3559  * host is currently reading, and a wptr (write pointer)
3560  * which determines where the GPU has written.  When the
3561  * pointers are equal, the ring is idle.  When the GPU
3562  * writes vectors to the ring buffer, it increments the
3563  * wptr.  When there is an interrupt, the host then starts
3564  * fetching commands and processing them until the pointers are
3565  * equal again at which point it updates the rptr.
3566  */
3567
3568 /**
3569  * cik_enable_interrupts - Enable the interrupt ring buffer
3570  *
3571  * @rdev: radeon_device pointer
3572  *
3573  * Enable the interrupt ring buffer (CIK).
3574  */
3575 static void cik_enable_interrupts(struct radeon_device *rdev)
3576 {
3577         u32 ih_cntl = RREG32(IH_CNTL);
3578         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3579
3580         ih_cntl |= ENABLE_INTR;
3581         ih_rb_cntl |= IH_RB_ENABLE;
3582         WREG32(IH_CNTL, ih_cntl);
3583         WREG32(IH_RB_CNTL, ih_rb_cntl);
3584         rdev->ih.enabled = true;
3585 }
3586
3587 /**
3588  * cik_disable_interrupts - Disable the interrupt ring buffer
3589  *
3590  * @rdev: radeon_device pointer
3591  *
3592  * Disable the interrupt ring buffer (CIK).
3593  */
3594 static void cik_disable_interrupts(struct radeon_device *rdev)
3595 {
3596         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
3597         u32 ih_cntl = RREG32(IH_CNTL);
3598
3599         ih_rb_cntl &= ~IH_RB_ENABLE;
3600         ih_cntl &= ~ENABLE_INTR;
3601         WREG32(IH_RB_CNTL, ih_rb_cntl);
3602         WREG32(IH_CNTL, ih_cntl);
3603         /* set rptr, wptr to 0 */
3604         WREG32(IH_RB_RPTR, 0);
3605         WREG32(IH_RB_WPTR, 0);
3606         rdev->ih.enabled = false;
3607         rdev->ih.rptr = 0;
3608 }
3609
3610 /**
3611  * cik_disable_interrupt_state - Disable all interrupt sources
3612  *
3613  * @rdev: radeon_device pointer
3614  *
3615  * Clear all interrupt enable bits used by the driver (CIK).
3616  */
3617 static void cik_disable_interrupt_state(struct radeon_device *rdev)
3618 {
3619         u32 tmp;
3620
3621         /* gfx ring */
3622         WREG32(CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
3623         /* sdma */
3624         tmp = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3625         WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, tmp);
3626         tmp = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3627         WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, tmp);
3628         /* compute queues */
3629         WREG32(CP_ME1_PIPE0_INT_CNTL, 0);
3630         WREG32(CP_ME1_PIPE1_INT_CNTL, 0);
3631         WREG32(CP_ME1_PIPE2_INT_CNTL, 0);
3632         WREG32(CP_ME1_PIPE3_INT_CNTL, 0);
3633         WREG32(CP_ME2_PIPE0_INT_CNTL, 0);
3634         WREG32(CP_ME2_PIPE1_INT_CNTL, 0);
3635         WREG32(CP_ME2_PIPE2_INT_CNTL, 0);
3636         WREG32(CP_ME2_PIPE3_INT_CNTL, 0);
3637         /* grbm */
3638         WREG32(GRBM_INT_CNTL, 0);
3639         /* vline/vblank, etc. */
3640         WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
3641         WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
3642         if (rdev->num_crtc >= 4) {
3643                 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
3644                 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
3645         }
3646         if (rdev->num_crtc >= 6) {
3647                 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
3648                 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
3649         }
3650
3651         /* dac hotplug */
3652         WREG32(DAC_AUTODETECT_INT_CONTROL, 0);
3653
3654         /* digital hotplug */
3655         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3656         WREG32(DC_HPD1_INT_CONTROL, tmp);
3657         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3658         WREG32(DC_HPD2_INT_CONTROL, tmp);
3659         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3660         WREG32(DC_HPD3_INT_CONTROL, tmp);
3661         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3662         WREG32(DC_HPD4_INT_CONTROL, tmp);
3663         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3664         WREG32(DC_HPD5_INT_CONTROL, tmp);
3665         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
3666         WREG32(DC_HPD6_INT_CONTROL, tmp);
3667
3668 }
3669
3670 /**
3671  * cik_irq_init - init and enable the interrupt ring
3672  *
3673  * @rdev: radeon_device pointer
3674  *
3675  * Allocate a ring buffer for the interrupt controller,
3676  * enable the RLC, disable interrupts, enable the IH
3677  * ring buffer and enable it (CIK).
3678  * Called at device load and reume.
3679  * Returns 0 for success, errors for failure.
3680  */
3681 static int cik_irq_init(struct radeon_device *rdev)
3682 {
3683         int ret = 0;
3684         int rb_bufsz;
3685         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
3686
3687         /* allocate ring */
3688         ret = r600_ih_ring_alloc(rdev);
3689         if (ret)
3690                 return ret;
3691
3692         /* disable irqs */
3693         cik_disable_interrupts(rdev);
3694
3695         /* init rlc */
3696         ret = cik_rlc_resume(rdev);
3697         if (ret) {
3698                 r600_ih_ring_fini(rdev);
3699                 return ret;
3700         }
3701
3702         /* setup interrupt control */
3703         /* XXX this should actually be a bus address, not an MC address. same on older asics */
3704         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
3705         interrupt_cntl = RREG32(INTERRUPT_CNTL);
3706         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
3707          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
3708          */
3709         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
3710         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
3711         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
3712         WREG32(INTERRUPT_CNTL, interrupt_cntl);
3713
3714         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
3715         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
3716
3717         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
3718                       IH_WPTR_OVERFLOW_CLEAR |
3719                       (rb_bufsz << 1));
3720
3721         if (rdev->wb.enabled)
3722                 ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
3723
3724         /* set the writeback address whether it's enabled or not */
3725         WREG32(IH_RB_WPTR_ADDR_LO, (rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFFFFFFFC);
3726         WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + R600_WB_IH_WPTR_OFFSET) & 0xFF);
3727
3728         WREG32(IH_RB_CNTL, ih_rb_cntl);
3729
3730         /* set rptr, wptr to 0 */
3731         WREG32(IH_RB_RPTR, 0);
3732         WREG32(IH_RB_WPTR, 0);
3733
3734         /* Default settings for IH_CNTL (disabled at first) */
3735         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10) | MC_VMID(0);
3736         /* RPTR_REARM only works if msi's are enabled */
3737         if (rdev->msi_enabled)
3738                 ih_cntl |= RPTR_REARM;
3739         WREG32(IH_CNTL, ih_cntl);
3740
3741         /* force the active interrupt state to all disabled */
3742         cik_disable_interrupt_state(rdev);
3743
3744         pci_set_master(rdev->pdev);
3745
3746         /* enable irqs */
3747         cik_enable_interrupts(rdev);
3748
3749         return ret;
3750 }
3751
3752 /**
3753  * cik_irq_set - enable/disable interrupt sources
3754  *
3755  * @rdev: radeon_device pointer
3756  *
3757  * Enable interrupt sources on the GPU (vblanks, hpd,
3758  * etc.) (CIK).
3759  * Returns 0 for success, errors for failure.
3760  */
3761 int cik_irq_set(struct radeon_device *rdev)
3762 {
3763         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE |
3764                 PRIV_INSTR_INT_ENABLE | PRIV_REG_INT_ENABLE;
3765         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
3766         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
3767         u32 grbm_int_cntl = 0;
3768         u32 dma_cntl, dma_cntl1;
3769
3770         if (!rdev->irq.installed) {
3771                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
3772                 return -EINVAL;
3773         }
3774         /* don't enable anything if the ih is disabled */
3775         if (!rdev->ih.enabled) {
3776                 cik_disable_interrupts(rdev);
3777                 /* force the active interrupt state to all disabled */
3778                 cik_disable_interrupt_state(rdev);
3779                 return 0;
3780         }
3781
3782         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3783         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3784         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3785         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3786         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3787         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3788
3789         dma_cntl = RREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET) & ~TRAP_ENABLE;
3790         dma_cntl1 = RREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
3791
3792         /* enable CP interrupts on all rings */
3793         if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
3794                 DRM_DEBUG("cik_irq_set: sw int gfx\n");
3795                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
3796         }
3797         /* TODO: compute queues! */
3798         /* CP_ME[1-2]_PIPE[0-3]_INT_CNTL */
3799
3800         if (atomic_read(&rdev->irq.ring_int[R600_RING_TYPE_DMA_INDEX])) {
3801                 DRM_DEBUG("cik_irq_set: sw int dma\n");
3802                 dma_cntl |= TRAP_ENABLE;
3803         }
3804
3805         if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_DMA1_INDEX])) {
3806                 DRM_DEBUG("cik_irq_set: sw int dma1\n");
3807                 dma_cntl1 |= TRAP_ENABLE;
3808         }
3809
3810         if (rdev->irq.crtc_vblank_int[0] ||
3811             atomic_read(&rdev->irq.pflip[0])) {
3812                 DRM_DEBUG("cik_irq_set: vblank 0\n");
3813                 crtc1 |= VBLANK_INTERRUPT_MASK;
3814         }
3815         if (rdev->irq.crtc_vblank_int[1] ||
3816             atomic_read(&rdev->irq.pflip[1])) {
3817                 DRM_DEBUG("cik_irq_set: vblank 1\n");
3818                 crtc2 |= VBLANK_INTERRUPT_MASK;
3819         }
3820         if (rdev->irq.crtc_vblank_int[2] ||
3821             atomic_read(&rdev->irq.pflip[2])) {
3822                 DRM_DEBUG("cik_irq_set: vblank 2\n");
3823                 crtc3 |= VBLANK_INTERRUPT_MASK;
3824         }
3825         if (rdev->irq.crtc_vblank_int[3] ||
3826             atomic_read(&rdev->irq.pflip[3])) {
3827                 DRM_DEBUG("cik_irq_set: vblank 3\n");
3828                 crtc4 |= VBLANK_INTERRUPT_MASK;
3829         }
3830         if (rdev->irq.crtc_vblank_int[4] ||
3831             atomic_read(&rdev->irq.pflip[4])) {
3832                 DRM_DEBUG("cik_irq_set: vblank 4\n");
3833                 crtc5 |= VBLANK_INTERRUPT_MASK;
3834         }
3835         if (rdev->irq.crtc_vblank_int[5] ||
3836             atomic_read(&rdev->irq.pflip[5])) {
3837                 DRM_DEBUG("cik_irq_set: vblank 5\n");
3838                 crtc6 |= VBLANK_INTERRUPT_MASK;
3839         }
3840         if (rdev->irq.hpd[0]) {
3841                 DRM_DEBUG("cik_irq_set: hpd 1\n");
3842                 hpd1 |= DC_HPDx_INT_EN;
3843         }
3844         if (rdev->irq.hpd[1]) {
3845                 DRM_DEBUG("cik_irq_set: hpd 2\n");
3846                 hpd2 |= DC_HPDx_INT_EN;
3847         }
3848         if (rdev->irq.hpd[2]) {
3849                 DRM_DEBUG("cik_irq_set: hpd 3\n");
3850                 hpd3 |= DC_HPDx_INT_EN;
3851         }
3852         if (rdev->irq.hpd[3]) {
3853                 DRM_DEBUG("cik_irq_set: hpd 4\n");
3854                 hpd4 |= DC_HPDx_INT_EN;
3855         }
3856         if (rdev->irq.hpd[4]) {
3857                 DRM_DEBUG("cik_irq_set: hpd 5\n");
3858                 hpd5 |= DC_HPDx_INT_EN;
3859         }
3860         if (rdev->irq.hpd[5]) {
3861                 DRM_DEBUG("cik_irq_set: hpd 6\n");
3862                 hpd6 |= DC_HPDx_INT_EN;
3863         }
3864
3865         WREG32(CP_INT_CNTL_RING0, cp_int_cntl);
3866
3867         WREG32(SDMA0_CNTL + SDMA0_REGISTER_OFFSET, dma_cntl);
3868         WREG32(SDMA0_CNTL + SDMA1_REGISTER_OFFSET, dma_cntl1);
3869
3870         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3871
3872         WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
3873         WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
3874         if (rdev->num_crtc >= 4) {
3875                 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
3876                 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
3877         }
3878         if (rdev->num_crtc >= 6) {
3879                 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
3880                 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
3881         }
3882
3883         WREG32(DC_HPD1_INT_CONTROL, hpd1);
3884         WREG32(DC_HPD2_INT_CONTROL, hpd2);
3885         WREG32(DC_HPD3_INT_CONTROL, hpd3);
3886         WREG32(DC_HPD4_INT_CONTROL, hpd4);
3887         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3888         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3889
3890         return 0;
3891 }
3892
3893 /**
3894  * cik_irq_ack - ack interrupt sources
3895  *
3896  * @rdev: radeon_device pointer
3897  *
3898  * Ack interrupt sources on the GPU (vblanks, hpd,
3899  * etc.) (CIK).  Certain interrupts sources are sw
3900  * generated and do not require an explicit ack.
3901  */
3902 static inline void cik_irq_ack(struct radeon_device *rdev)
3903 {
3904         u32 tmp;
3905
3906         rdev->irq.stat_regs.cik.disp_int = RREG32(DISP_INTERRUPT_STATUS);
3907         rdev->irq.stat_regs.cik.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3908         rdev->irq.stat_regs.cik.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
3909         rdev->irq.stat_regs.cik.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
3910         rdev->irq.stat_regs.cik.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
3911         rdev->irq.stat_regs.cik.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
3912         rdev->irq.stat_regs.cik.disp_int_cont6 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE6);
3913
3914         if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT)
3915                 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
3916         if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT)
3917                 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
3918         if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
3919                 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
3920         if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT)
3921                 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
3922
3923         if (rdev->num_crtc >= 4) {
3924                 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
3925                         WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
3926                 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
3927                         WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
3928                 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
3929                         WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
3930                 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
3931                         WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
3932         }
3933
3934         if (rdev->num_crtc >= 6) {
3935                 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
3936                         WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
3937                 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
3938                         WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
3939                 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
3940                         WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
3941                 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
3942                         WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
3943         }
3944
3945         if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) {
3946                 tmp = RREG32(DC_HPD1_INT_CONTROL);
3947                 tmp |= DC_HPDx_INT_ACK;
3948                 WREG32(DC_HPD1_INT_CONTROL, tmp);
3949         }
3950         if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT) {
3951                 tmp = RREG32(DC_HPD2_INT_CONTROL);
3952                 tmp |= DC_HPDx_INT_ACK;
3953                 WREG32(DC_HPD2_INT_CONTROL, tmp);
3954         }
3955         if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3956                 tmp = RREG32(DC_HPD3_INT_CONTROL);
3957                 tmp |= DC_HPDx_INT_ACK;
3958                 WREG32(DC_HPD3_INT_CONTROL, tmp);
3959         }
3960         if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3961                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3962                 tmp |= DC_HPDx_INT_ACK;
3963                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3964         }
3965         if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3966                 tmp = RREG32(DC_HPD5_INT_CONTROL);
3967                 tmp |= DC_HPDx_INT_ACK;
3968                 WREG32(DC_HPD5_INT_CONTROL, tmp);
3969         }
3970         if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3971                 tmp = RREG32(DC_HPD5_INT_CONTROL);
3972                 tmp |= DC_HPDx_INT_ACK;
3973                 WREG32(DC_HPD6_INT_CONTROL, tmp);
3974         }
3975 }
3976
3977 /**
3978  * cik_irq_disable - disable interrupts
3979  *
3980  * @rdev: radeon_device pointer
3981  *
3982  * Disable interrupts on the hw (CIK).
3983  */
3984 static void cik_irq_disable(struct radeon_device *rdev)
3985 {
3986         cik_disable_interrupts(rdev);
3987         /* Wait and acknowledge irq */
3988         mdelay(1);
3989         cik_irq_ack(rdev);
3990         cik_disable_interrupt_state(rdev);
3991 }
3992
3993 /**
3994  * cik_irq_disable - disable interrupts for suspend
3995  *
3996  * @rdev: radeon_device pointer
3997  *
3998  * Disable interrupts and stop the RLC (CIK).
3999  * Used for suspend.
4000  */
4001 static void cik_irq_suspend(struct radeon_device *rdev)
4002 {
4003         cik_irq_disable(rdev);
4004         cik_rlc_stop(rdev);
4005 }
4006
4007 /**
4008  * cik_irq_fini - tear down interrupt support
4009  *
4010  * @rdev: radeon_device pointer
4011  *
4012  * Disable interrupts on the hw and free the IH ring
4013  * buffer (CIK).
4014  * Used for driver unload.
4015  */
4016 static void cik_irq_fini(struct radeon_device *rdev)
4017 {
4018         cik_irq_suspend(rdev);
4019         r600_ih_ring_fini(rdev);
4020 }
4021
4022 /**
4023  * cik_get_ih_wptr - get the IH ring buffer wptr
4024  *
4025  * @rdev: radeon_device pointer
4026  *
4027  * Get the IH ring buffer wptr from either the register
4028  * or the writeback memory buffer (CIK).  Also check for
4029  * ring buffer overflow and deal with it.
4030  * Used by cik_irq_process().
4031  * Returns the value of the wptr.
4032  */
4033 static inline u32 cik_get_ih_wptr(struct radeon_device *rdev)
4034 {
4035         u32 wptr, tmp;
4036
4037         if (rdev->wb.enabled)
4038                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
4039         else
4040                 wptr = RREG32(IH_RB_WPTR);
4041
4042         if (wptr & RB_OVERFLOW) {
4043                 /* When a ring buffer overflow happen start parsing interrupt
4044                  * from the last not overwritten vector (wptr + 16). Hopefully
4045                  * this should allow us to catchup.
4046                  */
4047                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
4048                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
4049                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
4050                 tmp = RREG32(IH_RB_CNTL);
4051                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
4052                 WREG32(IH_RB_CNTL, tmp);
4053         }
4054         return (wptr & rdev->ih.ptr_mask);
4055 }
4056
4057 /*        CIK IV Ring
4058  * Each IV ring entry is 128 bits:
4059  * [7:0]    - interrupt source id
4060  * [31:8]   - reserved
4061  * [59:32]  - interrupt source data
4062  * [63:60]  - reserved
4063  * [71:64]  - RINGID
4064  *            CP:
4065  *            ME_ID [1:0], PIPE_ID[1:0], QUEUE_ID[2:0]
4066  *            QUEUE_ID - for compute, which of the 8 queues owned by the dispatcher
4067  *                     - for gfx, hw shader state (0=PS...5=LS, 6=CS)
4068  *            ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
4069  *            PIPE_ID - ME0 0=3D
4070  *                    - ME1&2 compute dispatcher (4 pipes each)
4071  *            SDMA:
4072  *            INSTANCE_ID [1:0], QUEUE_ID[1:0]
4073  *            INSTANCE_ID - 0 = sdma0, 1 = sdma1
4074  *            QUEUE_ID - 0 = gfx, 1 = rlc0, 2 = rlc1
4075  * [79:72]  - VMID
4076  * [95:80]  - PASID
4077  * [127:96] - reserved
4078  */
4079 /**
4080  * cik_irq_process - interrupt handler
4081  *
4082  * @rdev: radeon_device pointer
4083  *
4084  * Interrupt hander (CIK).  Walk the IH ring,
4085  * ack interrupts and schedule work to handle
4086  * interrupt events.
4087  * Returns irq process return code.
4088  */
4089 int cik_irq_process(struct radeon_device *rdev)
4090 {
4091         u32 wptr;
4092         u32 rptr;
4093         u32 src_id, src_data, ring_id;
4094         u8 me_id, pipe_id, queue_id;
4095         u32 ring_index;
4096         bool queue_hotplug = false;
4097         bool queue_reset = false;
4098
4099         if (!rdev->ih.enabled || rdev->shutdown)
4100                 return IRQ_NONE;
4101
4102         wptr = cik_get_ih_wptr(rdev);
4103
4104 restart_ih:
4105         /* is somebody else already processing irqs? */
4106         if (atomic_xchg(&rdev->ih.lock, 1))
4107                 return IRQ_NONE;
4108
4109         rptr = rdev->ih.rptr;
4110         DRM_DEBUG("cik_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
4111
4112         /* Order reading of wptr vs. reading of IH ring data */
4113         rmb();
4114
4115         /* display interrupts */
4116         cik_irq_ack(rdev);
4117
4118         while (rptr != wptr) {
4119                 /* wptr/rptr are in bytes! */
4120                 ring_index = rptr / 4;
4121                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
4122                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
4123                 ring_id = le32_to_cpu(rdev->ih.ring[ring_index + 2]) & 0xff;
4124
4125                 switch (src_id) {
4126                 case 1: /* D1 vblank/vline */
4127                         switch (src_data) {
4128                         case 0: /* D1 vblank */
4129                                 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VBLANK_INTERRUPT) {
4130                                         if (rdev->irq.crtc_vblank_int[0]) {
4131                                                 drm_handle_vblank(rdev->ddev, 0);
4132                                                 rdev->pm.vblank_sync = true;
4133                                                 wake_up(&rdev->irq.vblank_queue);
4134                                         }
4135                                         if (atomic_read(&rdev->irq.pflip[0]))
4136                                                 radeon_crtc_handle_flip(rdev, 0);
4137                                         rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
4138                                         DRM_DEBUG("IH: D1 vblank\n");
4139                                 }
4140                                 break;
4141                         case 1: /* D1 vline */
4142                                 if (rdev->irq.stat_regs.cik.disp_int & LB_D1_VLINE_INTERRUPT) {
4143                                         rdev->irq.stat_regs.cik.disp_int &= ~LB_D1_VLINE_INTERRUPT;
4144                                         DRM_DEBUG("IH: D1 vline\n");
4145                                 }
4146                                 break;
4147                         default:
4148                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4149                                 break;
4150                         }
4151                         break;
4152                 case 2: /* D2 vblank/vline */
4153                         switch (src_data) {
4154                         case 0: /* D2 vblank */
4155                                 if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
4156                                         if (rdev->irq.crtc_vblank_int[1]) {
4157                                                 drm_handle_vblank(rdev->ddev, 1);
4158                                                 rdev->pm.vblank_sync = true;
4159                                                 wake_up(&rdev->irq.vblank_queue);
4160                                         }
4161                                         if (atomic_read(&rdev->irq.pflip[1]))
4162                                                 radeon_crtc_handle_flip(rdev, 1);
4163                                         rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
4164                                         DRM_DEBUG("IH: D2 vblank\n");
4165                                 }
4166                                 break;
4167                         case 1: /* D2 vline */
4168                                 if (rdev->irq.stat_regs.cik.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
4169                                         rdev->irq.stat_regs.cik.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
4170                                         DRM_DEBUG("IH: D2 vline\n");
4171                                 }
4172                                 break;
4173                         default:
4174                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4175                                 break;
4176                         }
4177                         break;
4178                 case 3: /* D3 vblank/vline */
4179                         switch (src_data) {
4180                         case 0: /* D3 vblank */
4181                                 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
4182                                         if (rdev->irq.crtc_vblank_int[2]) {
4183                                                 drm_handle_vblank(rdev->ddev, 2);
4184                                                 rdev->pm.vblank_sync = true;
4185                                                 wake_up(&rdev->irq.vblank_queue);
4186                                         }
4187                                         if (atomic_read(&rdev->irq.pflip[2]))
4188                                                 radeon_crtc_handle_flip(rdev, 2);
4189                                         rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
4190                                         DRM_DEBUG("IH: D3 vblank\n");
4191                                 }
4192                                 break;
4193                         case 1: /* D3 vline */
4194                                 if (rdev->irq.stat_regs.cik.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
4195                                         rdev->irq.stat_regs.cik.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
4196                                         DRM_DEBUG("IH: D3 vline\n");
4197                                 }
4198                                 break;
4199                         default:
4200                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4201                                 break;
4202                         }
4203                         break;
4204                 case 4: /* D4 vblank/vline */
4205                         switch (src_data) {
4206                         case 0: /* D4 vblank */
4207                                 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
4208                                         if (rdev->irq.crtc_vblank_int[3]) {
4209                                                 drm_handle_vblank(rdev->ddev, 3);
4210                                                 rdev->pm.vblank_sync = true;
4211                                                 wake_up(&rdev->irq.vblank_queue);
4212                                         }
4213                                         if (atomic_read(&rdev->irq.pflip[3]))
4214                                                 radeon_crtc_handle_flip(rdev, 3);
4215                                         rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
4216                                         DRM_DEBUG("IH: D4 vblank\n");
4217                                 }
4218                                 break;
4219                         case 1: /* D4 vline */
4220                                 if (rdev->irq.stat_regs.cik.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
4221                                         rdev->irq.stat_regs.cik.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
4222                                         DRM_DEBUG("IH: D4 vline\n");
4223                                 }
4224                                 break;
4225                         default:
4226                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4227                                 break;
4228                         }
4229                         break;
4230                 case 5: /* D5 vblank/vline */
4231                         switch (src_data) {
4232                         case 0: /* D5 vblank */
4233                                 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
4234                                         if (rdev->irq.crtc_vblank_int[4]) {
4235                                                 drm_handle_vblank(rdev->ddev, 4);
4236                                                 rdev->pm.vblank_sync = true;
4237                                                 wake_up(&rdev->irq.vblank_queue);
4238                                         }
4239                                         if (atomic_read(&rdev->irq.pflip[4]))
4240                                                 radeon_crtc_handle_flip(rdev, 4);
4241                                         rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
4242                                         DRM_DEBUG("IH: D5 vblank\n");
4243                                 }
4244                                 break;
4245                         case 1: /* D5 vline */
4246                                 if (rdev->irq.stat_regs.cik.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
4247                                         rdev->irq.stat_regs.cik.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
4248                                         DRM_DEBUG("IH: D5 vline\n");
4249                                 }
4250                                 break;
4251                         default:
4252                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4253                                 break;
4254                         }
4255                         break;
4256                 case 6: /* D6 vblank/vline */
4257                         switch (src_data) {
4258                         case 0: /* D6 vblank */
4259                                 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
4260                                         if (rdev->irq.crtc_vblank_int[5]) {
4261                                                 drm_handle_vblank(rdev->ddev, 5);
4262                                                 rdev->pm.vblank_sync = true;
4263                                                 wake_up(&rdev->irq.vblank_queue);
4264                                         }
4265                                         if (atomic_read(&rdev->irq.pflip[5]))
4266                                                 radeon_crtc_handle_flip(rdev, 5);
4267                                         rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
4268                                         DRM_DEBUG("IH: D6 vblank\n");
4269                                 }
4270                                 break;
4271                         case 1: /* D6 vline */
4272                                 if (rdev->irq.stat_regs.cik.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
4273                                         rdev->irq.stat_regs.cik.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
4274                                         DRM_DEBUG("IH: D6 vline\n");
4275                                 }
4276                                 break;
4277                         default:
4278                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4279                                 break;
4280                         }
4281                         break;
4282                 case 42: /* HPD hotplug */
4283                         switch (src_data) {
4284                         case 0:
4285                                 if (rdev->irq.stat_regs.cik.disp_int & DC_HPD1_INTERRUPT) {
4286                                         rdev->irq.stat_regs.cik.disp_int &= ~DC_HPD1_INTERRUPT;
4287                                         queue_hotplug = true;
4288                                         DRM_DEBUG("IH: HPD1\n");
4289                                 }
4290                                 break;
4291                         case 1:
4292                                 if (rdev->irq.stat_regs.cik.disp_int_cont & DC_HPD2_INTERRUPT) {
4293                                         rdev->irq.stat_regs.cik.disp_int_cont &= ~DC_HPD2_INTERRUPT;
4294                                         queue_hotplug = true;
4295                                         DRM_DEBUG("IH: HPD2\n");
4296                                 }
4297                                 break;
4298                         case 2:
4299                                 if (rdev->irq.stat_regs.cik.disp_int_cont2 & DC_HPD3_INTERRUPT) {
4300                                         rdev->irq.stat_regs.cik.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
4301                                         queue_hotplug = true;
4302                                         DRM_DEBUG("IH: HPD3\n");
4303                                 }
4304                                 break;
4305                         case 3:
4306                                 if (rdev->irq.stat_regs.cik.disp_int_cont3 & DC_HPD4_INTERRUPT) {
4307                                         rdev->irq.stat_regs.cik.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
4308                                         queue_hotplug = true;
4309                                         DRM_DEBUG("IH: HPD4\n");
4310                                 }
4311                                 break;
4312                         case 4:
4313                                 if (rdev->irq.stat_regs.cik.disp_int_cont4 & DC_HPD5_INTERRUPT) {
4314                                         rdev->irq.stat_regs.cik.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
4315                                         queue_hotplug = true;
4316                                         DRM_DEBUG("IH: HPD5\n");
4317                                 }
4318                                 break;
4319                         case 5:
4320                                 if (rdev->irq.stat_regs.cik.disp_int_cont5 & DC_HPD6_INTERRUPT) {
4321                                         rdev->irq.stat_regs.cik.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
4322                                         queue_hotplug = true;
4323                                         DRM_DEBUG("IH: HPD6\n");
4324                                 }
4325                                 break;
4326                         default:
4327                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4328                                 break;
4329                         }
4330                         break;
4331                 case 146:
4332                 case 147:
4333                         dev_err(rdev->dev, "GPU fault detected: %d 0x%08x\n", src_id, src_data);
4334                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_ADDR   0x%08X\n",
4335                                 RREG32(VM_CONTEXT1_PROTECTION_FAULT_ADDR));
4336                         dev_err(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
4337                                 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
4338                         /* reset addr and status */
4339                         WREG32_P(VM_CONTEXT1_CNTL2, 1, ~1);
4340                         break;
4341                 case 176: /* GFX RB CP_INT */
4342                 case 177: /* GFX IB CP_INT */
4343                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4344                         break;
4345                 case 181: /* CP EOP event */
4346                         DRM_DEBUG("IH: CP EOP\n");
4347                         /* XXX check the bitfield order! */
4348                         me_id = (ring_id & 0x60) >> 5;
4349                         pipe_id = (ring_id & 0x18) >> 3;
4350                         queue_id = (ring_id & 0x7) >> 0;
4351                         switch (me_id) {
4352                         case 0:
4353                                 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
4354                                 break;
4355                         case 1:
4356                                 /* XXX compute */
4357                                 break;
4358                         case 2:
4359                                 /* XXX compute */
4360                                 break;
4361                         }
4362                         break;
4363                 case 184: /* CP Privileged reg access */
4364                         DRM_ERROR("Illegal register access in command stream\n");
4365                         /* XXX check the bitfield order! */
4366                         me_id = (ring_id & 0x60) >> 5;
4367                         pipe_id = (ring_id & 0x18) >> 3;
4368                         queue_id = (ring_id & 0x7) >> 0;
4369                         switch (me_id) {
4370                         case 0:
4371                                 /* This results in a full GPU reset, but all we need to do is soft
4372                                  * reset the CP for gfx
4373                                  */
4374                                 queue_reset = true;
4375                                 break;
4376                         case 1:
4377                                 /* XXX compute */
4378                                 break;
4379                         case 2:
4380                                 /* XXX compute */
4381                                 break;
4382                         }
4383                         break;
4384                 case 185: /* CP Privileged inst */
4385                         DRM_ERROR("Illegal instruction in command stream\n");
4386                         /* XXX check the bitfield order! */
4387                         me_id = (ring_id & 0x60) >> 5;
4388                         pipe_id = (ring_id & 0x18) >> 3;
4389                         queue_id = (ring_id & 0x7) >> 0;
4390                         switch (me_id) {
4391                         case 0:
4392                                 /* This results in a full GPU reset, but all we need to do is soft
4393                                  * reset the CP for gfx
4394                                  */
4395                                 queue_reset = true;
4396                                 break;
4397                         case 1:
4398                                 /* XXX compute */
4399                                 break;
4400                         case 2:
4401                                 /* XXX compute */
4402                                 break;
4403                         }
4404                         break;
4405                 case 224: /* SDMA trap event */
4406                         /* XXX check the bitfield order! */
4407                         me_id = (ring_id & 0x3) >> 0;
4408                         queue_id = (ring_id & 0xc) >> 2;
4409                         DRM_DEBUG("IH: SDMA trap\n");
4410                         switch (me_id) {
4411                         case 0:
4412                                 switch (queue_id) {
4413                                 case 0:
4414                                         radeon_fence_process(rdev, R600_RING_TYPE_DMA_INDEX);
4415                                         break;
4416                                 case 1:
4417                                         /* XXX compute */
4418                                         break;
4419                                 case 2:
4420                                         /* XXX compute */
4421                                         break;
4422                                 }
4423                                 break;
4424                         case 1:
4425                                 switch (queue_id) {
4426                                 case 0:
4427                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_DMA1_INDEX);
4428                                         break;
4429                                 case 1:
4430                                         /* XXX compute */
4431                                         break;
4432                                 case 2:
4433                                         /* XXX compute */
4434                                         break;
4435                                 }
4436                                 break;
4437                         }
4438                         break;
4439                 case 241: /* SDMA Privileged inst */
4440                 case 247: /* SDMA Privileged inst */
4441                         DRM_ERROR("Illegal instruction in SDMA command stream\n");
4442                         /* XXX check the bitfield order! */
4443                         me_id = (ring_id & 0x3) >> 0;
4444                         queue_id = (ring_id & 0xc) >> 2;
4445                         switch (me_id) {
4446                         case 0:
4447                                 switch (queue_id) {
4448                                 case 0:
4449                                         queue_reset = true;
4450                                         break;
4451                                 case 1:
4452                                         /* XXX compute */
4453                                         queue_reset = true;
4454                                         break;
4455                                 case 2:
4456                                         /* XXX compute */
4457                                         queue_reset = true;
4458                                         break;
4459                                 }
4460                                 break;
4461                         case 1:
4462                                 switch (queue_id) {
4463                                 case 0:
4464                                         queue_reset = true;
4465                                         break;
4466                                 case 1:
4467                                         /* XXX compute */
4468                                         queue_reset = true;
4469                                         break;
4470                                 case 2:
4471                                         /* XXX compute */
4472                                         queue_reset = true;
4473                                         break;
4474                                 }
4475                                 break;
4476                         }
4477                         break;
4478                 case 233: /* GUI IDLE */
4479                         DRM_DEBUG("IH: GUI idle\n");
4480                         break;
4481                 default:
4482                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
4483                         break;
4484                 }
4485
4486                 /* wptr/rptr are in bytes! */
4487                 rptr += 16;
4488                 rptr &= rdev->ih.ptr_mask;
4489         }
4490         if (queue_hotplug)
4491                 schedule_work(&rdev->hotplug_work);
4492         if (queue_reset)
4493                 schedule_work(&rdev->reset_work);
4494         rdev->ih.rptr = rptr;
4495         WREG32(IH_RB_RPTR, rdev->ih.rptr);
4496         atomic_set(&rdev->ih.lock, 0);
4497
4498         /* make sure wptr hasn't changed while processing */
4499         wptr = cik_get_ih_wptr(rdev);
4500         if (wptr != rptr)
4501                 goto restart_ih;
4502
4503         return IRQ_HANDLED;
4504 }