2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
42 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
43 * @intel_dp: DP struct
45 * If a CPU or PCH DP output is attached to an eDP panel, this function
46 * will return true, and false otherwise.
48 static bool is_edp(struct intel_dp *intel_dp)
50 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
52 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
56 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
57 * @intel_dp: DP struct
59 * Returns true if the given DP struct corresponds to a PCH DP port attached
60 * to an eDP panel, false otherwise. Helpful for determining whether we
61 * may need FDI resources for a given DP output or not.
63 static bool is_pch_edp(struct intel_dp *intel_dp)
65 return intel_dp->is_pch_edp;
69 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
70 * @intel_dp: DP struct
72 * Returns true if the given DP struct corresponds to a CPU eDP port.
74 static bool is_cpu_edp(struct intel_dp *intel_dp)
76 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
79 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
81 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
83 return intel_dig_port->base.base.dev;
86 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
88 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
92 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
93 * @encoder: DRM encoder
95 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
98 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
100 struct intel_dp *intel_dp;
105 intel_dp = enc_to_intel_dp(encoder);
107 return is_pch_edp(intel_dp);
110 static void intel_dp_link_down(struct intel_dp *intel_dp);
113 intel_edp_link_config(struct intel_encoder *intel_encoder,
114 int *lane_num, int *link_bw)
116 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
118 *lane_num = intel_dp->lane_count;
119 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
123 intel_edp_target_clock(struct intel_encoder *intel_encoder,
124 struct drm_display_mode *mode)
126 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
127 struct intel_connector *intel_connector = intel_dp->attached_connector;
129 if (intel_connector->panel.fixed_mode)
130 return intel_connector->panel.fixed_mode->clock;
136 intel_dp_max_link_bw(struct intel_dp *intel_dp)
138 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
140 switch (max_link_bw) {
141 case DP_LINK_BW_1_62:
145 max_link_bw = DP_LINK_BW_1_62;
152 * The units on the numbers in the next two are... bizarre. Examples will
153 * make it clearer; this one parallels an example in the eDP spec.
155 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
157 * 270000 * 1 * 8 / 10 == 216000
159 * The actual data capacity of that configuration is 2.16Gbit/s, so the
160 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
161 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
162 * 119000. At 18bpp that's 2142000 kilobits per second.
164 * Thus the strange-looking division by 10 in intel_dp_link_required, to
165 * get the result in decakilobits instead of kilobits.
169 intel_dp_link_required(int pixel_clock, int bpp)
171 return (pixel_clock * bpp + 9) / 10;
175 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
177 return (max_link_clock * max_lanes * 8) / 10;
181 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
182 struct drm_display_mode *mode,
186 drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
187 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
188 int max_rate, mode_rate;
190 mode_rate = intel_dp_link_required(mode->clock, 24);
191 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
193 if (mode_rate > max_rate) {
194 mode_rate = intel_dp_link_required(mode->clock, 18);
195 if (mode_rate > max_rate)
200 |= INTEL_MODE_DP_FORCE_6BPC;
209 intel_dp_mode_valid(struct drm_connector *connector,
210 struct drm_display_mode *mode)
212 struct intel_dp *intel_dp = intel_attached_dp(connector);
213 struct intel_connector *intel_connector = to_intel_connector(connector);
214 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
216 if (is_edp(intel_dp) && fixed_mode) {
217 if (mode->hdisplay > fixed_mode->hdisplay)
220 if (mode->vdisplay > fixed_mode->vdisplay)
224 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
225 return MODE_CLOCK_HIGH;
227 if (mode->clock < 10000)
228 return MODE_CLOCK_LOW;
230 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
231 return MODE_H_ILLEGAL;
237 pack_aux(uint8_t *src, int src_bytes)
244 for (i = 0; i < src_bytes; i++)
245 v |= ((uint32_t) src[i]) << ((3-i) * 8);
250 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
255 for (i = 0; i < dst_bytes; i++)
256 dst[i] = src >> ((3-i) * 8);
259 /* hrawclock is 1/4 the FSB frequency */
261 intel_hrawclk(struct drm_device *dev)
263 struct drm_i915_private *dev_priv = dev->dev_private;
266 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
267 if (IS_VALLEYVIEW(dev))
270 clkcfg = I915_READ(CLKCFG);
271 switch (clkcfg & CLKCFG_FSB_MASK) {
280 case CLKCFG_FSB_1067:
282 case CLKCFG_FSB_1333:
284 /* these two are just a guess; one of them might be right */
285 case CLKCFG_FSB_1600:
286 case CLKCFG_FSB_1600_ALT:
293 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
295 struct drm_device *dev = intel_dp_to_dev(intel_dp);
296 struct drm_i915_private *dev_priv = dev->dev_private;
298 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
301 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
303 struct drm_device *dev = intel_dp_to_dev(intel_dp);
304 struct drm_i915_private *dev_priv = dev->dev_private;
306 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
310 intel_dp_check_edp(struct intel_dp *intel_dp)
312 struct drm_device *dev = intel_dp_to_dev(intel_dp);
313 struct drm_i915_private *dev_priv = dev->dev_private;
315 if (!is_edp(intel_dp))
317 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
318 WARN(1, "eDP powered off while attempting aux channel communication.\n");
319 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
320 I915_READ(PCH_PP_STATUS),
321 I915_READ(PCH_PP_CONTROL));
326 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
328 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
329 struct drm_device *dev = intel_dig_port->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
331 uint32_t ch_ctl = intel_dp->output_reg + 0x10;
335 if (IS_HASWELL(dev)) {
336 switch (intel_dig_port->port) {
338 ch_ctl = DPA_AUX_CH_CTL;
341 ch_ctl = PCH_DPB_AUX_CH_CTL;
344 ch_ctl = PCH_DPC_AUX_CH_CTL;
347 ch_ctl = PCH_DPD_AUX_CH_CTL;
354 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
356 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);
358 done = wait_for_atomic(C, 10) == 0;
360 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
368 intel_dp_aux_ch(struct intel_dp *intel_dp,
369 uint8_t *send, int send_bytes,
370 uint8_t *recv, int recv_size)
372 uint32_t output_reg = intel_dp->output_reg;
373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
374 struct drm_device *dev = intel_dig_port->base.base.dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
376 uint32_t ch_ctl = output_reg + 0x10;
377 uint32_t ch_data = ch_ctl + 4;
378 int i, ret, recv_bytes;
380 uint32_t aux_clock_divider;
382 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
384 /* dp aux is extremely sensitive to irq latency, hence request the
385 * lowest possible wakeup latency and so prevent the cpu from going into
388 pm_qos_update_request(&dev_priv->pm_qos, 0);
390 if (IS_HASWELL(dev)) {
391 switch (intel_dig_port->port) {
393 ch_ctl = DPA_AUX_CH_CTL;
394 ch_data = DPA_AUX_CH_DATA1;
397 ch_ctl = PCH_DPB_AUX_CH_CTL;
398 ch_data = PCH_DPB_AUX_CH_DATA1;
401 ch_ctl = PCH_DPC_AUX_CH_CTL;
402 ch_data = PCH_DPC_AUX_CH_DATA1;
405 ch_ctl = PCH_DPD_AUX_CH_CTL;
406 ch_data = PCH_DPD_AUX_CH_DATA1;
413 intel_dp_check_edp(intel_dp);
414 /* The clock divider is based off the hrawclk,
415 * and would like to run at 2MHz. So, take the
416 * hrawclk value and divide by 2 and use that
418 * Note that PCH attached eDP panels should use a 125MHz input
421 if (is_cpu_edp(intel_dp)) {
423 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
424 else if (IS_VALLEYVIEW(dev))
425 aux_clock_divider = 100;
426 else if (IS_GEN6(dev) || IS_GEN7(dev))
427 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
429 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
430 } else if (HAS_PCH_SPLIT(dev))
431 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
433 aux_clock_divider = intel_hrawclk(dev) / 2;
440 /* Try to wait for any previous AUX channel activity */
441 for (try = 0; try < 3; try++) {
442 status = I915_READ_NOTRACE(ch_ctl);
443 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
449 WARN(1, "dp_aux_ch not started status 0x%08x\n",
455 /* Must try at least 3 times according to DP spec */
456 for (try = 0; try < 5; try++) {
457 /* Load the send data into the aux channel data registers */
458 for (i = 0; i < send_bytes; i += 4)
459 I915_WRITE(ch_data + i,
460 pack_aux(send + i, send_bytes - i));
462 /* Send the command and wait for it to complete */
464 DP_AUX_CH_CTL_SEND_BUSY |
465 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
466 DP_AUX_CH_CTL_TIME_OUT_400us |
467 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
468 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
469 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
471 DP_AUX_CH_CTL_TIME_OUT_ERROR |
472 DP_AUX_CH_CTL_RECEIVE_ERROR);
474 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
476 /* Clear done status and any errors */
480 DP_AUX_CH_CTL_TIME_OUT_ERROR |
481 DP_AUX_CH_CTL_RECEIVE_ERROR);
483 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
484 DP_AUX_CH_CTL_RECEIVE_ERROR))
486 if (status & DP_AUX_CH_CTL_DONE)
490 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
491 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
496 /* Check for timeout or receive error.
497 * Timeouts occur when the sink is not connected
499 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
500 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
505 /* Timeouts occur when the device isn't connected, so they're
506 * "normal" -- don't fill the kernel log with these */
507 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
508 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
513 /* Unload any bytes sent back from the other side */
514 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
515 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
516 if (recv_bytes > recv_size)
517 recv_bytes = recv_size;
519 for (i = 0; i < recv_bytes; i += 4)
520 unpack_aux(I915_READ(ch_data + i),
521 recv + i, recv_bytes - i);
525 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
530 /* Write data to the aux channel in native mode */
532 intel_dp_aux_native_write(struct intel_dp *intel_dp,
533 uint16_t address, uint8_t *send, int send_bytes)
540 intel_dp_check_edp(intel_dp);
543 msg[0] = AUX_NATIVE_WRITE << 4;
544 msg[1] = address >> 8;
545 msg[2] = address & 0xff;
546 msg[3] = send_bytes - 1;
547 memcpy(&msg[4], send, send_bytes);
548 msg_bytes = send_bytes + 4;
550 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
553 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
555 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
563 /* Write a single byte to the aux channel in native mode */
565 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
566 uint16_t address, uint8_t byte)
568 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
571 /* read bytes from a native aux channel */
573 intel_dp_aux_native_read(struct intel_dp *intel_dp,
574 uint16_t address, uint8_t *recv, int recv_bytes)
583 intel_dp_check_edp(intel_dp);
584 msg[0] = AUX_NATIVE_READ << 4;
585 msg[1] = address >> 8;
586 msg[2] = address & 0xff;
587 msg[3] = recv_bytes - 1;
590 reply_bytes = recv_bytes + 1;
593 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
600 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
601 memcpy(recv, reply + 1, ret - 1);
604 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
612 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
613 uint8_t write_byte, uint8_t *read_byte)
615 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
616 struct intel_dp *intel_dp = container_of(adapter,
619 uint16_t address = algo_data->address;
627 intel_dp_check_edp(intel_dp);
628 /* Set up the command byte */
629 if (mode & MODE_I2C_READ)
630 msg[0] = AUX_I2C_READ << 4;
632 msg[0] = AUX_I2C_WRITE << 4;
634 if (!(mode & MODE_I2C_STOP))
635 msg[0] |= AUX_I2C_MOT << 4;
637 msg[1] = address >> 8;
658 for (retry = 0; retry < 5; retry++) {
659 ret = intel_dp_aux_ch(intel_dp,
663 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
667 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
668 case AUX_NATIVE_REPLY_ACK:
669 /* I2C-over-AUX Reply field is only valid
670 * when paired with AUX ACK.
673 case AUX_NATIVE_REPLY_NACK:
674 DRM_DEBUG_KMS("aux_ch native nack\n");
676 case AUX_NATIVE_REPLY_DEFER:
680 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
685 switch (reply[0] & AUX_I2C_REPLY_MASK) {
686 case AUX_I2C_REPLY_ACK:
687 if (mode == MODE_I2C_READ) {
688 *read_byte = reply[1];
690 return reply_bytes - 1;
691 case AUX_I2C_REPLY_NACK:
692 DRM_DEBUG_KMS("aux_i2c nack\n");
694 case AUX_I2C_REPLY_DEFER:
695 DRM_DEBUG_KMS("aux_i2c defer\n");
699 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
704 DRM_ERROR("too many retries, giving up\n");
709 intel_dp_i2c_init(struct intel_dp *intel_dp,
710 struct intel_connector *intel_connector, const char *name)
714 DRM_DEBUG_KMS("i2c_init %s\n", name);
715 intel_dp->algo.running = false;
716 intel_dp->algo.address = 0;
717 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
719 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
720 intel_dp->adapter.owner = THIS_MODULE;
721 intel_dp->adapter.class = I2C_CLASS_DDC;
722 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
723 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
724 intel_dp->adapter.algo_data = &intel_dp->algo;
725 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
727 ironlake_edp_panel_vdd_on(intel_dp);
728 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
729 ironlake_edp_panel_vdd_off(intel_dp, false);
734 intel_dp_mode_fixup(struct drm_encoder *encoder,
735 const struct drm_display_mode *mode,
736 struct drm_display_mode *adjusted_mode)
738 struct drm_device *dev = encoder->dev;
739 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
740 struct intel_connector *intel_connector = intel_dp->attached_connector;
741 int lane_count, clock;
742 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
743 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
745 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
747 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
748 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
750 intel_pch_panel_fitting(dev,
751 intel_connector->panel.fitting_mode,
752 mode, adjusted_mode);
755 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
758 DRM_DEBUG_KMS("DP link computation with max lane count %i "
759 "max bw %02x pixel clock %iKHz\n",
760 max_lane_count, bws[max_clock], adjusted_mode->clock);
762 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
765 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
766 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
768 for (clock = 0; clock <= max_clock; clock++) {
769 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
771 drm_dp_bw_code_to_link_rate(bws[clock]);
772 int link_avail = intel_dp_max_data_rate(link_bw_clock,
775 if (mode_rate <= link_avail) {
776 intel_dp->link_bw = bws[clock];
777 intel_dp->lane_count = lane_count;
778 adjusted_mode->clock = link_bw_clock;
779 DRM_DEBUG_KMS("DP link bw %02x lane "
780 "count %d clock %d bpp %d\n",
781 intel_dp->link_bw, intel_dp->lane_count,
782 adjusted_mode->clock, bpp);
783 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
784 mode_rate, link_avail);
794 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
795 struct drm_display_mode *adjusted_mode)
797 struct drm_device *dev = crtc->dev;
798 struct intel_encoder *intel_encoder;
799 struct intel_dp *intel_dp;
800 struct drm_i915_private *dev_priv = dev->dev_private;
801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
803 struct intel_link_m_n m_n;
804 int pipe = intel_crtc->pipe;
805 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
808 * Find the lane count in the intel_encoder private
810 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
811 intel_dp = enc_to_intel_dp(&intel_encoder->base);
813 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
814 intel_encoder->type == INTEL_OUTPUT_EDP)
816 lane_count = intel_dp->lane_count;
822 * Compute the GMCH and Link ratios. The '3' here is
823 * the number of bytes_per_pixel post-LUT, which we always
824 * set up for 8-bits of R/G/B, or 3 bytes total.
826 intel_link_compute_m_n(intel_crtc->bpp, lane_count,
827 mode->clock, adjusted_mode->clock, &m_n);
829 if (IS_HASWELL(dev)) {
830 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
831 TU_SIZE(m_n.tu) | m_n.gmch_m);
832 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
833 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
834 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
835 } else if (HAS_PCH_SPLIT(dev)) {
836 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
837 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
838 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
839 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
840 } else if (IS_VALLEYVIEW(dev)) {
841 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
842 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
843 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
844 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
846 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
847 TU_SIZE(m_n.tu) | m_n.gmch_m);
848 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
849 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
850 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
854 void intel_dp_init_link_config(struct intel_dp *intel_dp)
856 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
857 intel_dp->link_configuration[0] = intel_dp->link_bw;
858 intel_dp->link_configuration[1] = intel_dp->lane_count;
859 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
861 * Check for DPCD version > 1.1 and enhanced framing support
863 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
864 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
865 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
869 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
871 struct drm_device *dev = crtc->dev;
872 struct drm_i915_private *dev_priv = dev->dev_private;
875 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
876 dpa_ctl = I915_READ(DP_A);
877 dpa_ctl &= ~DP_PLL_FREQ_MASK;
879 if (clock < 200000) {
880 /* For a long time we've carried around a ILK-DevA w/a for the
881 * 160MHz clock. If we're really unlucky, it's still required.
883 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
884 dpa_ctl |= DP_PLL_FREQ_160MHZ;
886 dpa_ctl |= DP_PLL_FREQ_270MHZ;
889 I915_WRITE(DP_A, dpa_ctl);
896 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
897 struct drm_display_mode *adjusted_mode)
899 struct drm_device *dev = encoder->dev;
900 struct drm_i915_private *dev_priv = dev->dev_private;
901 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
902 struct drm_crtc *crtc = encoder->crtc;
903 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
906 * There are four kinds of DP registers:
913 * IBX PCH and CPU are the same for almost everything,
914 * except that the CPU DP PLL is configured in this
917 * CPT PCH is quite different, having many bits moved
918 * to the TRANS_DP_CTL register instead. That
919 * configuration happens (oddly) in ironlake_pch_enable
922 /* Preserve the BIOS-computed detected bit. This is
923 * supposed to be read-only.
925 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
927 /* Handle DP bits in common between all three register formats */
928 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
930 switch (intel_dp->lane_count) {
932 intel_dp->DP |= DP_PORT_WIDTH_1;
935 intel_dp->DP |= DP_PORT_WIDTH_2;
938 intel_dp->DP |= DP_PORT_WIDTH_4;
941 if (intel_dp->has_audio) {
942 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
943 pipe_name(intel_crtc->pipe));
944 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
945 intel_write_eld(encoder, adjusted_mode);
948 intel_dp_init_link_config(intel_dp);
950 /* Split out the IBX/CPU vs CPT settings */
952 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
953 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
954 intel_dp->DP |= DP_SYNC_HS_HIGH;
955 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
956 intel_dp->DP |= DP_SYNC_VS_HIGH;
957 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
959 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
960 intel_dp->DP |= DP_ENHANCED_FRAMING;
962 intel_dp->DP |= intel_crtc->pipe << 29;
964 /* don't miss out required setting for eDP */
965 if (adjusted_mode->clock < 200000)
966 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
968 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
969 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
970 intel_dp->DP |= intel_dp->color_range;
972 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
973 intel_dp->DP |= DP_SYNC_HS_HIGH;
974 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
975 intel_dp->DP |= DP_SYNC_VS_HIGH;
976 intel_dp->DP |= DP_LINK_TRAIN_OFF;
978 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
979 intel_dp->DP |= DP_ENHANCED_FRAMING;
981 if (intel_crtc->pipe == 1)
982 intel_dp->DP |= DP_PIPEB_SELECT;
984 if (is_cpu_edp(intel_dp)) {
985 /* don't miss out required setting for eDP */
986 if (adjusted_mode->clock < 200000)
987 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
989 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
992 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
995 if (is_cpu_edp(intel_dp))
996 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
999 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1000 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1002 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1003 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1005 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1006 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1008 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1012 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1015 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1017 I915_READ(PCH_PP_STATUS),
1018 I915_READ(PCH_PP_CONTROL));
1020 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
1021 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1022 I915_READ(PCH_PP_STATUS),
1023 I915_READ(PCH_PP_CONTROL));
1027 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1029 DRM_DEBUG_KMS("Wait for panel power on\n");
1030 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1033 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1035 DRM_DEBUG_KMS("Wait for panel power off time\n");
1036 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1039 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1041 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1042 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1046 /* Read the current pp_control value, unlocking the register if it
1050 static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1052 u32 control = I915_READ(PCH_PP_CONTROL);
1054 control &= ~PANEL_UNLOCK_MASK;
1055 control |= PANEL_UNLOCK_REGS;
1059 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1061 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1062 struct drm_i915_private *dev_priv = dev->dev_private;
1065 if (!is_edp(intel_dp))
1067 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1069 WARN(intel_dp->want_panel_vdd,
1070 "eDP VDD already requested on\n");
1072 intel_dp->want_panel_vdd = true;
1074 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1075 DRM_DEBUG_KMS("eDP VDD already on\n");
1079 if (!ironlake_edp_have_panel_power(intel_dp))
1080 ironlake_wait_panel_power_cycle(intel_dp);
1082 pp = ironlake_get_pp_control(dev_priv);
1083 pp |= EDP_FORCE_VDD;
1084 I915_WRITE(PCH_PP_CONTROL, pp);
1085 POSTING_READ(PCH_PP_CONTROL);
1086 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1087 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1090 * If the panel wasn't on, delay before accessing aux channel
1092 if (!ironlake_edp_have_panel_power(intel_dp)) {
1093 DRM_DEBUG_KMS("eDP was not running\n");
1094 msleep(intel_dp->panel_power_up_delay);
1098 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1100 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1101 struct drm_i915_private *dev_priv = dev->dev_private;
1104 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1105 pp = ironlake_get_pp_control(dev_priv);
1106 pp &= ~EDP_FORCE_VDD;
1107 I915_WRITE(PCH_PP_CONTROL, pp);
1108 POSTING_READ(PCH_PP_CONTROL);
1110 /* Make sure sequencer is idle before allowing subsequent activity */
1111 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1112 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1114 msleep(intel_dp->panel_power_down_delay);
1118 static void ironlake_panel_vdd_work(struct work_struct *__work)
1120 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1121 struct intel_dp, panel_vdd_work);
1122 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1124 mutex_lock(&dev->mode_config.mutex);
1125 ironlake_panel_vdd_off_sync(intel_dp);
1126 mutex_unlock(&dev->mode_config.mutex);
1129 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1131 if (!is_edp(intel_dp))
1134 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1135 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1137 intel_dp->want_panel_vdd = false;
1140 ironlake_panel_vdd_off_sync(intel_dp);
1143 * Queue the timer to fire a long
1144 * time from now (relative to the power down delay)
1145 * to keep the panel power up across a sequence of operations
1147 schedule_delayed_work(&intel_dp->panel_vdd_work,
1148 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1152 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1154 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1155 struct drm_i915_private *dev_priv = dev->dev_private;
1158 if (!is_edp(intel_dp))
1161 DRM_DEBUG_KMS("Turn eDP power on\n");
1163 if (ironlake_edp_have_panel_power(intel_dp)) {
1164 DRM_DEBUG_KMS("eDP power already on\n");
1168 ironlake_wait_panel_power_cycle(intel_dp);
1170 pp = ironlake_get_pp_control(dev_priv);
1172 /* ILK workaround: disable reset around power sequence */
1173 pp &= ~PANEL_POWER_RESET;
1174 I915_WRITE(PCH_PP_CONTROL, pp);
1175 POSTING_READ(PCH_PP_CONTROL);
1178 pp |= POWER_TARGET_ON;
1180 pp |= PANEL_POWER_RESET;
1182 I915_WRITE(PCH_PP_CONTROL, pp);
1183 POSTING_READ(PCH_PP_CONTROL);
1185 ironlake_wait_panel_on(intel_dp);
1188 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1189 I915_WRITE(PCH_PP_CONTROL, pp);
1190 POSTING_READ(PCH_PP_CONTROL);
1194 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1196 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1197 struct drm_i915_private *dev_priv = dev->dev_private;
1200 if (!is_edp(intel_dp))
1203 DRM_DEBUG_KMS("Turn eDP power off\n");
1205 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1207 pp = ironlake_get_pp_control(dev_priv);
1208 /* We need to switch off panel power _and_ force vdd, for otherwise some
1209 * panels get very unhappy and cease to work. */
1210 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1211 I915_WRITE(PCH_PP_CONTROL, pp);
1212 POSTING_READ(PCH_PP_CONTROL);
1214 intel_dp->want_panel_vdd = false;
1216 ironlake_wait_panel_off(intel_dp);
1219 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1221 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1222 struct drm_device *dev = intel_dig_port->base.base.dev;
1223 struct drm_i915_private *dev_priv = dev->dev_private;
1224 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1227 if (!is_edp(intel_dp))
1230 DRM_DEBUG_KMS("\n");
1232 * If we enable the backlight right away following a panel power
1233 * on, we may see slight flicker as the panel syncs with the eDP
1234 * link. So delay a bit to make sure the image is solid before
1235 * allowing it to appear.
1237 msleep(intel_dp->backlight_on_delay);
1238 pp = ironlake_get_pp_control(dev_priv);
1239 pp |= EDP_BLC_ENABLE;
1240 I915_WRITE(PCH_PP_CONTROL, pp);
1241 POSTING_READ(PCH_PP_CONTROL);
1243 intel_panel_enable_backlight(dev, pipe);
1246 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1248 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1249 struct drm_i915_private *dev_priv = dev->dev_private;
1252 if (!is_edp(intel_dp))
1255 intel_panel_disable_backlight(dev);
1257 DRM_DEBUG_KMS("\n");
1258 pp = ironlake_get_pp_control(dev_priv);
1259 pp &= ~EDP_BLC_ENABLE;
1260 I915_WRITE(PCH_PP_CONTROL, pp);
1261 POSTING_READ(PCH_PP_CONTROL);
1262 msleep(intel_dp->backlight_off_delay);
1265 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1267 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1268 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1269 struct drm_device *dev = crtc->dev;
1270 struct drm_i915_private *dev_priv = dev->dev_private;
1273 assert_pipe_disabled(dev_priv,
1274 to_intel_crtc(crtc)->pipe);
1276 DRM_DEBUG_KMS("\n");
1277 dpa_ctl = I915_READ(DP_A);
1278 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1279 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1281 /* We don't adjust intel_dp->DP while tearing down the link, to
1282 * facilitate link retraining (e.g. after hotplug). Hence clear all
1283 * enable bits here to ensure that we don't enable too much. */
1284 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1285 intel_dp->DP |= DP_PLL_ENABLE;
1286 I915_WRITE(DP_A, intel_dp->DP);
1291 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1293 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1294 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1295 struct drm_device *dev = crtc->dev;
1296 struct drm_i915_private *dev_priv = dev->dev_private;
1299 assert_pipe_disabled(dev_priv,
1300 to_intel_crtc(crtc)->pipe);
1302 dpa_ctl = I915_READ(DP_A);
1303 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1304 "dp pll off, should be on\n");
1305 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1307 /* We can't rely on the value tracked for the DP register in
1308 * intel_dp->DP because link_down must not change that (otherwise link
1309 * re-training will fail. */
1310 dpa_ctl &= ~DP_PLL_ENABLE;
1311 I915_WRITE(DP_A, dpa_ctl);
1316 /* If the sink supports it, try to set the power state appropriately */
1317 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1321 /* Should have a valid DPCD by this point */
1322 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1325 if (mode != DRM_MODE_DPMS_ON) {
1326 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1329 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1332 * When turning on, we need to retry for 1ms to give the sink
1335 for (i = 0; i < 3; i++) {
1336 ret = intel_dp_aux_native_write_1(intel_dp,
1346 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1349 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1350 struct drm_device *dev = encoder->base.dev;
1351 struct drm_i915_private *dev_priv = dev->dev_private;
1352 u32 tmp = I915_READ(intel_dp->output_reg);
1354 if (!(tmp & DP_PORT_EN))
1357 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1358 *pipe = PORT_TO_PIPE_CPT(tmp);
1359 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1360 *pipe = PORT_TO_PIPE(tmp);
1366 switch (intel_dp->output_reg) {
1368 trans_sel = TRANS_DP_PORT_SEL_B;
1371 trans_sel = TRANS_DP_PORT_SEL_C;
1374 trans_sel = TRANS_DP_PORT_SEL_D;
1381 trans_dp = I915_READ(TRANS_DP_CTL(i));
1382 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1388 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1389 intel_dp->output_reg);
1395 static void intel_disable_dp(struct intel_encoder *encoder)
1397 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1399 /* Make sure the panel is off before trying to change the mode. But also
1400 * ensure that we have vdd while we switch off the panel. */
1401 ironlake_edp_panel_vdd_on(intel_dp);
1402 ironlake_edp_backlight_off(intel_dp);
1403 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1404 ironlake_edp_panel_off(intel_dp);
1406 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1407 if (!is_cpu_edp(intel_dp))
1408 intel_dp_link_down(intel_dp);
1411 static void intel_post_disable_dp(struct intel_encoder *encoder)
1413 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1415 if (is_cpu_edp(intel_dp)) {
1416 intel_dp_link_down(intel_dp);
1417 ironlake_edp_pll_off(intel_dp);
1421 static void intel_enable_dp(struct intel_encoder *encoder)
1423 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1424 struct drm_device *dev = encoder->base.dev;
1425 struct drm_i915_private *dev_priv = dev->dev_private;
1426 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1428 if (WARN_ON(dp_reg & DP_PORT_EN))
1431 ironlake_edp_panel_vdd_on(intel_dp);
1432 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1433 intel_dp_start_link_train(intel_dp);
1434 ironlake_edp_panel_on(intel_dp);
1435 ironlake_edp_panel_vdd_off(intel_dp, true);
1436 intel_dp_complete_link_train(intel_dp);
1437 ironlake_edp_backlight_on(intel_dp);
1440 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1442 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1444 if (is_cpu_edp(intel_dp))
1445 ironlake_edp_pll_on(intel_dp);
1449 * Native read with retry for link status and receiver capability reads for
1450 * cases where the sink may still be asleep.
1453 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1454 uint8_t *recv, int recv_bytes)
1459 * Sinks are *supposed* to come up within 1ms from an off state,
1460 * but we're also supposed to retry 3 times per the spec.
1462 for (i = 0; i < 3; i++) {
1463 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1465 if (ret == recv_bytes)
1474 * Fetch AUX CH registers 0x202 - 0x207 which contain
1475 * link status information
1478 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1480 return intel_dp_aux_native_read_retry(intel_dp,
1483 DP_LINK_STATUS_SIZE);
1487 static char *voltage_names[] = {
1488 "0.4V", "0.6V", "0.8V", "1.2V"
1490 static char *pre_emph_names[] = {
1491 "0dB", "3.5dB", "6dB", "9.5dB"
1493 static char *link_train_names[] = {
1494 "pattern 1", "pattern 2", "idle", "off"
1499 * These are source-specific values; current Intel hardware supports
1500 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1504 intel_dp_voltage_max(struct intel_dp *intel_dp)
1506 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1508 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1509 return DP_TRAIN_VOLTAGE_SWING_800;
1510 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1511 return DP_TRAIN_VOLTAGE_SWING_1200;
1513 return DP_TRAIN_VOLTAGE_SWING_800;
1517 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1519 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1521 if (IS_HASWELL(dev)) {
1522 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1523 case DP_TRAIN_VOLTAGE_SWING_400:
1524 return DP_TRAIN_PRE_EMPHASIS_9_5;
1525 case DP_TRAIN_VOLTAGE_SWING_600:
1526 return DP_TRAIN_PRE_EMPHASIS_6;
1527 case DP_TRAIN_VOLTAGE_SWING_800:
1528 return DP_TRAIN_PRE_EMPHASIS_3_5;
1529 case DP_TRAIN_VOLTAGE_SWING_1200:
1531 return DP_TRAIN_PRE_EMPHASIS_0;
1533 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1534 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1535 case DP_TRAIN_VOLTAGE_SWING_400:
1536 return DP_TRAIN_PRE_EMPHASIS_6;
1537 case DP_TRAIN_VOLTAGE_SWING_600:
1538 case DP_TRAIN_VOLTAGE_SWING_800:
1539 return DP_TRAIN_PRE_EMPHASIS_3_5;
1541 return DP_TRAIN_PRE_EMPHASIS_0;
1544 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1545 case DP_TRAIN_VOLTAGE_SWING_400:
1546 return DP_TRAIN_PRE_EMPHASIS_6;
1547 case DP_TRAIN_VOLTAGE_SWING_600:
1548 return DP_TRAIN_PRE_EMPHASIS_6;
1549 case DP_TRAIN_VOLTAGE_SWING_800:
1550 return DP_TRAIN_PRE_EMPHASIS_3_5;
1551 case DP_TRAIN_VOLTAGE_SWING_1200:
1553 return DP_TRAIN_PRE_EMPHASIS_0;
1559 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1564 uint8_t voltage_max;
1565 uint8_t preemph_max;
1567 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1568 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1569 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1577 voltage_max = intel_dp_voltage_max(intel_dp);
1578 if (v >= voltage_max)
1579 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1581 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1582 if (p >= preemph_max)
1583 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1585 for (lane = 0; lane < 4; lane++)
1586 intel_dp->train_set[lane] = v | p;
1590 intel_dp_signal_levels(uint8_t train_set)
1592 uint32_t signal_levels = 0;
1594 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1595 case DP_TRAIN_VOLTAGE_SWING_400:
1597 signal_levels |= DP_VOLTAGE_0_4;
1599 case DP_TRAIN_VOLTAGE_SWING_600:
1600 signal_levels |= DP_VOLTAGE_0_6;
1602 case DP_TRAIN_VOLTAGE_SWING_800:
1603 signal_levels |= DP_VOLTAGE_0_8;
1605 case DP_TRAIN_VOLTAGE_SWING_1200:
1606 signal_levels |= DP_VOLTAGE_1_2;
1609 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1610 case DP_TRAIN_PRE_EMPHASIS_0:
1612 signal_levels |= DP_PRE_EMPHASIS_0;
1614 case DP_TRAIN_PRE_EMPHASIS_3_5:
1615 signal_levels |= DP_PRE_EMPHASIS_3_5;
1617 case DP_TRAIN_PRE_EMPHASIS_6:
1618 signal_levels |= DP_PRE_EMPHASIS_6;
1620 case DP_TRAIN_PRE_EMPHASIS_9_5:
1621 signal_levels |= DP_PRE_EMPHASIS_9_5;
1624 return signal_levels;
1627 /* Gen6's DP voltage swing and pre-emphasis control */
1629 intel_gen6_edp_signal_levels(uint8_t train_set)
1631 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1632 DP_TRAIN_PRE_EMPHASIS_MASK);
1633 switch (signal_levels) {
1634 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1635 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1636 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1637 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1638 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1639 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1640 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1641 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1642 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1643 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1644 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1645 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1646 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1647 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1649 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1650 "0x%x\n", signal_levels);
1651 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1655 /* Gen7's DP voltage swing and pre-emphasis control */
1657 intel_gen7_edp_signal_levels(uint8_t train_set)
1659 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1660 DP_TRAIN_PRE_EMPHASIS_MASK);
1661 switch (signal_levels) {
1662 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1663 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1664 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1665 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1666 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1667 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1669 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1670 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1671 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1672 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1674 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1675 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1676 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1677 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1680 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1681 "0x%x\n", signal_levels);
1682 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1686 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1688 intel_dp_signal_levels_hsw(uint8_t train_set)
1690 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1691 DP_TRAIN_PRE_EMPHASIS_MASK);
1692 switch (signal_levels) {
1693 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1694 return DDI_BUF_EMP_400MV_0DB_HSW;
1695 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1696 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1697 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1698 return DDI_BUF_EMP_400MV_6DB_HSW;
1699 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1700 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1702 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1703 return DDI_BUF_EMP_600MV_0DB_HSW;
1704 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1705 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1706 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1707 return DDI_BUF_EMP_600MV_6DB_HSW;
1709 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1710 return DDI_BUF_EMP_800MV_0DB_HSW;
1711 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1712 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1714 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1715 "0x%x\n", signal_levels);
1716 return DDI_BUF_EMP_400MV_0DB_HSW;
1721 intel_dp_set_link_train(struct intel_dp *intel_dp,
1722 uint32_t dp_reg_value,
1723 uint8_t dp_train_pat)
1725 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1726 struct drm_device *dev = intel_dig_port->base.base.dev;
1727 struct drm_i915_private *dev_priv = dev->dev_private;
1728 enum port port = intel_dig_port->port;
1732 if (IS_HASWELL(dev)) {
1733 temp = I915_READ(DP_TP_CTL(port));
1735 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1736 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1738 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1740 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1741 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1742 case DP_TRAINING_PATTERN_DISABLE:
1743 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1744 I915_WRITE(DP_TP_CTL(port), temp);
1746 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1747 DP_TP_STATUS_IDLE_DONE), 1))
1748 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1750 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1751 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1754 case DP_TRAINING_PATTERN_1:
1755 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1757 case DP_TRAINING_PATTERN_2:
1758 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1760 case DP_TRAINING_PATTERN_3:
1761 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1764 I915_WRITE(DP_TP_CTL(port), temp);
1766 } else if (HAS_PCH_CPT(dev) &&
1767 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1768 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1770 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1771 case DP_TRAINING_PATTERN_DISABLE:
1772 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1774 case DP_TRAINING_PATTERN_1:
1775 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1777 case DP_TRAINING_PATTERN_2:
1778 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1780 case DP_TRAINING_PATTERN_3:
1781 DRM_ERROR("DP training pattern 3 not supported\n");
1782 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1787 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1789 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1790 case DP_TRAINING_PATTERN_DISABLE:
1791 dp_reg_value |= DP_LINK_TRAIN_OFF;
1793 case DP_TRAINING_PATTERN_1:
1794 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1796 case DP_TRAINING_PATTERN_2:
1797 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1799 case DP_TRAINING_PATTERN_3:
1800 DRM_ERROR("DP training pattern 3 not supported\n");
1801 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1806 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1807 POSTING_READ(intel_dp->output_reg);
1809 intel_dp_aux_native_write_1(intel_dp,
1810 DP_TRAINING_PATTERN_SET,
1813 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1814 DP_TRAINING_PATTERN_DISABLE) {
1815 ret = intel_dp_aux_native_write(intel_dp,
1816 DP_TRAINING_LANE0_SET,
1817 intel_dp->train_set,
1818 intel_dp->lane_count);
1819 if (ret != intel_dp->lane_count)
1826 /* Enable corresponding port and start training pattern 1 */
1828 intel_dp_start_link_train(struct intel_dp *intel_dp)
1830 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1831 struct drm_device *dev = encoder->dev;
1834 bool clock_recovery = false;
1835 int voltage_tries, loop_tries;
1836 uint32_t DP = intel_dp->DP;
1839 intel_ddi_prepare_link_retrain(encoder);
1841 /* Write the link configuration data */
1842 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1843 intel_dp->link_configuration,
1844 DP_LINK_CONFIGURATION_SIZE);
1848 memset(intel_dp->train_set, 0, 4);
1852 clock_recovery = false;
1854 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1855 uint8_t link_status[DP_LINK_STATUS_SIZE];
1856 uint32_t signal_levels;
1858 if (IS_HASWELL(dev)) {
1859 signal_levels = intel_dp_signal_levels_hsw(
1860 intel_dp->train_set[0]);
1861 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1862 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1863 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1864 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1865 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1866 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1867 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1869 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1870 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1872 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1875 /* Set training pattern 1 */
1876 if (!intel_dp_set_link_train(intel_dp, DP,
1877 DP_TRAINING_PATTERN_1 |
1878 DP_LINK_SCRAMBLING_DISABLE))
1881 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1882 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1883 DRM_ERROR("failed to get link status\n");
1887 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1888 DRM_DEBUG_KMS("clock recovery OK\n");
1889 clock_recovery = true;
1893 /* Check to see if we've tried the max voltage */
1894 for (i = 0; i < intel_dp->lane_count; i++)
1895 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1897 if (i == intel_dp->lane_count && voltage_tries == 5) {
1899 if (loop_tries == 5) {
1900 DRM_DEBUG_KMS("too many full retries, give up\n");
1903 memset(intel_dp->train_set, 0, 4);
1908 /* Check to see if we've tried the same voltage 5 times */
1909 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1911 if (voltage_tries == 5) {
1912 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1917 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1919 /* Compute new intel_dp->train_set as requested by target */
1920 intel_get_adjust_train(intel_dp, link_status);
1927 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1929 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1930 bool channel_eq = false;
1931 int tries, cr_tries;
1932 uint32_t DP = intel_dp->DP;
1934 /* channel equalization */
1939 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1940 uint32_t signal_levels;
1941 uint8_t link_status[DP_LINK_STATUS_SIZE];
1944 DRM_ERROR("failed to train DP, aborting\n");
1945 intel_dp_link_down(intel_dp);
1949 if (IS_HASWELL(dev)) {
1950 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1951 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1952 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1953 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1954 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1955 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1956 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1957 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1959 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1960 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1963 /* channel eq pattern */
1964 if (!intel_dp_set_link_train(intel_dp, DP,
1965 DP_TRAINING_PATTERN_2 |
1966 DP_LINK_SCRAMBLING_DISABLE))
1969 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1970 if (!intel_dp_get_link_status(intel_dp, link_status))
1973 /* Make sure clock is still ok */
1974 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1975 intel_dp_start_link_train(intel_dp);
1980 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1985 /* Try 5 times, then try clock recovery if that fails */
1987 intel_dp_link_down(intel_dp);
1988 intel_dp_start_link_train(intel_dp);
1994 /* Compute new intel_dp->train_set as requested by target */
1995 intel_get_adjust_train(intel_dp, link_status);
2000 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2002 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
2006 intel_dp_link_down(struct intel_dp *intel_dp)
2008 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2009 struct drm_device *dev = intel_dig_port->base.base.dev;
2010 struct drm_i915_private *dev_priv = dev->dev_private;
2011 struct intel_crtc *intel_crtc =
2012 to_intel_crtc(intel_dig_port->base.base.crtc);
2013 uint32_t DP = intel_dp->DP;
2016 * DDI code has a strict mode set sequence and we should try to respect
2017 * it, otherwise we might hang the machine in many different ways. So we
2018 * really should be disabling the port only on a complete crtc_disable
2019 * sequence. This function is just called under two conditions on DDI
2021 * - Link train failed while doing crtc_enable, and on this case we
2022 * really should respect the mode set sequence and wait for a
2024 * - Someone turned the monitor off and intel_dp_check_link_status
2025 * called us. We don't need to disable the whole port on this case, so
2026 * when someone turns the monitor on again,
2027 * intel_ddi_prepare_link_retrain will take care of redoing the link
2033 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2036 DRM_DEBUG_KMS("\n");
2038 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2039 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2040 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2042 DP &= ~DP_LINK_TRAIN_MASK;
2043 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2045 POSTING_READ(intel_dp->output_reg);
2047 /* We don't really know why we're doing this */
2048 intel_wait_for_vblank(dev, intel_crtc->pipe);
2050 if (HAS_PCH_IBX(dev) &&
2051 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2052 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2054 /* Hardware workaround: leaving our transcoder select
2055 * set to transcoder B while it's off will prevent the
2056 * corresponding HDMI output on transcoder A.
2058 * Combine this with another hardware workaround:
2059 * transcoder select bit can only be cleared while the
2062 DP &= ~DP_PIPEB_SELECT;
2063 I915_WRITE(intel_dp->output_reg, DP);
2065 /* Changes to enable or select take place the vblank
2066 * after being written.
2068 if (WARN_ON(crtc == NULL)) {
2069 /* We should never try to disable a port without a crtc
2070 * attached. For paranoia keep the code around for a
2072 POSTING_READ(intel_dp->output_reg);
2075 intel_wait_for_vblank(dev, intel_crtc->pipe);
2078 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2079 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2080 POSTING_READ(intel_dp->output_reg);
2081 msleep(intel_dp->panel_power_down_delay);
2085 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2087 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2088 sizeof(intel_dp->dpcd)) == 0)
2089 return false; /* aux transfer failed */
2091 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2092 return false; /* DPCD not present */
2094 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2095 DP_DWN_STRM_PORT_PRESENT))
2096 return true; /* native DP sink */
2098 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2099 return true; /* no per-port downstream info */
2101 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2102 intel_dp->downstream_ports,
2103 DP_MAX_DOWNSTREAM_PORTS) == 0)
2104 return false; /* downstream port status fetch failed */
2110 intel_dp_probe_oui(struct intel_dp *intel_dp)
2114 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2117 ironlake_edp_panel_vdd_on(intel_dp);
2119 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2120 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2121 buf[0], buf[1], buf[2]);
2123 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2124 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2125 buf[0], buf[1], buf[2]);
2127 ironlake_edp_panel_vdd_off(intel_dp, false);
2131 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2135 ret = intel_dp_aux_native_read_retry(intel_dp,
2136 DP_DEVICE_SERVICE_IRQ_VECTOR,
2137 sink_irq_vector, 1);
2145 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2147 /* NAK by default */
2148 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2152 * According to DP spec
2155 * 2. Configure link according to Receiver Capabilities
2156 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2157 * 4. Check link status on receipt of hot-plug interrupt
2161 intel_dp_check_link_status(struct intel_dp *intel_dp)
2163 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2165 u8 link_status[DP_LINK_STATUS_SIZE];
2167 if (!intel_encoder->connectors_active)
2170 if (WARN_ON(!intel_encoder->base.crtc))
2173 /* Try to read receiver status if the link appears to be up */
2174 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2175 intel_dp_link_down(intel_dp);
2179 /* Now read the DPCD to see if it's actually running */
2180 if (!intel_dp_get_dpcd(intel_dp)) {
2181 intel_dp_link_down(intel_dp);
2185 /* Try to read the source of the interrupt */
2186 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2187 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2188 /* Clear interrupt source */
2189 intel_dp_aux_native_write_1(intel_dp,
2190 DP_DEVICE_SERVICE_IRQ_VECTOR,
2193 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2194 intel_dp_handle_test_request(intel_dp);
2195 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2196 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2199 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2200 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2201 drm_get_encoder_name(&intel_encoder->base));
2202 intel_dp_start_link_train(intel_dp);
2203 intel_dp_complete_link_train(intel_dp);
2207 /* XXX this is probably wrong for multiple downstream ports */
2208 static enum drm_connector_status
2209 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2211 uint8_t *dpcd = intel_dp->dpcd;
2215 if (!intel_dp_get_dpcd(intel_dp))
2216 return connector_status_disconnected;
2218 /* if there's no downstream port, we're done */
2219 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2220 return connector_status_connected;
2222 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2223 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2226 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2228 return connector_status_unknown;
2229 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2230 : connector_status_disconnected;
2233 /* If no HPD, poke DDC gently */
2234 if (drm_probe_ddc(&intel_dp->adapter))
2235 return connector_status_connected;
2237 /* Well we tried, say unknown for unreliable port types */
2238 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2239 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2240 return connector_status_unknown;
2242 /* Anything else is out of spec, warn and ignore */
2243 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2244 return connector_status_disconnected;
2247 static enum drm_connector_status
2248 ironlake_dp_detect(struct intel_dp *intel_dp)
2250 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2251 struct drm_i915_private *dev_priv = dev->dev_private;
2252 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2253 enum drm_connector_status status;
2255 /* Can't disconnect eDP, but you can close the lid... */
2256 if (is_edp(intel_dp)) {
2257 status = intel_panel_detect(dev);
2258 if (status == connector_status_unknown)
2259 status = connector_status_connected;
2263 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2264 return connector_status_disconnected;
2266 return intel_dp_detect_dpcd(intel_dp);
2269 static enum drm_connector_status
2270 g4x_dp_detect(struct intel_dp *intel_dp)
2272 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2273 struct drm_i915_private *dev_priv = dev->dev_private;
2276 switch (intel_dp->output_reg) {
2278 bit = DPB_HOTPLUG_LIVE_STATUS;
2281 bit = DPC_HOTPLUG_LIVE_STATUS;
2284 bit = DPD_HOTPLUG_LIVE_STATUS;
2287 return connector_status_unknown;
2290 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2291 return connector_status_disconnected;
2293 return intel_dp_detect_dpcd(intel_dp);
2296 static struct edid *
2297 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2299 struct intel_connector *intel_connector = to_intel_connector(connector);
2301 /* use cached edid if we have one */
2302 if (intel_connector->edid) {
2307 if (IS_ERR(intel_connector->edid))
2310 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2311 edid = kmalloc(size, GFP_KERNEL);
2315 memcpy(edid, intel_connector->edid, size);
2319 return drm_get_edid(connector, adapter);
2323 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2325 struct intel_connector *intel_connector = to_intel_connector(connector);
2327 /* use cached edid if we have one */
2328 if (intel_connector->edid) {
2330 if (IS_ERR(intel_connector->edid))
2333 return intel_connector_update_modes(connector,
2334 intel_connector->edid);
2337 return intel_ddc_get_modes(connector, adapter);
2342 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2344 * \return true if DP port is connected.
2345 * \return false if DP port is disconnected.
2347 static enum drm_connector_status
2348 intel_dp_detect(struct drm_connector *connector, bool force)
2350 struct intel_dp *intel_dp = intel_attached_dp(connector);
2351 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2352 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2353 struct drm_device *dev = connector->dev;
2354 enum drm_connector_status status;
2355 struct edid *edid = NULL;
2356 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2358 intel_dp->has_audio = false;
2360 if (HAS_PCH_SPLIT(dev))
2361 status = ironlake_dp_detect(intel_dp);
2363 status = g4x_dp_detect(intel_dp);
2365 hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2366 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2367 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2369 if (status != connector_status_connected)
2372 intel_dp_probe_oui(intel_dp);
2374 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2375 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2377 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2379 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2384 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2385 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2386 return connector_status_connected;
2389 static int intel_dp_get_modes(struct drm_connector *connector)
2391 struct intel_dp *intel_dp = intel_attached_dp(connector);
2392 struct intel_connector *intel_connector = to_intel_connector(connector);
2393 struct drm_device *dev = connector->dev;
2396 /* We should parse the EDID data and find out if it has an audio sink
2399 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2403 /* if eDP has no EDID, fall back to fixed mode */
2404 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2405 struct drm_display_mode *mode;
2406 mode = drm_mode_duplicate(dev,
2407 intel_connector->panel.fixed_mode);
2409 drm_mode_probed_add(connector, mode);
2417 intel_dp_detect_audio(struct drm_connector *connector)
2419 struct intel_dp *intel_dp = intel_attached_dp(connector);
2421 bool has_audio = false;
2423 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2425 has_audio = drm_detect_monitor_audio(edid);
2433 intel_dp_set_property(struct drm_connector *connector,
2434 struct drm_property *property,
2437 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2438 struct intel_connector *intel_connector = to_intel_connector(connector);
2439 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2440 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2443 ret = drm_object_property_set_value(&connector->base, property, val);
2447 if (property == dev_priv->force_audio_property) {
2451 if (i == intel_dp->force_audio)
2454 intel_dp->force_audio = i;
2456 if (i == HDMI_AUDIO_AUTO)
2457 has_audio = intel_dp_detect_audio(connector);
2459 has_audio = (i == HDMI_AUDIO_ON);
2461 if (has_audio == intel_dp->has_audio)
2464 intel_dp->has_audio = has_audio;
2468 if (property == dev_priv->broadcast_rgb_property) {
2469 if (val == !!intel_dp->color_range)
2472 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2476 if (is_edp(intel_dp) &&
2477 property == connector->dev->mode_config.scaling_mode_property) {
2478 if (val == DRM_MODE_SCALE_NONE) {
2479 DRM_DEBUG_KMS("no scaling not supported\n");
2483 if (intel_connector->panel.fitting_mode == val) {
2484 /* the eDP scaling property is not changed */
2487 intel_connector->panel.fitting_mode = val;
2495 if (intel_encoder->base.crtc) {
2496 struct drm_crtc *crtc = intel_encoder->base.crtc;
2497 intel_set_mode(crtc, &crtc->mode,
2498 crtc->x, crtc->y, crtc->fb);
2505 intel_dp_destroy(struct drm_connector *connector)
2507 struct drm_device *dev = connector->dev;
2508 struct intel_dp *intel_dp = intel_attached_dp(connector);
2509 struct intel_connector *intel_connector = to_intel_connector(connector);
2511 if (!IS_ERR_OR_NULL(intel_connector->edid))
2512 kfree(intel_connector->edid);
2514 if (is_edp(intel_dp)) {
2515 intel_panel_destroy_backlight(dev);
2516 intel_panel_fini(&intel_connector->panel);
2519 drm_sysfs_connector_remove(connector);
2520 drm_connector_cleanup(connector);
2524 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2526 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2527 struct intel_dp *intel_dp = &intel_dig_port->dp;
2529 i2c_del_adapter(&intel_dp->adapter);
2530 drm_encoder_cleanup(encoder);
2531 if (is_edp(intel_dp)) {
2532 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2533 ironlake_panel_vdd_off_sync(intel_dp);
2535 kfree(intel_dig_port);
2538 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2539 .mode_fixup = intel_dp_mode_fixup,
2540 .mode_set = intel_dp_mode_set,
2541 .disable = intel_encoder_noop,
2544 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2545 .dpms = intel_connector_dpms,
2546 .detect = intel_dp_detect,
2547 .fill_modes = drm_helper_probe_single_connector_modes,
2548 .set_property = intel_dp_set_property,
2549 .destroy = intel_dp_destroy,
2552 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2553 .get_modes = intel_dp_get_modes,
2554 .mode_valid = intel_dp_mode_valid,
2555 .best_encoder = intel_best_encoder,
2558 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2559 .destroy = intel_dp_encoder_destroy,
2563 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2565 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2567 intel_dp_check_link_status(intel_dp);
2570 /* Return which DP Port should be selected for Transcoder DP control */
2572 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2574 struct drm_device *dev = crtc->dev;
2575 struct intel_encoder *intel_encoder;
2576 struct intel_dp *intel_dp;
2578 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2579 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2581 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2582 intel_encoder->type == INTEL_OUTPUT_EDP)
2583 return intel_dp->output_reg;
2589 /* check the VBT to see whether the eDP is on DP-D port */
2590 bool intel_dpd_is_edp(struct drm_device *dev)
2592 struct drm_i915_private *dev_priv = dev->dev_private;
2593 struct child_device_config *p_child;
2596 if (!dev_priv->child_dev_num)
2599 for (i = 0; i < dev_priv->child_dev_num; i++) {
2600 p_child = dev_priv->child_dev + i;
2602 if (p_child->dvo_port == PORT_IDPD &&
2603 p_child->device_type == DEVICE_TYPE_eDP)
2610 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2612 struct intel_connector *intel_connector = to_intel_connector(connector);
2614 intel_attach_force_audio_property(connector);
2615 intel_attach_broadcast_rgb_property(connector);
2617 if (is_edp(intel_dp)) {
2618 drm_mode_create_scaling_mode_property(connector->dev);
2619 drm_connector_attach_property(
2621 connector->dev->mode_config.scaling_mode_property,
2622 DRM_MODE_SCALE_ASPECT);
2623 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2628 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2629 struct intel_dp *intel_dp)
2631 struct drm_i915_private *dev_priv = dev->dev_private;
2632 struct edp_power_seq cur, vbt, spec, final;
2633 u32 pp_on, pp_off, pp_div, pp;
2635 /* Workaround: Need to write PP_CONTROL with the unlock key as
2636 * the very first thing. */
2637 pp = ironlake_get_pp_control(dev_priv);
2638 I915_WRITE(PCH_PP_CONTROL, pp);
2640 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2641 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2642 pp_div = I915_READ(PCH_PP_DIVISOR);
2644 /* Pull timing values out of registers */
2645 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2646 PANEL_POWER_UP_DELAY_SHIFT;
2648 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2649 PANEL_LIGHT_ON_DELAY_SHIFT;
2651 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2652 PANEL_LIGHT_OFF_DELAY_SHIFT;
2654 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2655 PANEL_POWER_DOWN_DELAY_SHIFT;
2657 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2658 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2660 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2661 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2663 vbt = dev_priv->edp.pps;
2665 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2666 * our hw here, which are all in 100usec. */
2667 spec.t1_t3 = 210 * 10;
2668 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2669 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2670 spec.t10 = 500 * 10;
2671 /* This one is special and actually in units of 100ms, but zero
2672 * based in the hw (so we need to add 100 ms). But the sw vbt
2673 * table multiplies it with 1000 to make it in units of 100usec,
2675 spec.t11_t12 = (510 + 100) * 10;
2677 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2678 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2680 /* Use the max of the register settings and vbt. If both are
2681 * unset, fall back to the spec limits. */
2682 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2684 max(cur.field, vbt.field))
2685 assign_final(t1_t3);
2689 assign_final(t11_t12);
2692 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2693 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2694 intel_dp->backlight_on_delay = get_delay(t8);
2695 intel_dp->backlight_off_delay = get_delay(t9);
2696 intel_dp->panel_power_down_delay = get_delay(t10);
2697 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2700 /* And finally store the new values in the power sequencer. */
2701 pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2702 (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2703 pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2704 (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2705 /* Compute the divisor for the pp clock, simply match the Bspec
2707 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2708 << PP_REFERENCE_DIVIDER_SHIFT;
2709 pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
2710 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2712 /* Haswell doesn't have any port selection bits for the panel
2713 * power sequencer any more. */
2714 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2715 if (is_cpu_edp(intel_dp))
2716 pp_on |= PANEL_POWER_PORT_DP_A;
2718 pp_on |= PANEL_POWER_PORT_DP_D;
2721 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2722 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2723 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2726 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2727 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2728 intel_dp->panel_power_cycle_delay);
2730 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2731 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2733 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2734 I915_READ(PCH_PP_ON_DELAYS),
2735 I915_READ(PCH_PP_OFF_DELAYS),
2736 I915_READ(PCH_PP_DIVISOR));
2740 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2741 struct intel_connector *intel_connector)
2743 struct drm_connector *connector = &intel_connector->base;
2744 struct intel_dp *intel_dp = &intel_dig_port->dp;
2745 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2746 struct drm_device *dev = intel_encoder->base.dev;
2747 struct drm_i915_private *dev_priv = dev->dev_private;
2748 struct drm_display_mode *fixed_mode = NULL;
2749 enum port port = intel_dig_port->port;
2750 const char *name = NULL;
2753 /* Preserve the current hw state. */
2754 intel_dp->DP = I915_READ(intel_dp->output_reg);
2755 intel_dp->attached_connector = intel_connector;
2757 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2758 if (intel_dpd_is_edp(dev))
2759 intel_dp->is_pch_edp = true;
2762 * FIXME : We need to initialize built-in panels before external panels.
2763 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2765 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2766 type = DRM_MODE_CONNECTOR_eDP;
2767 intel_encoder->type = INTEL_OUTPUT_EDP;
2768 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
2769 type = DRM_MODE_CONNECTOR_eDP;
2770 intel_encoder->type = INTEL_OUTPUT_EDP;
2772 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2773 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2776 type = DRM_MODE_CONNECTOR_DisplayPort;
2779 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2780 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2782 connector->polled = DRM_CONNECTOR_POLL_HPD;
2783 connector->interlace_allowed = true;
2784 connector->doublescan_allowed = 0;
2786 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2787 ironlake_panel_vdd_work);
2789 intel_connector_attach_encoder(intel_connector, intel_encoder);
2790 drm_sysfs_connector_add(connector);
2793 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2795 intel_connector->get_hw_state = intel_connector_get_hw_state;
2798 /* Set up the DDC bus. */
2804 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2808 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2812 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2816 WARN(1, "Invalid port %c\n", port_name(port));
2820 if (is_edp(intel_dp))
2821 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2823 intel_dp_i2c_init(intel_dp, intel_connector, name);
2825 /* Cache DPCD and EDID for edp. */
2826 if (is_edp(intel_dp)) {
2828 struct drm_display_mode *scan;
2831 ironlake_edp_panel_vdd_on(intel_dp);
2832 ret = intel_dp_get_dpcd(intel_dp);
2833 ironlake_edp_panel_vdd_off(intel_dp, false);
2836 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2837 dev_priv->no_aux_handshake =
2838 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2839 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2841 /* if this fails, presume the device is a ghost */
2842 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2843 intel_dp_encoder_destroy(&intel_encoder->base);
2844 intel_dp_destroy(connector);
2848 ironlake_edp_panel_vdd_on(intel_dp);
2849 edid = drm_get_edid(connector, &intel_dp->adapter);
2851 if (drm_add_edid_modes(connector, edid)) {
2852 drm_mode_connector_update_edid_property(connector, edid);
2853 drm_edid_to_eld(connector, edid);
2856 edid = ERR_PTR(-EINVAL);
2859 edid = ERR_PTR(-ENOENT);
2861 intel_connector->edid = edid;
2863 /* prefer fixed mode from EDID if available */
2864 list_for_each_entry(scan, &connector->probed_modes, head) {
2865 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2866 fixed_mode = drm_mode_duplicate(dev, scan);
2871 /* fallback to VBT if available for eDP */
2872 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2873 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2875 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2878 ironlake_edp_panel_vdd_off(intel_dp, false);
2881 if (is_edp(intel_dp)) {
2882 intel_panel_init(&intel_connector->panel, fixed_mode);
2883 intel_panel_setup_backlight(connector);
2886 intel_dp_add_properties(intel_dp, connector);
2888 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2889 * 0xd. Failure to do so will result in spurious interrupts being
2890 * generated on the port when a cable is not attached.
2892 if (IS_G4X(dev) && !IS_GM45(dev)) {
2893 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2894 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2899 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2901 struct intel_digital_port *intel_dig_port;
2902 struct intel_encoder *intel_encoder;
2903 struct drm_encoder *encoder;
2904 struct intel_connector *intel_connector;
2906 intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2907 if (!intel_dig_port)
2910 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2911 if (!intel_connector) {
2912 kfree(intel_dig_port);
2916 intel_encoder = &intel_dig_port->base;
2917 encoder = &intel_encoder->base;
2919 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2920 DRM_MODE_ENCODER_TMDS);
2921 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2923 intel_encoder->enable = intel_enable_dp;
2924 intel_encoder->pre_enable = intel_pre_enable_dp;
2925 intel_encoder->disable = intel_disable_dp;
2926 intel_encoder->post_disable = intel_post_disable_dp;
2927 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2929 intel_dig_port->port = port;
2930 intel_dig_port->dp.output_reg = output_reg;
2932 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2933 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2934 intel_encoder->cloneable = false;
2935 intel_encoder->hot_plug = intel_dp_hot_plug;
2937 intel_dp_init_connector(intel_dig_port, intel_connector);