drivers/gpu/drm/radeon/radeon_asic.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28
  29 #include <linux/console.h>
  30 #include <drm/drmP.h>
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/radeon_drm.h>
  33 #include <linux/vgaarb.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include "radeon_reg.h"
  36 #include "radeon.h"
  37 #include "radeon_asic.h"
  38 #include "atom.h"
  39
  40 /*
  41  * Registers accessors functions.
  42  */
  43 /**
  44  * radeon_invalid_rreg - dummy reg read function
  45  *
  46  * @rdev: radeon device pointer
  47  * @reg: offset of register
  48  *
  49  * Dummy register read function.  Used for register blocks
  50  * that certain asics don't have (all asics).
  51  * Returns the value in the register.
  52  */
  53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
  54 {
  55         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
  56         BUG_ON(1);
  57         return 0;
  58 }
  59
  60 /**
  61  * radeon_invalid_wreg - dummy reg write function
  62  *
  63  * @rdev: radeon device pointer
  64  * @reg: offset of register
  65  * @v: value to write to the register
  66  *
  67  * Dummy register read function.  Used for register blocks
  68  * that certain asics don't have (all asics).
  69  */
  70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  71 {
  72         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
  73                   reg, v);
  74         BUG_ON(1);
  75 }
  76
  77 /**
  78  * radeon_register_accessor_init - sets up the register accessor callbacks
  79  *
  80  * @rdev: radeon device pointer
  81  *
  82  * Sets up the register accessor callbacks for various register
  83  * apertures.  Not all asics have all apertures (all asics).
  84  */
  85 static void radeon_register_accessor_init(struct radeon_device *rdev)
  86 {
  87         rdev->mc_rreg = &radeon_invalid_rreg;
  88         rdev->mc_wreg = &radeon_invalid_wreg;
  89         rdev->pll_rreg = &radeon_invalid_rreg;
  90         rdev->pll_wreg = &radeon_invalid_wreg;
  91         rdev->pciep_rreg = &radeon_invalid_rreg;
  92         rdev->pciep_wreg = &radeon_invalid_wreg;
  93
  94         /* Don't change order as we are overridding accessor. */
  95         if (rdev->family < CHIP_RV515) {
  96                 rdev->pcie_reg_mask = 0xff;
  97         } else {
  98                 rdev->pcie_reg_mask = 0x7ff;
  99         }
 100         /* FIXME: not sure here */
 101         if (rdev->family <= CHIP_R580) {
 102                 rdev->pll_rreg = &r100_pll_rreg;
 103                 rdev->pll_wreg = &r100_pll_wreg;
 104         }
 105         if (rdev->family >= CHIP_R420) {
 106                 rdev->mc_rreg = &r420_mc_rreg;
 107                 rdev->mc_wreg = &r420_mc_wreg;
 108         }
 109         if (rdev->family >= CHIP_RV515) {
 110                 rdev->mc_rreg = &rv515_mc_rreg;
 111                 rdev->mc_wreg = &rv515_mc_wreg;
 112         }
 113         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
 114                 rdev->mc_rreg = &rs400_mc_rreg;
 115                 rdev->mc_wreg = &rs400_mc_wreg;
 116         }
 117         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
 118                 rdev->mc_rreg = &rs690_mc_rreg;
 119                 rdev->mc_wreg = &rs690_mc_wreg;
 120         }
 121         if (rdev->family == CHIP_RS600) {
 122                 rdev->mc_rreg = &rs600_mc_rreg;
 123                 rdev->mc_wreg = &rs600_mc_wreg;
 124         }
 125         if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
 126                 rdev->mc_rreg = &rs780_mc_rreg;
 127                 rdev->mc_wreg = &rs780_mc_wreg;
 128         }
 129
 130         if (rdev->family >= CHIP_BONAIRE) {
 131                 rdev->pciep_rreg = &cik_pciep_rreg;
 132                 rdev->pciep_wreg = &cik_pciep_wreg;
 133         } else if (rdev->family >= CHIP_R600) {
 134                 rdev->pciep_rreg = &r600_pciep_rreg;
 135                 rdev->pciep_wreg = &r600_pciep_wreg;
 136         }
 137 }
 138
 139
 140 /* helper to disable agp */
 141 /**
 142  * radeon_agp_disable - AGP disable helper function
 143  *
 144  * @rdev: radeon device pointer
 145  *
 146  * Removes AGP flags and changes the gart callbacks on AGP
 147  * cards when using the internal gart rather than AGP (all asics).
 148  */
 149 void radeon_agp_disable(struct radeon_device *rdev)
 150 {
 151         rdev->flags &= ~RADEON_IS_AGP;
 152         if (rdev->family >= CHIP_R600) {
 153                 DRM_INFO("Forcing AGP to PCIE mode\n");
 154                 rdev->flags |= RADEON_IS_PCIE;
 155         } else if (rdev->family >= CHIP_RV515 ||
 156                         rdev->family == CHIP_RV380 ||
 157                         rdev->family == CHIP_RV410 ||
 158                         rdev->family == CHIP_R423) {
 159                 DRM_INFO("Forcing AGP to PCIE mode\n");
 160                 rdev->flags |= RADEON_IS_PCIE;
 161                 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
 162                 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
 163         } else {
 164                 DRM_INFO("Forcing AGP to PCI mode\n");
 165                 rdev->flags |= RADEON_IS_PCI;
 166                 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
 167                 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
 168         }
 169         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
 170 }
 171
 172 /*
 173  * ASIC
 174  */
 175 static struct radeon_asic r100_asic = {
 176         .init = &r100_init,
 177         .fini = &r100_fini,
 178         .suspend = &r100_suspend,
 179         .resume = &r100_resume,
 180         .vga_set_state = &r100_vga_set_state,
 181         .asic_reset = &r100_asic_reset,
 182         .ioctl_wait_idle = NULL,
 183         .gui_idle = &r100_gui_idle,
 184         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 185         .gart = {
 186                 .tlb_flush = &r100_pci_gart_tlb_flush,
 187                 .set_page = &r100_pci_gart_set_page,
 188         },
 189         .ring = {
 190                 [RADEON_RING_TYPE_GFX_INDEX] = {
 191                         .ib_execute = &r100_ring_ib_execute,
 192                         .emit_fence = &r100_fence_ring_emit,
 193                         .emit_semaphore = &r100_semaphore_ring_emit,
 194                         .cs_parse = &r100_cs_parse,
 195                         .ring_start = &r100_ring_start,
 196                         .ring_test = &r100_ring_test,
 197                         .ib_test = &r100_ib_test,
 198                         .is_lockup = &r100_gpu_is_lockup,
 199                         .get_rptr = &radeon_ring_generic_get_rptr,
 200                         .get_wptr = &radeon_ring_generic_get_wptr,
 201                         .set_wptr = &radeon_ring_generic_set_wptr,
 202                 }
 203         },
 204         .irq = {
 205                 .set = &r100_irq_set,
 206                 .process = &r100_irq_process,
 207         },
 208         .display = {
 209                 .bandwidth_update = &r100_bandwidth_update,
 210                 .get_vblank_counter = &r100_get_vblank_counter,
 211                 .wait_for_vblank = &r100_wait_for_vblank,
 212                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 213                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 214         },
 215         .copy = {
 216                 .blit = &r100_copy_blit,
 217                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 218                 .dma = NULL,
 219                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 220                 .copy = &r100_copy_blit,
 221                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 222         },
 223         .surface = {
 224                 .set_reg = r100_set_surface_reg,
 225                 .clear_reg = r100_clear_surface_reg,
 226         },
 227         .hpd = {
 228                 .init = &r100_hpd_init,
 229                 .fini = &r100_hpd_fini,
 230                 .sense = &r100_hpd_sense,
 231                 .set_polarity = &r100_hpd_set_polarity,
 232         },
 233         .pm = {
 234                 .misc = &r100_pm_misc,
 235                 .prepare = &r100_pm_prepare,
 236                 .finish = &r100_pm_finish,
 237                 .init_profile = &r100_pm_init_profile,
 238                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 239                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 240                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 241                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 242                 .set_memory_clock = NULL,
 243                 .get_pcie_lanes = NULL,
 244                 .set_pcie_lanes = NULL,
 245                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 246         },
 247         .pflip = {
 248                 .pre_page_flip = &r100_pre_page_flip,
 249                 .page_flip = &r100_page_flip,
 250                 .post_page_flip = &r100_post_page_flip,
 251         },
 252 };
 253
 254 static struct radeon_asic r200_asic = {
 255         .init = &r100_init,
 256         .fini = &r100_fini,
 257         .suspend = &r100_suspend,
 258         .resume = &r100_resume,
 259         .vga_set_state = &r100_vga_set_state,
 260         .asic_reset = &r100_asic_reset,
 261         .ioctl_wait_idle = NULL,
 262         .gui_idle = &r100_gui_idle,
 263         .mc_wait_for_idle = &r100_mc_wait_for_idle,
 264         .gart = {
 265                 .tlb_flush = &r100_pci_gart_tlb_flush,
 266                 .set_page = &r100_pci_gart_set_page,
 267         },
 268         .ring = {
 269                 [RADEON_RING_TYPE_GFX_INDEX] = {
 270                         .ib_execute = &r100_ring_ib_execute,
 271                         .emit_fence = &r100_fence_ring_emit,
 272                         .emit_semaphore = &r100_semaphore_ring_emit,
 273                         .cs_parse = &r100_cs_parse,
 274                         .ring_start = &r100_ring_start,
 275                         .ring_test = &r100_ring_test,
 276                         .ib_test = &r100_ib_test,
 277                         .is_lockup = &r100_gpu_is_lockup,
 278                         .get_rptr = &radeon_ring_generic_get_rptr,
 279                         .get_wptr = &radeon_ring_generic_get_wptr,
 280                         .set_wptr = &radeon_ring_generic_set_wptr,
 281                 }
 282         },
 283         .irq = {
 284                 .set = &r100_irq_set,
 285                 .process = &r100_irq_process,
 286         },
 287         .display = {
 288                 .bandwidth_update = &r100_bandwidth_update,
 289                 .get_vblank_counter = &r100_get_vblank_counter,
 290                 .wait_for_vblank = &r100_wait_for_vblank,
 291                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 292                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 293         },
 294         .copy = {
 295                 .blit = &r100_copy_blit,
 296                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 297                 .dma = &r200_copy_dma,
 298                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 299                 .copy = &r100_copy_blit,
 300                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 301         },
 302         .surface = {
 303                 .set_reg = r100_set_surface_reg,
 304                 .clear_reg = r100_clear_surface_reg,
 305         },
 306         .hpd = {
 307                 .init = &r100_hpd_init,
 308                 .fini = &r100_hpd_fini,
 309                 .sense = &r100_hpd_sense,
 310                 .set_polarity = &r100_hpd_set_polarity,
 311         },
 312         .pm = {
 313                 .misc = &r100_pm_misc,
 314                 .prepare = &r100_pm_prepare,
 315                 .finish = &r100_pm_finish,
 316                 .init_profile = &r100_pm_init_profile,
 317                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 318                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 319                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 320                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 321                 .set_memory_clock = NULL,
 322                 .get_pcie_lanes = NULL,
 323                 .set_pcie_lanes = NULL,
 324                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 325         },
 326         .pflip = {
 327                 .pre_page_flip = &r100_pre_page_flip,
 328                 .page_flip = &r100_page_flip,
 329                 .post_page_flip = &r100_post_page_flip,
 330         },
 331 };
 332
 333 static struct radeon_asic r300_asic = {
 334         .init = &r300_init,
 335         .fini = &r300_fini,
 336         .suspend = &r300_suspend,
 337         .resume = &r300_resume,
 338         .vga_set_state = &r100_vga_set_state,
 339         .asic_reset = &r300_asic_reset,
 340         .ioctl_wait_idle = NULL,
 341         .gui_idle = &r100_gui_idle,
 342         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 343         .gart = {
 344                 .tlb_flush = &r100_pci_gart_tlb_flush,
 345                 .set_page = &r100_pci_gart_set_page,
 346         },
 347         .ring = {
 348                 [RADEON_RING_TYPE_GFX_INDEX] = {
 349                         .ib_execute = &r100_ring_ib_execute,
 350                         .emit_fence = &r300_fence_ring_emit,
 351                         .emit_semaphore = &r100_semaphore_ring_emit,
 352                         .cs_parse = &r300_cs_parse,
 353                         .ring_start = &r300_ring_start,
 354                         .ring_test = &r100_ring_test,
 355                         .ib_test = &r100_ib_test,
 356                         .is_lockup = &r100_gpu_is_lockup,
 357                         .get_rptr = &radeon_ring_generic_get_rptr,
 358                         .get_wptr = &radeon_ring_generic_get_wptr,
 359                         .set_wptr = &radeon_ring_generic_set_wptr,
 360                 }
 361         },
 362         .irq = {
 363                 .set = &r100_irq_set,
 364                 .process = &r100_irq_process,
 365         },
 366         .display = {
 367                 .bandwidth_update = &r100_bandwidth_update,
 368                 .get_vblank_counter = &r100_get_vblank_counter,
 369                 .wait_for_vblank = &r100_wait_for_vblank,
 370                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 371                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 372         },
 373         .copy = {
 374                 .blit = &r100_copy_blit,
 375                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 376                 .dma = &r200_copy_dma,
 377                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 378                 .copy = &r100_copy_blit,
 379                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 380         },
 381         .surface = {
 382                 .set_reg = r100_set_surface_reg,
 383                 .clear_reg = r100_clear_surface_reg,
 384         },
 385         .hpd = {
 386                 .init = &r100_hpd_init,
 387                 .fini = &r100_hpd_fini,
 388                 .sense = &r100_hpd_sense,
 389                 .set_polarity = &r100_hpd_set_polarity,
 390         },
 391         .pm = {
 392                 .misc = &r100_pm_misc,
 393                 .prepare = &r100_pm_prepare,
 394                 .finish = &r100_pm_finish,
 395                 .init_profile = &r100_pm_init_profile,
 396                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 397                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 398                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 399                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 400                 .set_memory_clock = NULL,
 401                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 402                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 403                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 404         },
 405         .pflip = {
 406                 .pre_page_flip = &r100_pre_page_flip,
 407                 .page_flip = &r100_page_flip,
 408                 .post_page_flip = &r100_post_page_flip,
 409         },
 410 };
 411
 412 static struct radeon_asic r300_asic_pcie = {
 413         .init = &r300_init,
 414         .fini = &r300_fini,
 415         .suspend = &r300_suspend,
 416         .resume = &r300_resume,
 417         .vga_set_state = &r100_vga_set_state,
 418         .asic_reset = &r300_asic_reset,
 419         .ioctl_wait_idle = NULL,
 420         .gui_idle = &r100_gui_idle,
 421         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 422         .gart = {
 423                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 424                 .set_page = &rv370_pcie_gart_set_page,
 425         },
 426         .ring = {
 427                 [RADEON_RING_TYPE_GFX_INDEX] = {
 428                         .ib_execute = &r100_ring_ib_execute,
 429                         .emit_fence = &r300_fence_ring_emit,
 430                         .emit_semaphore = &r100_semaphore_ring_emit,
 431                         .cs_parse = &r300_cs_parse,
 432                         .ring_start = &r300_ring_start,
 433                         .ring_test = &r100_ring_test,
 434                         .ib_test = &r100_ib_test,
 435                         .is_lockup = &r100_gpu_is_lockup,
 436                         .get_rptr = &radeon_ring_generic_get_rptr,
 437                         .get_wptr = &radeon_ring_generic_get_wptr,
 438                         .set_wptr = &radeon_ring_generic_set_wptr,
 439                 }
 440         },
 441         .irq = {
 442                 .set = &r100_irq_set,
 443                 .process = &r100_irq_process,
 444         },
 445         .display = {
 446                 .bandwidth_update = &r100_bandwidth_update,
 447                 .get_vblank_counter = &r100_get_vblank_counter,
 448                 .wait_for_vblank = &r100_wait_for_vblank,
 449                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 450                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 451         },
 452         .copy = {
 453                 .blit = &r100_copy_blit,
 454                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 455                 .dma = &r200_copy_dma,
 456                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 457                 .copy = &r100_copy_blit,
 458                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 459         },
 460         .surface = {
 461                 .set_reg = r100_set_surface_reg,
 462                 .clear_reg = r100_clear_surface_reg,
 463         },
 464         .hpd = {
 465                 .init = &r100_hpd_init,
 466                 .fini = &r100_hpd_fini,
 467                 .sense = &r100_hpd_sense,
 468                 .set_polarity = &r100_hpd_set_polarity,
 469         },
 470         .pm = {
 471                 .misc = &r100_pm_misc,
 472                 .prepare = &r100_pm_prepare,
 473                 .finish = &r100_pm_finish,
 474                 .init_profile = &r100_pm_init_profile,
 475                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 476                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 477                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 478                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 479                 .set_memory_clock = NULL,
 480                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 481                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 482                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 483         },
 484         .pflip = {
 485                 .pre_page_flip = &r100_pre_page_flip,
 486                 .page_flip = &r100_page_flip,
 487                 .post_page_flip = &r100_post_page_flip,
 488         },
 489 };
 490
 491 static struct radeon_asic r420_asic = {
 492         .init = &r420_init,
 493         .fini = &r420_fini,
 494         .suspend = &r420_suspend,
 495         .resume = &r420_resume,
 496         .vga_set_state = &r100_vga_set_state,
 497         .asic_reset = &r300_asic_reset,
 498         .ioctl_wait_idle = NULL,
 499         .gui_idle = &r100_gui_idle,
 500         .mc_wait_for_idle = &r300_mc_wait_for_idle,
 501         .gart = {
 502                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 503                 .set_page = &rv370_pcie_gart_set_page,
 504         },
 505         .ring = {
 506                 [RADEON_RING_TYPE_GFX_INDEX] = {
 507                         .ib_execute = &r100_ring_ib_execute,
 508                         .emit_fence = &r300_fence_ring_emit,
 509                         .emit_semaphore = &r100_semaphore_ring_emit,
 510                         .cs_parse = &r300_cs_parse,
 511                         .ring_start = &r300_ring_start,
 512                         .ring_test = &r100_ring_test,
 513                         .ib_test = &r100_ib_test,
 514                         .is_lockup = &r100_gpu_is_lockup,
 515                         .get_rptr = &radeon_ring_generic_get_rptr,
 516                         .get_wptr = &radeon_ring_generic_get_wptr,
 517                         .set_wptr = &radeon_ring_generic_set_wptr,
 518                 }
 519         },
 520         .irq = {
 521                 .set = &r100_irq_set,
 522                 .process = &r100_irq_process,
 523         },
 524         .display = {
 525                 .bandwidth_update = &r100_bandwidth_update,
 526                 .get_vblank_counter = &r100_get_vblank_counter,
 527                 .wait_for_vblank = &r100_wait_for_vblank,
 528                 .set_backlight_level = &atombios_set_backlight_level,
 529                 .get_backlight_level = &atombios_get_backlight_level,
 530         },
 531         .copy = {
 532                 .blit = &r100_copy_blit,
 533                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 534                 .dma = &r200_copy_dma,
 535                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 536                 .copy = &r100_copy_blit,
 537                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 538         },
 539         .surface = {
 540                 .set_reg = r100_set_surface_reg,
 541                 .clear_reg = r100_clear_surface_reg,
 542         },
 543         .hpd = {
 544                 .init = &r100_hpd_init,
 545                 .fini = &r100_hpd_fini,
 546                 .sense = &r100_hpd_sense,
 547                 .set_polarity = &r100_hpd_set_polarity,
 548         },
 549         .pm = {
 550                 .misc = &r100_pm_misc,
 551                 .prepare = &r100_pm_prepare,
 552                 .finish = &r100_pm_finish,
 553                 .init_profile = &r420_pm_init_profile,
 554                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 555                 .get_engine_clock = &radeon_atom_get_engine_clock,
 556                 .set_engine_clock = &radeon_atom_set_engine_clock,
 557                 .get_memory_clock = &radeon_atom_get_memory_clock,
 558                 .set_memory_clock = &radeon_atom_set_memory_clock,
 559                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 560                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 561                 .set_clock_gating = &radeon_atom_set_clock_gating,
 562         },
 563         .pflip = {
 564                 .pre_page_flip = &r100_pre_page_flip,
 565                 .page_flip = &r100_page_flip,
 566                 .post_page_flip = &r100_post_page_flip,
 567         },
 568 };
 569
 570 static struct radeon_asic rs400_asic = {
 571         .init = &rs400_init,
 572         .fini = &rs400_fini,
 573         .suspend = &rs400_suspend,
 574         .resume = &rs400_resume,
 575         .vga_set_state = &r100_vga_set_state,
 576         .asic_reset = &r300_asic_reset,
 577         .ioctl_wait_idle = NULL,
 578         .gui_idle = &r100_gui_idle,
 579         .mc_wait_for_idle = &rs400_mc_wait_for_idle,
 580         .gart = {
 581                 .tlb_flush = &rs400_gart_tlb_flush,
 582                 .set_page = &rs400_gart_set_page,
 583         },
 584         .ring = {
 585                 [RADEON_RING_TYPE_GFX_INDEX] = {
 586                         .ib_execute = &r100_ring_ib_execute,
 587                         .emit_fence = &r300_fence_ring_emit,
 588                         .emit_semaphore = &r100_semaphore_ring_emit,
 589                         .cs_parse = &r300_cs_parse,
 590                         .ring_start = &r300_ring_start,
 591                         .ring_test = &r100_ring_test,
 592                         .ib_test = &r100_ib_test,
 593                         .is_lockup = &r100_gpu_is_lockup,
 594                         .get_rptr = &radeon_ring_generic_get_rptr,
 595                         .get_wptr = &radeon_ring_generic_get_wptr,
 596                         .set_wptr = &radeon_ring_generic_set_wptr,
 597                 }
 598         },
 599         .irq = {
 600                 .set = &r100_irq_set,
 601                 .process = &r100_irq_process,
 602         },
 603         .display = {
 604                 .bandwidth_update = &r100_bandwidth_update,
 605                 .get_vblank_counter = &r100_get_vblank_counter,
 606                 .wait_for_vblank = &r100_wait_for_vblank,
 607                 .set_backlight_level = &radeon_legacy_set_backlight_level,
 608                 .get_backlight_level = &radeon_legacy_get_backlight_level,
 609         },
 610         .copy = {
 611                 .blit = &r100_copy_blit,
 612                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 613                 .dma = &r200_copy_dma,
 614                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 615                 .copy = &r100_copy_blit,
 616                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 617         },
 618         .surface = {
 619                 .set_reg = r100_set_surface_reg,
 620                 .clear_reg = r100_clear_surface_reg,
 621         },
 622         .hpd = {
 623                 .init = &r100_hpd_init,
 624                 .fini = &r100_hpd_fini,
 625                 .sense = &r100_hpd_sense,
 626                 .set_polarity = &r100_hpd_set_polarity,
 627         },
 628         .pm = {
 629                 .misc = &r100_pm_misc,
 630                 .prepare = &r100_pm_prepare,
 631                 .finish = &r100_pm_finish,
 632                 .init_profile = &r100_pm_init_profile,
 633                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 634                 .get_engine_clock = &radeon_legacy_get_engine_clock,
 635                 .set_engine_clock = &radeon_legacy_set_engine_clock,
 636                 .get_memory_clock = &radeon_legacy_get_memory_clock,
 637                 .set_memory_clock = NULL,
 638                 .get_pcie_lanes = NULL,
 639                 .set_pcie_lanes = NULL,
 640                 .set_clock_gating = &radeon_legacy_set_clock_gating,
 641         },
 642         .pflip = {
 643                 .pre_page_flip = &r100_pre_page_flip,
 644                 .page_flip = &r100_page_flip,
 645                 .post_page_flip = &r100_post_page_flip,
 646         },
 647 };
 648
 649 static struct radeon_asic rs600_asic = {
 650         .init = &rs600_init,
 651         .fini = &rs600_fini,
 652         .suspend = &rs600_suspend,
 653         .resume = &rs600_resume,
 654         .vga_set_state = &r100_vga_set_state,
 655         .asic_reset = &rs600_asic_reset,
 656         .ioctl_wait_idle = NULL,
 657         .gui_idle = &r100_gui_idle,
 658         .mc_wait_for_idle = &rs600_mc_wait_for_idle,
 659         .gart = {
 660                 .tlb_flush = &rs600_gart_tlb_flush,
 661                 .set_page = &rs600_gart_set_page,
 662         },
 663         .ring = {
 664                 [RADEON_RING_TYPE_GFX_INDEX] = {
 665                         .ib_execute = &r100_ring_ib_execute,
 666                         .emit_fence = &r300_fence_ring_emit,
 667                         .emit_semaphore = &r100_semaphore_ring_emit,
 668                         .cs_parse = &r300_cs_parse,
 669                         .ring_start = &r300_ring_start,
 670                         .ring_test = &r100_ring_test,
 671                         .ib_test = &r100_ib_test,
 672                         .is_lockup = &r100_gpu_is_lockup,
 673                         .get_rptr = &radeon_ring_generic_get_rptr,
 674                         .get_wptr = &radeon_ring_generic_get_wptr,
 675                         .set_wptr = &radeon_ring_generic_set_wptr,
 676                 }
 677         },
 678         .irq = {
 679                 .set = &rs600_irq_set,
 680                 .process = &rs600_irq_process,
 681         },
 682         .display = {
 683                 .bandwidth_update = &rs600_bandwidth_update,
 684                 .get_vblank_counter = &rs600_get_vblank_counter,
 685                 .wait_for_vblank = &avivo_wait_for_vblank,
 686                 .set_backlight_level = &atombios_set_backlight_level,
 687                 .get_backlight_level = &atombios_get_backlight_level,
 688                 .hdmi_enable = &r600_hdmi_enable,
 689                 .hdmi_setmode = &r600_hdmi_setmode,
 690         },
 691         .copy = {
 692                 .blit = &r100_copy_blit,
 693                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 694                 .dma = &r200_copy_dma,
 695                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 696                 .copy = &r100_copy_blit,
 697                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 698         },
 699         .surface = {
 700                 .set_reg = r100_set_surface_reg,
 701                 .clear_reg = r100_clear_surface_reg,
 702         },
 703         .hpd = {
 704                 .init = &rs600_hpd_init,
 705                 .fini = &rs600_hpd_fini,
 706                 .sense = &rs600_hpd_sense,
 707                 .set_polarity = &rs600_hpd_set_polarity,
 708         },
 709         .pm = {
 710                 .misc = &rs600_pm_misc,
 711                 .prepare = &rs600_pm_prepare,
 712                 .finish = &rs600_pm_finish,
 713                 .init_profile = &r420_pm_init_profile,
 714                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 715                 .get_engine_clock = &radeon_atom_get_engine_clock,
 716                 .set_engine_clock = &radeon_atom_set_engine_clock,
 717                 .get_memory_clock = &radeon_atom_get_memory_clock,
 718                 .set_memory_clock = &radeon_atom_set_memory_clock,
 719                 .get_pcie_lanes = NULL,
 720                 .set_pcie_lanes = NULL,
 721                 .set_clock_gating = &radeon_atom_set_clock_gating,
 722         },
 723         .pflip = {
 724                 .pre_page_flip = &rs600_pre_page_flip,
 725                 .page_flip = &rs600_page_flip,
 726                 .post_page_flip = &rs600_post_page_flip,
 727         },
 728 };
 729
 730 static struct radeon_asic rs690_asic = {
 731         .init = &rs690_init,
 732         .fini = &rs690_fini,
 733         .suspend = &rs690_suspend,
 734         .resume = &rs690_resume,
 735         .vga_set_state = &r100_vga_set_state,
 736         .asic_reset = &rs600_asic_reset,
 737         .ioctl_wait_idle = NULL,
 738         .gui_idle = &r100_gui_idle,
 739         .mc_wait_for_idle = &rs690_mc_wait_for_idle,
 740         .gart = {
 741                 .tlb_flush = &rs400_gart_tlb_flush,
 742                 .set_page = &rs400_gart_set_page,
 743         },
 744         .ring = {
 745                 [RADEON_RING_TYPE_GFX_INDEX] = {
 746                         .ib_execute = &r100_ring_ib_execute,
 747                         .emit_fence = &r300_fence_ring_emit,
 748                         .emit_semaphore = &r100_semaphore_ring_emit,
 749                         .cs_parse = &r300_cs_parse,
 750                         .ring_start = &r300_ring_start,
 751                         .ring_test = &r100_ring_test,
 752                         .ib_test = &r100_ib_test,
 753                         .is_lockup = &r100_gpu_is_lockup,
 754                         .get_rptr = &radeon_ring_generic_get_rptr,
 755                         .get_wptr = &radeon_ring_generic_get_wptr,
 756                         .set_wptr = &radeon_ring_generic_set_wptr,
 757                 }
 758         },
 759         .irq = {
 760                 .set = &rs600_irq_set,
 761                 .process = &rs600_irq_process,
 762         },
 763         .display = {
 764                 .get_vblank_counter = &rs600_get_vblank_counter,
 765                 .bandwidth_update = &rs690_bandwidth_update,
 766                 .wait_for_vblank = &avivo_wait_for_vblank,
 767                 .set_backlight_level = &atombios_set_backlight_level,
 768                 .get_backlight_level = &atombios_get_backlight_level,
 769                 .hdmi_enable = &r600_hdmi_enable,
 770                 .hdmi_setmode = &r600_hdmi_setmode,
 771         },
 772         .copy = {
 773                 .blit = &r100_copy_blit,
 774                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 775                 .dma = &r200_copy_dma,
 776                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 777                 .copy = &r200_copy_dma,
 778                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 779         },
 780         .surface = {
 781                 .set_reg = r100_set_surface_reg,
 782                 .clear_reg = r100_clear_surface_reg,
 783         },
 784         .hpd = {
 785                 .init = &rs600_hpd_init,
 786                 .fini = &rs600_hpd_fini,
 787                 .sense = &rs600_hpd_sense,
 788                 .set_polarity = &rs600_hpd_set_polarity,
 789         },
 790         .pm = {
 791                 .misc = &rs600_pm_misc,
 792                 .prepare = &rs600_pm_prepare,
 793                 .finish = &rs600_pm_finish,
 794                 .init_profile = &r420_pm_init_profile,
 795                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 796                 .get_engine_clock = &radeon_atom_get_engine_clock,
 797                 .set_engine_clock = &radeon_atom_set_engine_clock,
 798                 .get_memory_clock = &radeon_atom_get_memory_clock,
 799                 .set_memory_clock = &radeon_atom_set_memory_clock,
 800                 .get_pcie_lanes = NULL,
 801                 .set_pcie_lanes = NULL,
 802                 .set_clock_gating = &radeon_atom_set_clock_gating,
 803         },
 804         .pflip = {
 805                 .pre_page_flip = &rs600_pre_page_flip,
 806                 .page_flip = &rs600_page_flip,
 807                 .post_page_flip = &rs600_post_page_flip,
 808         },
 809 };
 810
 811 static struct radeon_asic rv515_asic = {
 812         .init = &rv515_init,
 813         .fini = &rv515_fini,
 814         .suspend = &rv515_suspend,
 815         .resume = &rv515_resume,
 816         .vga_set_state = &r100_vga_set_state,
 817         .asic_reset = &rs600_asic_reset,
 818         .ioctl_wait_idle = NULL,
 819         .gui_idle = &r100_gui_idle,
 820         .mc_wait_for_idle = &rv515_mc_wait_for_idle,
 821         .gart = {
 822                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 823                 .set_page = &rv370_pcie_gart_set_page,
 824         },
 825         .ring = {
 826                 [RADEON_RING_TYPE_GFX_INDEX] = {
 827                         .ib_execute = &r100_ring_ib_execute,
 828                         .emit_fence = &r300_fence_ring_emit,
 829                         .emit_semaphore = &r100_semaphore_ring_emit,
 830                         .cs_parse = &r300_cs_parse,
 831                         .ring_start = &rv515_ring_start,
 832                         .ring_test = &r100_ring_test,
 833                         .ib_test = &r100_ib_test,
 834                         .is_lockup = &r100_gpu_is_lockup,
 835                         .get_rptr = &radeon_ring_generic_get_rptr,
 836                         .get_wptr = &radeon_ring_generic_get_wptr,
 837                         .set_wptr = &radeon_ring_generic_set_wptr,
 838                 }
 839         },
 840         .irq = {
 841                 .set = &rs600_irq_set,
 842                 .process = &rs600_irq_process,
 843         },
 844         .display = {
 845                 .get_vblank_counter = &rs600_get_vblank_counter,
 846                 .bandwidth_update = &rv515_bandwidth_update,
 847                 .wait_for_vblank = &avivo_wait_for_vblank,
 848                 .set_backlight_level = &atombios_set_backlight_level,
 849                 .get_backlight_level = &atombios_get_backlight_level,
 850         },
 851         .copy = {
 852                 .blit = &r100_copy_blit,
 853                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 854                 .dma = &r200_copy_dma,
 855                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 856                 .copy = &r100_copy_blit,
 857                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 858         },
 859         .surface = {
 860                 .set_reg = r100_set_surface_reg,
 861                 .clear_reg = r100_clear_surface_reg,
 862         },
 863         .hpd = {
 864                 .init = &rs600_hpd_init,
 865                 .fini = &rs600_hpd_fini,
 866                 .sense = &rs600_hpd_sense,
 867                 .set_polarity = &rs600_hpd_set_polarity,
 868         },
 869         .pm = {
 870                 .misc = &rs600_pm_misc,
 871                 .prepare = &rs600_pm_prepare,
 872                 .finish = &rs600_pm_finish,
 873                 .init_profile = &r420_pm_init_profile,
 874                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 875                 .get_engine_clock = &radeon_atom_get_engine_clock,
 876                 .set_engine_clock = &radeon_atom_set_engine_clock,
 877                 .get_memory_clock = &radeon_atom_get_memory_clock,
 878                 .set_memory_clock = &radeon_atom_set_memory_clock,
 879                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 880                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 881                 .set_clock_gating = &radeon_atom_set_clock_gating,
 882         },
 883         .pflip = {
 884                 .pre_page_flip = &rs600_pre_page_flip,
 885                 .page_flip = &rs600_page_flip,
 886                 .post_page_flip = &rs600_post_page_flip,
 887         },
 888 };
 889
 890 static struct radeon_asic r520_asic = {
 891         .init = &r520_init,
 892         .fini = &rv515_fini,
 893         .suspend = &rv515_suspend,
 894         .resume = &r520_resume,
 895         .vga_set_state = &r100_vga_set_state,
 896         .asic_reset = &rs600_asic_reset,
 897         .ioctl_wait_idle = NULL,
 898         .gui_idle = &r100_gui_idle,
 899         .mc_wait_for_idle = &r520_mc_wait_for_idle,
 900         .gart = {
 901                 .tlb_flush = &rv370_pcie_gart_tlb_flush,
 902                 .set_page = &rv370_pcie_gart_set_page,
 903         },
 904         .ring = {
 905                 [RADEON_RING_TYPE_GFX_INDEX] = {
 906                         .ib_execute = &r100_ring_ib_execute,
 907                         .emit_fence = &r300_fence_ring_emit,
 908                         .emit_semaphore = &r100_semaphore_ring_emit,
 909                         .cs_parse = &r300_cs_parse,
 910                         .ring_start = &rv515_ring_start,
 911                         .ring_test = &r100_ring_test,
 912                         .ib_test = &r100_ib_test,
 913                         .is_lockup = &r100_gpu_is_lockup,
 914                         .get_rptr = &radeon_ring_generic_get_rptr,
 915                         .get_wptr = &radeon_ring_generic_get_wptr,
 916                         .set_wptr = &radeon_ring_generic_set_wptr,
 917                 }
 918         },
 919         .irq = {
 920                 .set = &rs600_irq_set,
 921                 .process = &rs600_irq_process,
 922         },
 923         .display = {
 924                 .bandwidth_update = &rv515_bandwidth_update,
 925                 .get_vblank_counter = &rs600_get_vblank_counter,
 926                 .wait_for_vblank = &avivo_wait_for_vblank,
 927                 .set_backlight_level = &atombios_set_backlight_level,
 928                 .get_backlight_level = &atombios_get_backlight_level,
 929         },
 930         .copy = {
 931                 .blit = &r100_copy_blit,
 932                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 933                 .dma = &r200_copy_dma,
 934                 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 935                 .copy = &r100_copy_blit,
 936                 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
 937         },
 938         .surface = {
 939                 .set_reg = r100_set_surface_reg,
 940                 .clear_reg = r100_clear_surface_reg,
 941         },
 942         .hpd = {
 943                 .init = &rs600_hpd_init,
 944                 .fini = &rs600_hpd_fini,
 945                 .sense = &rs600_hpd_sense,
 946                 .set_polarity = &rs600_hpd_set_polarity,
 947         },
 948         .pm = {
 949                 .misc = &rs600_pm_misc,
 950                 .prepare = &rs600_pm_prepare,
 951                 .finish = &rs600_pm_finish,
 952                 .init_profile = &r420_pm_init_profile,
 953                 .get_dynpm_state = &r100_pm_get_dynpm_state,
 954                 .get_engine_clock = &radeon_atom_get_engine_clock,
 955                 .set_engine_clock = &radeon_atom_set_engine_clock,
 956                 .get_memory_clock = &radeon_atom_get_memory_clock,
 957                 .set_memory_clock = &radeon_atom_set_memory_clock,
 958                 .get_pcie_lanes = &rv370_get_pcie_lanes,
 959                 .set_pcie_lanes = &rv370_set_pcie_lanes,
 960                 .set_clock_gating = &radeon_atom_set_clock_gating,
 961         },
 962         .pflip = {
 963                 .pre_page_flip = &rs600_pre_page_flip,
 964                 .page_flip = &rs600_page_flip,
 965                 .post_page_flip = &rs600_post_page_flip,
 966         },
 967 };
 968
 969 static struct radeon_asic r600_asic = {
 970         .init = &r600_init,
 971         .fini = &r600_fini,
 972         .suspend = &r600_suspend,
 973         .resume = &r600_resume,
 974         .vga_set_state = &r600_vga_set_state,
 975         .asic_reset = &r600_asic_reset,
 976         .ioctl_wait_idle = r600_ioctl_wait_idle,
 977         .gui_idle = &r600_gui_idle,
 978         .mc_wait_for_idle = &r600_mc_wait_for_idle,
 979         .get_xclk = &r600_get_xclk,
 980         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
 981         .gart = {
 982                 .tlb_flush = &r600_pcie_gart_tlb_flush,
 983                 .set_page = &rs600_gart_set_page,
 984         },
 985         .ring = {
 986                 [RADEON_RING_TYPE_GFX_INDEX] = {
 987                         .ib_execute = &r600_ring_ib_execute,
 988                         .emit_fence = &r600_fence_ring_emit,
 989                         .emit_semaphore = &r600_semaphore_ring_emit,
 990                         .cs_parse = &r600_cs_parse,
 991                         .ring_test = &r600_ring_test,
 992                         .ib_test = &r600_ib_test,
 993                         .is_lockup = &r600_gfx_is_lockup,
 994                         .get_rptr = &radeon_ring_generic_get_rptr,
 995                         .get_wptr = &radeon_ring_generic_get_wptr,
 996                         .set_wptr = &radeon_ring_generic_set_wptr,
 997                 },
 998                 [R600_RING_TYPE_DMA_INDEX] = {
 999                         .ib_execute = &r600_dma_ring_ib_execute,
1000                         .emit_fence = &r600_dma_fence_ring_emit,
1001                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1002                         .cs_parse = &r600_dma_cs_parse,
1003                         .ring_test = &r600_dma_ring_test,
1004                         .ib_test = &r600_dma_ib_test,
1005                         .is_lockup = &r600_dma_is_lockup,
1006                         .get_rptr = &radeon_ring_generic_get_rptr,
1007                         .get_wptr = &radeon_ring_generic_get_wptr,
1008                         .set_wptr = &radeon_ring_generic_set_wptr,
1009                 }
1010         },
1011         .irq = {
1012                 .set = &r600_irq_set,
1013                 .process = &r600_irq_process,
1014         },
1015         .display = {
1016                 .bandwidth_update = &rv515_bandwidth_update,
1017                 .get_vblank_counter = &rs600_get_vblank_counter,
1018                 .wait_for_vblank = &avivo_wait_for_vblank,
1019                 .set_backlight_level = &atombios_set_backlight_level,
1020                 .get_backlight_level = &atombios_get_backlight_level,
1021                 .hdmi_enable = &r600_hdmi_enable,
1022                 .hdmi_setmode = &r600_hdmi_setmode,
1023         },
1024         .copy = {
1025                 .blit = &r600_copy_blit,
1026                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1027                 .dma = &r600_copy_dma,
1028                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1029                 .copy = &r600_copy_dma,
1030                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1031         },
1032         .surface = {
1033                 .set_reg = r600_set_surface_reg,
1034                 .clear_reg = r600_clear_surface_reg,
1035         },
1036         .hpd = {
1037                 .init = &r600_hpd_init,
1038                 .fini = &r600_hpd_fini,
1039                 .sense = &r600_hpd_sense,
1040                 .set_polarity = &r600_hpd_set_polarity,
1041         },
1042         .pm = {
1043                 .misc = &r600_pm_misc,
1044                 .prepare = &rs600_pm_prepare,
1045                 .finish = &rs600_pm_finish,
1046                 .init_profile = &r600_pm_init_profile,
1047                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1048                 .get_engine_clock = &radeon_atom_get_engine_clock,
1049                 .set_engine_clock = &radeon_atom_set_engine_clock,
1050                 .get_memory_clock = &radeon_atom_get_memory_clock,
1051                 .set_memory_clock = &radeon_atom_set_memory_clock,
1052                 .get_pcie_lanes = &r600_get_pcie_lanes,
1053                 .set_pcie_lanes = &r600_set_pcie_lanes,
1054                 .set_clock_gating = NULL,
1055                 .get_temperature = &rv6xx_get_temp,
1056         },
1057         .pflip = {
1058                 .pre_page_flip = &rs600_pre_page_flip,
1059                 .page_flip = &rs600_page_flip,
1060                 .post_page_flip = &rs600_post_page_flip,
1061         },
1062 };
1063
1064 static struct radeon_asic rv6xx_asic = {
1065         .init = &r600_init,
1066         .fini = &r600_fini,
1067         .suspend = &r600_suspend,
1068         .resume = &r600_resume,
1069         .vga_set_state = &r600_vga_set_state,
1070         .asic_reset = &r600_asic_reset,
1071         .ioctl_wait_idle = r600_ioctl_wait_idle,
1072         .gui_idle = &r600_gui_idle,
1073         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1074         .get_xclk = &r600_get_xclk,
1075         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1076         .gart = {
1077                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1078                 .set_page = &rs600_gart_set_page,
1079         },
1080         .ring = {
1081                 [RADEON_RING_TYPE_GFX_INDEX] = {
1082                         .ib_execute = &r600_ring_ib_execute,
1083                         .emit_fence = &r600_fence_ring_emit,
1084                         .emit_semaphore = &r600_semaphore_ring_emit,
1085                         .cs_parse = &r600_cs_parse,
1086                         .ring_test = &r600_ring_test,
1087                         .ib_test = &r600_ib_test,
1088                         .is_lockup = &r600_gfx_is_lockup,
1089                         .get_rptr = &radeon_ring_generic_get_rptr,
1090                         .get_wptr = &radeon_ring_generic_get_wptr,
1091                         .set_wptr = &radeon_ring_generic_set_wptr,
1092                 },
1093                 [R600_RING_TYPE_DMA_INDEX] = {
1094                         .ib_execute = &r600_dma_ring_ib_execute,
1095                         .emit_fence = &r600_dma_fence_ring_emit,
1096                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1097                         .cs_parse = &r600_dma_cs_parse,
1098                         .ring_test = &r600_dma_ring_test,
1099                         .ib_test = &r600_dma_ib_test,
1100                         .is_lockup = &r600_dma_is_lockup,
1101                         .get_rptr = &radeon_ring_generic_get_rptr,
1102                         .get_wptr = &radeon_ring_generic_get_wptr,
1103                         .set_wptr = &radeon_ring_generic_set_wptr,
1104                 }
1105         },
1106         .irq = {
1107                 .set = &r600_irq_set,
1108                 .process = &r600_irq_process,
1109         },
1110         .display = {
1111                 .bandwidth_update = &rv515_bandwidth_update,
1112                 .get_vblank_counter = &rs600_get_vblank_counter,
1113                 .wait_for_vblank = &avivo_wait_for_vblank,
1114                 .set_backlight_level = &atombios_set_backlight_level,
1115                 .get_backlight_level = &atombios_get_backlight_level,
1116         },
1117         .copy = {
1118                 .blit = &r600_copy_blit,
1119                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1120                 .dma = &r600_copy_dma,
1121                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1122                 .copy = &r600_copy_dma,
1123                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1124         },
1125         .surface = {
1126                 .set_reg = r600_set_surface_reg,
1127                 .clear_reg = r600_clear_surface_reg,
1128         },
1129         .hpd = {
1130                 .init = &r600_hpd_init,
1131                 .fini = &r600_hpd_fini,
1132                 .sense = &r600_hpd_sense,
1133                 .set_polarity = &r600_hpd_set_polarity,
1134         },
1135         .pm = {
1136                 .misc = &r600_pm_misc,
1137                 .prepare = &rs600_pm_prepare,
1138                 .finish = &rs600_pm_finish,
1139                 .init_profile = &r600_pm_init_profile,
1140                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1141                 .get_engine_clock = &radeon_atom_get_engine_clock,
1142                 .set_engine_clock = &radeon_atom_set_engine_clock,
1143                 .get_memory_clock = &radeon_atom_get_memory_clock,
1144                 .set_memory_clock = &radeon_atom_set_memory_clock,
1145                 .get_pcie_lanes = &r600_get_pcie_lanes,
1146                 .set_pcie_lanes = &r600_set_pcie_lanes,
1147                 .set_clock_gating = NULL,
1148                 .get_temperature = &rv6xx_get_temp,
1149         },
1150         .dpm = {
1151                 .init = &rv6xx_dpm_init,
1152                 .setup_asic = &rv6xx_setup_asic,
1153                 .enable = &rv6xx_dpm_enable,
1154                 .disable = &rv6xx_dpm_disable,
1155                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1156                 .set_power_state = &rv6xx_dpm_set_power_state,
1157                 .post_set_power_state = &r600_dpm_post_set_power_state,
1158                 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1159                 .fini = &rv6xx_dpm_fini,
1160                 .get_sclk = &rv6xx_dpm_get_sclk,
1161                 .get_mclk = &rv6xx_dpm_get_mclk,
1162                 .print_power_state = &rv6xx_dpm_print_power_state,
1163                 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1164         },
1165         .pflip = {
1166                 .pre_page_flip = &rs600_pre_page_flip,
1167                 .page_flip = &rs600_page_flip,
1168                 .post_page_flip = &rs600_post_page_flip,
1169         },
1170 };
1171
1172 static struct radeon_asic rs780_asic = {
1173         .init = &r600_init,
1174         .fini = &r600_fini,
1175         .suspend = &r600_suspend,
1176         .resume = &r600_resume,
1177         .vga_set_state = &r600_vga_set_state,
1178         .asic_reset = &r600_asic_reset,
1179         .ioctl_wait_idle = r600_ioctl_wait_idle,
1180         .gui_idle = &r600_gui_idle,
1181         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1182         .get_xclk = &r600_get_xclk,
1183         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1184         .gart = {
1185                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1186                 .set_page = &rs600_gart_set_page,
1187         },
1188         .ring = {
1189                 [RADEON_RING_TYPE_GFX_INDEX] = {
1190                         .ib_execute = &r600_ring_ib_execute,
1191                         .emit_fence = &r600_fence_ring_emit,
1192                         .emit_semaphore = &r600_semaphore_ring_emit,
1193                         .cs_parse = &r600_cs_parse,
1194                         .ring_test = &r600_ring_test,
1195                         .ib_test = &r600_ib_test,
1196                         .is_lockup = &r600_gfx_is_lockup,
1197                         .get_rptr = &radeon_ring_generic_get_rptr,
1198                         .get_wptr = &radeon_ring_generic_get_wptr,
1199                         .set_wptr = &radeon_ring_generic_set_wptr,
1200                 },
1201                 [R600_RING_TYPE_DMA_INDEX] = {
1202                         .ib_execute = &r600_dma_ring_ib_execute,
1203                         .emit_fence = &r600_dma_fence_ring_emit,
1204                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1205                         .cs_parse = &r600_dma_cs_parse,
1206                         .ring_test = &r600_dma_ring_test,
1207                         .ib_test = &r600_dma_ib_test,
1208                         .is_lockup = &r600_dma_is_lockup,
1209                         .get_rptr = &radeon_ring_generic_get_rptr,
1210                         .get_wptr = &radeon_ring_generic_get_wptr,
1211                         .set_wptr = &radeon_ring_generic_set_wptr,
1212                 }
1213         },
1214         .irq = {
1215                 .set = &r600_irq_set,
1216                 .process = &r600_irq_process,
1217         },
1218         .display = {
1219                 .bandwidth_update = &rs690_bandwidth_update,
1220                 .get_vblank_counter = &rs600_get_vblank_counter,
1221                 .wait_for_vblank = &avivo_wait_for_vblank,
1222                 .set_backlight_level = &atombios_set_backlight_level,
1223                 .get_backlight_level = &atombios_get_backlight_level,
1224                 .hdmi_enable = &r600_hdmi_enable,
1225                 .hdmi_setmode = &r600_hdmi_setmode,
1226         },
1227         .copy = {
1228                 .blit = &r600_copy_blit,
1229                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1230                 .dma = &r600_copy_dma,
1231                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1232                 .copy = &r600_copy_dma,
1233                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1234         },
1235         .surface = {
1236                 .set_reg = r600_set_surface_reg,
1237                 .clear_reg = r600_clear_surface_reg,
1238         },
1239         .hpd = {
1240                 .init = &r600_hpd_init,
1241                 .fini = &r600_hpd_fini,
1242                 .sense = &r600_hpd_sense,
1243                 .set_polarity = &r600_hpd_set_polarity,
1244         },
1245         .pm = {
1246                 .misc = &r600_pm_misc,
1247                 .prepare = &rs600_pm_prepare,
1248                 .finish = &rs600_pm_finish,
1249                 .init_profile = &rs780_pm_init_profile,
1250                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1251                 .get_engine_clock = &radeon_atom_get_engine_clock,
1252                 .set_engine_clock = &radeon_atom_set_engine_clock,
1253                 .get_memory_clock = NULL,
1254                 .set_memory_clock = NULL,
1255                 .get_pcie_lanes = NULL,
1256                 .set_pcie_lanes = NULL,
1257                 .set_clock_gating = NULL,
1258                 .get_temperature = &rv6xx_get_temp,
1259         },
1260         .dpm = {
1261                 .init = &rs780_dpm_init,
1262                 .setup_asic = &rs780_dpm_setup_asic,
1263                 .enable = &rs780_dpm_enable,
1264                 .disable = &rs780_dpm_disable,
1265                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1266                 .set_power_state = &rs780_dpm_set_power_state,
1267                 .post_set_power_state = &r600_dpm_post_set_power_state,
1268                 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1269                 .fini = &rs780_dpm_fini,
1270                 .get_sclk = &rs780_dpm_get_sclk,
1271                 .get_mclk = &rs780_dpm_get_mclk,
1272                 .print_power_state = &rs780_dpm_print_power_state,
1273         },
1274         .pflip = {
1275                 .pre_page_flip = &rs600_pre_page_flip,
1276                 .page_flip = &rs600_page_flip,
1277                 .post_page_flip = &rs600_post_page_flip,
1278         },
1279 };
1280
1281 static struct radeon_asic rv770_asic = {
1282         .init = &rv770_init,
1283         .fini = &rv770_fini,
1284         .suspend = &rv770_suspend,
1285         .resume = &rv770_resume,
1286         .asic_reset = &r600_asic_reset,
1287         .vga_set_state = &r600_vga_set_state,
1288         .ioctl_wait_idle = r600_ioctl_wait_idle,
1289         .gui_idle = &r600_gui_idle,
1290         .mc_wait_for_idle = &r600_mc_wait_for_idle,
1291         .get_xclk = &rv770_get_xclk,
1292         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1293         .gart = {
1294                 .tlb_flush = &r600_pcie_gart_tlb_flush,
1295                 .set_page = &rs600_gart_set_page,
1296         },
1297         .ring = {
1298                 [RADEON_RING_TYPE_GFX_INDEX] = {
1299                         .ib_execute = &r600_ring_ib_execute,
1300                         .emit_fence = &r600_fence_ring_emit,
1301                         .emit_semaphore = &r600_semaphore_ring_emit,
1302                         .cs_parse = &r600_cs_parse,
1303                         .ring_test = &r600_ring_test,
1304                         .ib_test = &r600_ib_test,
1305                         .is_lockup = &r600_gfx_is_lockup,
1306                         .get_rptr = &radeon_ring_generic_get_rptr,
1307                         .get_wptr = &radeon_ring_generic_get_wptr,
1308                         .set_wptr = &radeon_ring_generic_set_wptr,
1309                 },
1310                 [R600_RING_TYPE_DMA_INDEX] = {
1311                         .ib_execute = &r600_dma_ring_ib_execute,
1312                         .emit_fence = &r600_dma_fence_ring_emit,
1313                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1314                         .cs_parse = &r600_dma_cs_parse,
1315                         .ring_test = &r600_dma_ring_test,
1316                         .ib_test = &r600_dma_ib_test,
1317                         .is_lockup = &r600_dma_is_lockup,
1318                         .get_rptr = &radeon_ring_generic_get_rptr,
1319                         .get_wptr = &radeon_ring_generic_get_wptr,
1320                         .set_wptr = &radeon_ring_generic_set_wptr,
1321                 },
1322                 [R600_RING_TYPE_UVD_INDEX] = {
1323                         .ib_execute = &r600_uvd_ib_execute,
1324                         .emit_fence = &r600_uvd_fence_emit,
1325                         .emit_semaphore = &r600_uvd_semaphore_emit,
1326                         .cs_parse = &radeon_uvd_cs_parse,
1327                         .ring_test = &r600_uvd_ring_test,
1328                         .ib_test = &r600_uvd_ib_test,
1329                         .is_lockup = &radeon_ring_test_lockup,
1330                         .get_rptr = &radeon_ring_generic_get_rptr,
1331                         .get_wptr = &radeon_ring_generic_get_wptr,
1332                         .set_wptr = &radeon_ring_generic_set_wptr,
1333                 }
1334         },
1335         .irq = {
1336                 .set = &r600_irq_set,
1337                 .process = &r600_irq_process,
1338         },
1339         .display = {
1340                 .bandwidth_update = &rv515_bandwidth_update,
1341                 .get_vblank_counter = &rs600_get_vblank_counter,
1342                 .wait_for_vblank = &avivo_wait_for_vblank,
1343                 .set_backlight_level = &atombios_set_backlight_level,
1344                 .get_backlight_level = &atombios_get_backlight_level,
1345                 .hdmi_enable = &r600_hdmi_enable,
1346                 .hdmi_setmode = &r600_hdmi_setmode,
1347         },
1348         .copy = {
1349                 .blit = &r600_copy_blit,
1350                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1351                 .dma = &rv770_copy_dma,
1352                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1353                 .copy = &rv770_copy_dma,
1354                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1355         },
1356         .surface = {
1357                 .set_reg = r600_set_surface_reg,
1358                 .clear_reg = r600_clear_surface_reg,
1359         },
1360         .hpd = {
1361                 .init = &r600_hpd_init,
1362                 .fini = &r600_hpd_fini,
1363                 .sense = &r600_hpd_sense,
1364                 .set_polarity = &r600_hpd_set_polarity,
1365         },
1366         .pm = {
1367                 .misc = &rv770_pm_misc,
1368                 .prepare = &rs600_pm_prepare,
1369                 .finish = &rs600_pm_finish,
1370                 .init_profile = &r600_pm_init_profile,
1371                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1372                 .get_engine_clock = &radeon_atom_get_engine_clock,
1373                 .set_engine_clock = &radeon_atom_set_engine_clock,
1374                 .get_memory_clock = &radeon_atom_get_memory_clock,
1375                 .set_memory_clock = &radeon_atom_set_memory_clock,
1376                 .get_pcie_lanes = &r600_get_pcie_lanes,
1377                 .set_pcie_lanes = &r600_set_pcie_lanes,
1378                 .set_clock_gating = &radeon_atom_set_clock_gating,
1379                 .set_uvd_clocks = &rv770_set_uvd_clocks,
1380                 .get_temperature = &rv770_get_temp,
1381         },
1382         .dpm = {
1383                 .init = &rv770_dpm_init,
1384                 .setup_asic = &rv770_dpm_setup_asic,
1385                 .enable = &rv770_dpm_enable,
1386                 .disable = &rv770_dpm_disable,
1387                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1388                 .set_power_state = &rv770_dpm_set_power_state,
1389                 .post_set_power_state = &r600_dpm_post_set_power_state,
1390                 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1391                 .fini = &rv770_dpm_fini,
1392                 .get_sclk = &rv770_dpm_get_sclk,
1393                 .get_mclk = &rv770_dpm_get_mclk,
1394                 .print_power_state = &rv770_dpm_print_power_state,
1395                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1396                 .force_performance_level = &rv770_dpm_force_performance_level,
1397         },
1398         .pflip = {
1399                 .pre_page_flip = &rs600_pre_page_flip,
1400                 .page_flip = &rv770_page_flip,
1401                 .post_page_flip = &rs600_post_page_flip,
1402         },
1403 };
1404
1405 static struct radeon_asic evergreen_asic = {
1406         .init = &evergreen_init,
1407         .fini = &evergreen_fini,
1408         .suspend = &evergreen_suspend,
1409         .resume = &evergreen_resume,
1410         .asic_reset = &evergreen_asic_reset,
1411         .vga_set_state = &r600_vga_set_state,
1412         .ioctl_wait_idle = r600_ioctl_wait_idle,
1413         .gui_idle = &r600_gui_idle,
1414         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1415         .get_xclk = &rv770_get_xclk,
1416         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1417         .gart = {
1418                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1419                 .set_page = &rs600_gart_set_page,
1420         },
1421         .ring = {
1422                 [RADEON_RING_TYPE_GFX_INDEX] = {
1423                         .ib_execute = &evergreen_ring_ib_execute,
1424                         .emit_fence = &r600_fence_ring_emit,
1425                         .emit_semaphore = &r600_semaphore_ring_emit,
1426                         .cs_parse = &evergreen_cs_parse,
1427                         .ring_test = &r600_ring_test,
1428                         .ib_test = &r600_ib_test,
1429                         .is_lockup = &evergreen_gfx_is_lockup,
1430                         .get_rptr = &radeon_ring_generic_get_rptr,
1431                         .get_wptr = &radeon_ring_generic_get_wptr,
1432                         .set_wptr = &radeon_ring_generic_set_wptr,
1433                 },
1434                 [R600_RING_TYPE_DMA_INDEX] = {
1435                         .ib_execute = &evergreen_dma_ring_ib_execute,
1436                         .emit_fence = &evergreen_dma_fence_ring_emit,
1437                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1438                         .cs_parse = &evergreen_dma_cs_parse,
1439                         .ring_test = &r600_dma_ring_test,
1440                         .ib_test = &r600_dma_ib_test,
1441                         .is_lockup = &evergreen_dma_is_lockup,
1442                         .get_rptr = &radeon_ring_generic_get_rptr,
1443                         .get_wptr = &radeon_ring_generic_get_wptr,
1444                         .set_wptr = &radeon_ring_generic_set_wptr,
1445                 },
1446                 [R600_RING_TYPE_UVD_INDEX] = {
1447                         .ib_execute = &r600_uvd_ib_execute,
1448                         .emit_fence = &r600_uvd_fence_emit,
1449                         .emit_semaphore = &r600_uvd_semaphore_emit,
1450                         .cs_parse = &radeon_uvd_cs_parse,
1451                         .ring_test = &r600_uvd_ring_test,
1452                         .ib_test = &r600_uvd_ib_test,
1453                         .is_lockup = &radeon_ring_test_lockup,
1454                         .get_rptr = &radeon_ring_generic_get_rptr,
1455                         .get_wptr = &radeon_ring_generic_get_wptr,
1456                         .set_wptr = &radeon_ring_generic_set_wptr,
1457                 }
1458         },
1459         .irq = {
1460                 .set = &evergreen_irq_set,
1461                 .process = &evergreen_irq_process,
1462         },
1463         .display = {
1464                 .bandwidth_update = &evergreen_bandwidth_update,
1465                 .get_vblank_counter = &evergreen_get_vblank_counter,
1466                 .wait_for_vblank = &dce4_wait_for_vblank,
1467                 .set_backlight_level = &atombios_set_backlight_level,
1468                 .get_backlight_level = &atombios_get_backlight_level,
1469                 .hdmi_enable = &evergreen_hdmi_enable,
1470                 .hdmi_setmode = &evergreen_hdmi_setmode,
1471         },
1472         .copy = {
1473                 .blit = &r600_copy_blit,
1474                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1475                 .dma = &evergreen_copy_dma,
1476                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1477                 .copy = &evergreen_copy_dma,
1478                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1479         },
1480         .surface = {
1481                 .set_reg = r600_set_surface_reg,
1482                 .clear_reg = r600_clear_surface_reg,
1483         },
1484         .hpd = {
1485                 .init = &evergreen_hpd_init,
1486                 .fini = &evergreen_hpd_fini,
1487                 .sense = &evergreen_hpd_sense,
1488                 .set_polarity = &evergreen_hpd_set_polarity,
1489         },
1490         .pm = {
1491                 .misc = &evergreen_pm_misc,
1492                 .prepare = &evergreen_pm_prepare,
1493                 .finish = &evergreen_pm_finish,
1494                 .init_profile = &r600_pm_init_profile,
1495                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1496                 .get_engine_clock = &radeon_atom_get_engine_clock,
1497                 .set_engine_clock = &radeon_atom_set_engine_clock,
1498                 .get_memory_clock = &radeon_atom_get_memory_clock,
1499                 .set_memory_clock = &radeon_atom_set_memory_clock,
1500                 .get_pcie_lanes = &r600_get_pcie_lanes,
1501                 .set_pcie_lanes = &r600_set_pcie_lanes,
1502                 .set_clock_gating = NULL,
1503                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1504                 .get_temperature = &evergreen_get_temp,
1505         },
1506         .dpm = {
1507                 .init = &cypress_dpm_init,
1508                 .setup_asic = &cypress_dpm_setup_asic,
1509                 .enable = &cypress_dpm_enable,
1510                 .disable = &cypress_dpm_disable,
1511                 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1512                 .set_power_state = &cypress_dpm_set_power_state,
1513                 .post_set_power_state = &r600_dpm_post_set_power_state,
1514                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1515                 .fini = &cypress_dpm_fini,
1516                 .get_sclk = &rv770_dpm_get_sclk,
1517                 .get_mclk = &rv770_dpm_get_mclk,
1518                 .print_power_state = &rv770_dpm_print_power_state,
1519                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1520                 .force_performance_level = &rv770_dpm_force_performance_level,
1521         },
1522         .pflip = {
1523                 .pre_page_flip = &evergreen_pre_page_flip,
1524                 .page_flip = &evergreen_page_flip,
1525                 .post_page_flip = &evergreen_post_page_flip,
1526         },
1527 };
1528
1529 static struct radeon_asic sumo_asic = {
1530         .init = &evergreen_init,
1531         .fini = &evergreen_fini,
1532         .suspend = &evergreen_suspend,
1533         .resume = &evergreen_resume,
1534         .asic_reset = &evergreen_asic_reset,
1535         .vga_set_state = &r600_vga_set_state,
1536         .ioctl_wait_idle = r600_ioctl_wait_idle,
1537         .gui_idle = &r600_gui_idle,
1538         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1539         .get_xclk = &r600_get_xclk,
1540         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1541         .gart = {
1542                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1543                 .set_page = &rs600_gart_set_page,
1544         },
1545         .ring = {
1546                 [RADEON_RING_TYPE_GFX_INDEX] = {
1547                         .ib_execute = &evergreen_ring_ib_execute,
1548                         .emit_fence = &r600_fence_ring_emit,
1549                         .emit_semaphore = &r600_semaphore_ring_emit,
1550                         .cs_parse = &evergreen_cs_parse,
1551                         .ring_test = &r600_ring_test,
1552                         .ib_test = &r600_ib_test,
1553                         .is_lockup = &evergreen_gfx_is_lockup,
1554                         .get_rptr = &radeon_ring_generic_get_rptr,
1555                         .get_wptr = &radeon_ring_generic_get_wptr,
1556                         .set_wptr = &radeon_ring_generic_set_wptr,
1557                 },
1558                 [R600_RING_TYPE_DMA_INDEX] = {
1559                         .ib_execute = &evergreen_dma_ring_ib_execute,
1560                         .emit_fence = &evergreen_dma_fence_ring_emit,
1561                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1562                         .cs_parse = &evergreen_dma_cs_parse,
1563                         .ring_test = &r600_dma_ring_test,
1564                         .ib_test = &r600_dma_ib_test,
1565                         .is_lockup = &evergreen_dma_is_lockup,
1566                         .get_rptr = &radeon_ring_generic_get_rptr,
1567                         .get_wptr = &radeon_ring_generic_get_wptr,
1568                         .set_wptr = &radeon_ring_generic_set_wptr,
1569                 },
1570                 [R600_RING_TYPE_UVD_INDEX] = {
1571                         .ib_execute = &r600_uvd_ib_execute,
1572                         .emit_fence = &r600_uvd_fence_emit,
1573                         .emit_semaphore = &r600_uvd_semaphore_emit,
1574                         .cs_parse = &radeon_uvd_cs_parse,
1575                         .ring_test = &r600_uvd_ring_test,
1576                         .ib_test = &r600_uvd_ib_test,
1577                         .is_lockup = &radeon_ring_test_lockup,
1578                         .get_rptr = &radeon_ring_generic_get_rptr,
1579                         .get_wptr = &radeon_ring_generic_get_wptr,
1580                         .set_wptr = &radeon_ring_generic_set_wptr,
1581                 }
1582         },
1583         .irq = {
1584                 .set = &evergreen_irq_set,
1585                 .process = &evergreen_irq_process,
1586         },
1587         .display = {
1588                 .bandwidth_update = &evergreen_bandwidth_update,
1589                 .get_vblank_counter = &evergreen_get_vblank_counter,
1590                 .wait_for_vblank = &dce4_wait_for_vblank,
1591                 .set_backlight_level = &atombios_set_backlight_level,
1592                 .get_backlight_level = &atombios_get_backlight_level,
1593                 .hdmi_enable = &evergreen_hdmi_enable,
1594                 .hdmi_setmode = &evergreen_hdmi_setmode,
1595         },
1596         .copy = {
1597                 .blit = &r600_copy_blit,
1598                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1599                 .dma = &evergreen_copy_dma,
1600                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1601                 .copy = &evergreen_copy_dma,
1602                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1603         },
1604         .surface = {
1605                 .set_reg = r600_set_surface_reg,
1606                 .clear_reg = r600_clear_surface_reg,
1607         },
1608         .hpd = {
1609                 .init = &evergreen_hpd_init,
1610                 .fini = &evergreen_hpd_fini,
1611                 .sense = &evergreen_hpd_sense,
1612                 .set_polarity = &evergreen_hpd_set_polarity,
1613         },
1614         .pm = {
1615                 .misc = &evergreen_pm_misc,
1616                 .prepare = &evergreen_pm_prepare,
1617                 .finish = &evergreen_pm_finish,
1618                 .init_profile = &sumo_pm_init_profile,
1619                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1620                 .get_engine_clock = &radeon_atom_get_engine_clock,
1621                 .set_engine_clock = &radeon_atom_set_engine_clock,
1622                 .get_memory_clock = NULL,
1623                 .set_memory_clock = NULL,
1624                 .get_pcie_lanes = NULL,
1625                 .set_pcie_lanes = NULL,
1626                 .set_clock_gating = NULL,
1627                 .set_uvd_clocks = &sumo_set_uvd_clocks,
1628                 .get_temperature = &sumo_get_temp,
1629         },
1630         .dpm = {
1631                 .init = &sumo_dpm_init,
1632                 .setup_asic = &sumo_dpm_setup_asic,
1633                 .enable = &sumo_dpm_enable,
1634                 .disable = &sumo_dpm_disable,
1635                 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1636                 .set_power_state = &sumo_dpm_set_power_state,
1637                 .post_set_power_state = &sumo_dpm_post_set_power_state,
1638                 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1639                 .fini = &sumo_dpm_fini,
1640                 .get_sclk = &sumo_dpm_get_sclk,
1641                 .get_mclk = &sumo_dpm_get_mclk,
1642                 .print_power_state = &sumo_dpm_print_power_state,
1643                 .debugfs_print_current_performance_level = &sumo_dpm_debugfs_print_current_performance_level,
1644         },
1645         .pflip = {
1646                 .pre_page_flip = &evergreen_pre_page_flip,
1647                 .page_flip = &evergreen_page_flip,
1648                 .post_page_flip = &evergreen_post_page_flip,
1649         },
1650 };
1651
1652 static struct radeon_asic btc_asic = {
1653         .init = &evergreen_init,
1654         .fini = &evergreen_fini,
1655         .suspend = &evergreen_suspend,
1656         .resume = &evergreen_resume,
1657         .asic_reset = &evergreen_asic_reset,
1658         .vga_set_state = &r600_vga_set_state,
1659         .ioctl_wait_idle = r600_ioctl_wait_idle,
1660         .gui_idle = &r600_gui_idle,
1661         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1662         .get_xclk = &rv770_get_xclk,
1663         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1664         .gart = {
1665                 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1666                 .set_page = &rs600_gart_set_page,
1667         },
1668         .ring = {
1669                 [RADEON_RING_TYPE_GFX_INDEX] = {
1670                         .ib_execute = &evergreen_ring_ib_execute,
1671                         .emit_fence = &r600_fence_ring_emit,
1672                         .emit_semaphore = &r600_semaphore_ring_emit,
1673                         .cs_parse = &evergreen_cs_parse,
1674                         .ring_test = &r600_ring_test,
1675                         .ib_test = &r600_ib_test,
1676                         .is_lockup = &evergreen_gfx_is_lockup,
1677                         .get_rptr = &radeon_ring_generic_get_rptr,
1678                         .get_wptr = &radeon_ring_generic_get_wptr,
1679                         .set_wptr = &radeon_ring_generic_set_wptr,
1680                 },
1681                 [R600_RING_TYPE_DMA_INDEX] = {
1682                         .ib_execute = &evergreen_dma_ring_ib_execute,
1683                         .emit_fence = &evergreen_dma_fence_ring_emit,
1684                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1685                         .cs_parse = &evergreen_dma_cs_parse,
1686                         .ring_test = &r600_dma_ring_test,
1687                         .ib_test = &r600_dma_ib_test,
1688                         .is_lockup = &evergreen_dma_is_lockup,
1689                         .get_rptr = &radeon_ring_generic_get_rptr,
1690                         .get_wptr = &radeon_ring_generic_get_wptr,
1691                         .set_wptr = &radeon_ring_generic_set_wptr,
1692                 },
1693                 [R600_RING_TYPE_UVD_INDEX] = {
1694                         .ib_execute = &r600_uvd_ib_execute,
1695                         .emit_fence = &r600_uvd_fence_emit,
1696                         .emit_semaphore = &r600_uvd_semaphore_emit,
1697                         .cs_parse = &radeon_uvd_cs_parse,
1698                         .ring_test = &r600_uvd_ring_test,
1699                         .ib_test = &r600_uvd_ib_test,
1700                         .is_lockup = &radeon_ring_test_lockup,
1701                         .get_rptr = &radeon_ring_generic_get_rptr,
1702                         .get_wptr = &radeon_ring_generic_get_wptr,
1703                         .set_wptr = &radeon_ring_generic_set_wptr,
1704                 }
1705         },
1706         .irq = {
1707                 .set = &evergreen_irq_set,
1708                 .process = &evergreen_irq_process,
1709         },
1710         .display = {
1711                 .bandwidth_update = &evergreen_bandwidth_update,
1712                 .get_vblank_counter = &evergreen_get_vblank_counter,
1713                 .wait_for_vblank = &dce4_wait_for_vblank,
1714                 .set_backlight_level = &atombios_set_backlight_level,
1715                 .get_backlight_level = &atombios_get_backlight_level,
1716                 .hdmi_enable = &evergreen_hdmi_enable,
1717                 .hdmi_setmode = &evergreen_hdmi_setmode,
1718         },
1719         .copy = {
1720                 .blit = &r600_copy_blit,
1721                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1722                 .dma = &evergreen_copy_dma,
1723                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1724                 .copy = &evergreen_copy_dma,
1725                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1726         },
1727         .surface = {
1728                 .set_reg = r600_set_surface_reg,
1729                 .clear_reg = r600_clear_surface_reg,
1730         },
1731         .hpd = {
1732                 .init = &evergreen_hpd_init,
1733                 .fini = &evergreen_hpd_fini,
1734                 .sense = &evergreen_hpd_sense,
1735                 .set_polarity = &evergreen_hpd_set_polarity,
1736         },
1737         .pm = {
1738                 .misc = &evergreen_pm_misc,
1739                 .prepare = &evergreen_pm_prepare,
1740                 .finish = &evergreen_pm_finish,
1741                 .init_profile = &btc_pm_init_profile,
1742                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1743                 .get_engine_clock = &radeon_atom_get_engine_clock,
1744                 .set_engine_clock = &radeon_atom_set_engine_clock,
1745                 .get_memory_clock = &radeon_atom_get_memory_clock,
1746                 .set_memory_clock = &radeon_atom_set_memory_clock,
1747                 .get_pcie_lanes = &r600_get_pcie_lanes,
1748                 .set_pcie_lanes = &r600_set_pcie_lanes,
1749                 .set_clock_gating = NULL,
1750                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1751                 .get_temperature = &evergreen_get_temp,
1752         },
1753         .dpm = {
1754                 .init = &btc_dpm_init,
1755                 .setup_asic = &btc_dpm_setup_asic,
1756                 .enable = &btc_dpm_enable,
1757                 .disable = &btc_dpm_disable,
1758                 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1759                 .set_power_state = &btc_dpm_set_power_state,
1760                 .post_set_power_state = &btc_dpm_post_set_power_state,
1761                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1762                 .fini = &btc_dpm_fini,
1763                 .get_sclk = &btc_dpm_get_sclk,
1764                 .get_mclk = &btc_dpm_get_mclk,
1765                 .print_power_state = &rv770_dpm_print_power_state,
1766                 .debugfs_print_current_performance_level = &rv770_dpm_debugfs_print_current_performance_level,
1767                 .force_performance_level = &rv770_dpm_force_performance_level,
1768         },
1769         .pflip = {
1770                 .pre_page_flip = &evergreen_pre_page_flip,
1771                 .page_flip = &evergreen_page_flip,
1772                 .post_page_flip = &evergreen_post_page_flip,
1773         },
1774 };
1775
1776 static struct radeon_asic cayman_asic = {
1777         .init = &cayman_init,
1778         .fini = &cayman_fini,
1779         .suspend = &cayman_suspend,
1780         .resume = &cayman_resume,
1781         .asic_reset = &cayman_asic_reset,
1782         .vga_set_state = &r600_vga_set_state,
1783         .ioctl_wait_idle = r600_ioctl_wait_idle,
1784         .gui_idle = &r600_gui_idle,
1785         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1786         .get_xclk = &rv770_get_xclk,
1787         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1788         .gart = {
1789                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1790                 .set_page = &rs600_gart_set_page,
1791         },
1792         .vm = {
1793                 .init = &cayman_vm_init,
1794                 .fini = &cayman_vm_fini,
1795                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1796                 .set_page = &cayman_vm_set_page,
1797         },
1798         .ring = {
1799                 [RADEON_RING_TYPE_GFX_INDEX] = {
1800                         .ib_execute = &cayman_ring_ib_execute,
1801                         .ib_parse = &evergreen_ib_parse,
1802                         .emit_fence = &cayman_fence_ring_emit,
1803                         .emit_semaphore = &r600_semaphore_ring_emit,
1804                         .cs_parse = &evergreen_cs_parse,
1805                         .ring_test = &r600_ring_test,
1806                         .ib_test = &r600_ib_test,
1807                         .is_lockup = &cayman_gfx_is_lockup,
1808                         .vm_flush = &cayman_vm_flush,
1809                         .get_rptr = &radeon_ring_generic_get_rptr,
1810                         .get_wptr = &radeon_ring_generic_get_wptr,
1811                         .set_wptr = &radeon_ring_generic_set_wptr,
1812                 },
1813                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1814                         .ib_execute = &cayman_ring_ib_execute,
1815                         .ib_parse = &evergreen_ib_parse,
1816                         .emit_fence = &cayman_fence_ring_emit,
1817                         .emit_semaphore = &r600_semaphore_ring_emit,
1818                         .cs_parse = &evergreen_cs_parse,
1819                         .ring_test = &r600_ring_test,
1820                         .ib_test = &r600_ib_test,
1821                         .is_lockup = &cayman_gfx_is_lockup,
1822                         .vm_flush = &cayman_vm_flush,
1823                         .get_rptr = &radeon_ring_generic_get_rptr,
1824                         .get_wptr = &radeon_ring_generic_get_wptr,
1825                         .set_wptr = &radeon_ring_generic_set_wptr,
1826                 },
1827                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1828                         .ib_execute = &cayman_ring_ib_execute,
1829                         .ib_parse = &evergreen_ib_parse,
1830                         .emit_fence = &cayman_fence_ring_emit,
1831                         .emit_semaphore = &r600_semaphore_ring_emit,
1832                         .cs_parse = &evergreen_cs_parse,
1833                         .ring_test = &r600_ring_test,
1834                         .ib_test = &r600_ib_test,
1835                         .is_lockup = &cayman_gfx_is_lockup,
1836                         .vm_flush = &cayman_vm_flush,
1837                         .get_rptr = &radeon_ring_generic_get_rptr,
1838                         .get_wptr = &radeon_ring_generic_get_wptr,
1839                         .set_wptr = &radeon_ring_generic_set_wptr,
1840                 },
1841                 [R600_RING_TYPE_DMA_INDEX] = {
1842                         .ib_execute = &cayman_dma_ring_ib_execute,
1843                         .ib_parse = &evergreen_dma_ib_parse,
1844                         .emit_fence = &evergreen_dma_fence_ring_emit,
1845                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1846                         .cs_parse = &evergreen_dma_cs_parse,
1847                         .ring_test = &r600_dma_ring_test,
1848                         .ib_test = &r600_dma_ib_test,
1849                         .is_lockup = &cayman_dma_is_lockup,
1850                         .vm_flush = &cayman_dma_vm_flush,
1851                         .get_rptr = &radeon_ring_generic_get_rptr,
1852                         .get_wptr = &radeon_ring_generic_get_wptr,
1853                         .set_wptr = &radeon_ring_generic_set_wptr,
1854                 },
1855                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1856                         .ib_execute = &cayman_dma_ring_ib_execute,
1857                         .ib_parse = &evergreen_dma_ib_parse,
1858                         .emit_fence = &evergreen_dma_fence_ring_emit,
1859                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
1860                         .cs_parse = &evergreen_dma_cs_parse,
1861                         .ring_test = &r600_dma_ring_test,
1862                         .ib_test = &r600_dma_ib_test,
1863                         .is_lockup = &cayman_dma_is_lockup,
1864                         .vm_flush = &cayman_dma_vm_flush,
1865                         .get_rptr = &radeon_ring_generic_get_rptr,
1866                         .get_wptr = &radeon_ring_generic_get_wptr,
1867                         .set_wptr = &radeon_ring_generic_set_wptr,
1868                 },
1869                 [R600_RING_TYPE_UVD_INDEX] = {
1870                         .ib_execute = &r600_uvd_ib_execute,
1871                         .emit_fence = &r600_uvd_fence_emit,
1872                         .emit_semaphore = &cayman_uvd_semaphore_emit,
1873                         .cs_parse = &radeon_uvd_cs_parse,
1874                         .ring_test = &r600_uvd_ring_test,
1875                         .ib_test = &r600_uvd_ib_test,
1876                         .is_lockup = &radeon_ring_test_lockup,
1877                         .get_rptr = &radeon_ring_generic_get_rptr,
1878                         .get_wptr = &radeon_ring_generic_get_wptr,
1879                         .set_wptr = &radeon_ring_generic_set_wptr,
1880                 }
1881         },
1882         .irq = {
1883                 .set = &evergreen_irq_set,
1884                 .process = &evergreen_irq_process,
1885         },
1886         .display = {
1887                 .bandwidth_update = &evergreen_bandwidth_update,
1888                 .get_vblank_counter = &evergreen_get_vblank_counter,
1889                 .wait_for_vblank = &dce4_wait_for_vblank,
1890                 .set_backlight_level = &atombios_set_backlight_level,
1891                 .get_backlight_level = &atombios_get_backlight_level,
1892                 .hdmi_enable = &evergreen_hdmi_enable,
1893                 .hdmi_setmode = &evergreen_hdmi_setmode,
1894         },
1895         .copy = {
1896                 .blit = &r600_copy_blit,
1897                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1898                 .dma = &evergreen_copy_dma,
1899                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1900                 .copy = &evergreen_copy_dma,
1901                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1902         },
1903         .surface = {
1904                 .set_reg = r600_set_surface_reg,
1905                 .clear_reg = r600_clear_surface_reg,
1906         },
1907         .hpd = {
1908                 .init = &evergreen_hpd_init,
1909                 .fini = &evergreen_hpd_fini,
1910                 .sense = &evergreen_hpd_sense,
1911                 .set_polarity = &evergreen_hpd_set_polarity,
1912         },
1913         .pm = {
1914                 .misc = &evergreen_pm_misc,
1915                 .prepare = &evergreen_pm_prepare,
1916                 .finish = &evergreen_pm_finish,
1917                 .init_profile = &btc_pm_init_profile,
1918                 .get_dynpm_state = &r600_pm_get_dynpm_state,
1919                 .get_engine_clock = &radeon_atom_get_engine_clock,
1920                 .set_engine_clock = &radeon_atom_set_engine_clock,
1921                 .get_memory_clock = &radeon_atom_get_memory_clock,
1922                 .set_memory_clock = &radeon_atom_set_memory_clock,
1923                 .get_pcie_lanes = &r600_get_pcie_lanes,
1924                 .set_pcie_lanes = &r600_set_pcie_lanes,
1925                 .set_clock_gating = NULL,
1926                 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1927                 .get_temperature = &evergreen_get_temp,
1928         },
1929         .dpm = {
1930                 .init = &ni_dpm_init,
1931                 .setup_asic = &ni_dpm_setup_asic,
1932                 .enable = &ni_dpm_enable,
1933                 .disable = &ni_dpm_disable,
1934                 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1935                 .set_power_state = &ni_dpm_set_power_state,
1936                 .post_set_power_state = &ni_dpm_post_set_power_state,
1937                 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1938                 .fini = &ni_dpm_fini,
1939                 .get_sclk = &ni_dpm_get_sclk,
1940                 .get_mclk = &ni_dpm_get_mclk,
1941                 .print_power_state = &ni_dpm_print_power_state,
1942                 .debugfs_print_current_performance_level = &ni_dpm_debugfs_print_current_performance_level,
1943                 .force_performance_level = &ni_dpm_force_performance_level,
1944         },
1945         .pflip = {
1946                 .pre_page_flip = &evergreen_pre_page_flip,
1947                 .page_flip = &evergreen_page_flip,
1948                 .post_page_flip = &evergreen_post_page_flip,
1949         },
1950 };
1951
1952 static struct radeon_asic trinity_asic = {
1953         .init = &cayman_init,
1954         .fini = &cayman_fini,
1955         .suspend = &cayman_suspend,
1956         .resume = &cayman_resume,
1957         .asic_reset = &cayman_asic_reset,
1958         .vga_set_state = &r600_vga_set_state,
1959         .ioctl_wait_idle = r600_ioctl_wait_idle,
1960         .gui_idle = &r600_gui_idle,
1961         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1962         .get_xclk = &r600_get_xclk,
1963         .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1964         .gart = {
1965                 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1966                 .set_page = &rs600_gart_set_page,
1967         },
1968         .vm = {
1969                 .init = &cayman_vm_init,
1970                 .fini = &cayman_vm_fini,
1971                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1972                 .set_page = &cayman_vm_set_page,
1973         },
1974         .ring = {
1975                 [RADEON_RING_TYPE_GFX_INDEX] = {
1976                         .ib_execute = &cayman_ring_ib_execute,
1977                         .ib_parse = &evergreen_ib_parse,
1978                         .emit_fence = &cayman_fence_ring_emit,
1979                         .emit_semaphore = &r600_semaphore_ring_emit,
1980                         .cs_parse = &evergreen_cs_parse,
1981                         .ring_test = &r600_ring_test,
1982                         .ib_test = &r600_ib_test,
1983                         .is_lockup = &cayman_gfx_is_lockup,
1984                         .vm_flush = &cayman_vm_flush,
1985                         .get_rptr = &radeon_ring_generic_get_rptr,
1986                         .get_wptr = &radeon_ring_generic_get_wptr,
1987                         .set_wptr = &radeon_ring_generic_set_wptr,
1988                 },
1989                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1990                         .ib_execute = &cayman_ring_ib_execute,
1991                         .ib_parse = &evergreen_ib_parse,
1992                         .emit_fence = &cayman_fence_ring_emit,
1993                         .emit_semaphore = &r600_semaphore_ring_emit,
1994                         .cs_parse = &evergreen_cs_parse,
1995                         .ring_test = &r600_ring_test,
1996                         .ib_test = &r600_ib_test,
1997                         .is_lockup = &cayman_gfx_is_lockup,
1998                         .vm_flush = &cayman_vm_flush,
1999                         .get_rptr = &radeon_ring_generic_get_rptr,
2000                         .get_wptr = &radeon_ring_generic_get_wptr,
2001                         .set_wptr = &radeon_ring_generic_set_wptr,
2002                 },
2003                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2004                         .ib_execute = &cayman_ring_ib_execute,
2005                         .ib_parse = &evergreen_ib_parse,
2006                         .emit_fence = &cayman_fence_ring_emit,
2007                         .emit_semaphore = &r600_semaphore_ring_emit,
2008                         .cs_parse = &evergreen_cs_parse,
2009                         .ring_test = &r600_ring_test,
2010                         .ib_test = &r600_ib_test,
2011                         .is_lockup = &cayman_gfx_is_lockup,
2012                         .vm_flush = &cayman_vm_flush,
2013                         .get_rptr = &radeon_ring_generic_get_rptr,
2014                         .get_wptr = &radeon_ring_generic_get_wptr,
2015                         .set_wptr = &radeon_ring_generic_set_wptr,
2016                 },
2017                 [R600_RING_TYPE_DMA_INDEX] = {
2018                         .ib_execute = &cayman_dma_ring_ib_execute,
2019                         .ib_parse = &evergreen_dma_ib_parse,
2020                         .emit_fence = &evergreen_dma_fence_ring_emit,
2021                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
2022                         .cs_parse = &evergreen_dma_cs_parse,
2023                         .ring_test = &r600_dma_ring_test,
2024                         .ib_test = &r600_dma_ib_test,
2025                         .is_lockup = &cayman_dma_is_lockup,
2026                         .vm_flush = &cayman_dma_vm_flush,
2027                         .get_rptr = &radeon_ring_generic_get_rptr,
2028                         .get_wptr = &radeon_ring_generic_get_wptr,
2029                         .set_wptr = &radeon_ring_generic_set_wptr,
2030                 },
2031                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2032                         .ib_execute = &cayman_dma_ring_ib_execute,
2033                         .ib_parse = &evergreen_dma_ib_parse,
2034                         .emit_fence = &evergreen_dma_fence_ring_emit,
2035                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
2036                         .cs_parse = &evergreen_dma_cs_parse,
2037                         .ring_test = &r600_dma_ring_test,
2038                         .ib_test = &r600_dma_ib_test,
2039                         .is_lockup = &cayman_dma_is_lockup,
2040                         .vm_flush = &cayman_dma_vm_flush,
2041                         .get_rptr = &radeon_ring_generic_get_rptr,
2042                         .get_wptr = &radeon_ring_generic_get_wptr,
2043                         .set_wptr = &radeon_ring_generic_set_wptr,
2044                 },
2045                 [R600_RING_TYPE_UVD_INDEX] = {
2046                         .ib_execute = &r600_uvd_ib_execute,
2047                         .emit_fence = &r600_uvd_fence_emit,
2048                         .emit_semaphore = &cayman_uvd_semaphore_emit,
2049                         .cs_parse = &radeon_uvd_cs_parse,
2050                         .ring_test = &r600_uvd_ring_test,
2051                         .ib_test = &r600_uvd_ib_test,
2052                         .is_lockup = &radeon_ring_test_lockup,
2053                         .get_rptr = &radeon_ring_generic_get_rptr,
2054                         .get_wptr = &radeon_ring_generic_get_wptr,
2055                         .set_wptr = &radeon_ring_generic_set_wptr,
2056                 }
2057         },
2058         .irq = {
2059                 .set = &evergreen_irq_set,
2060                 .process = &evergreen_irq_process,
2061         },
2062         .display = {
2063                 .bandwidth_update = &dce6_bandwidth_update,
2064                 .get_vblank_counter = &evergreen_get_vblank_counter,
2065                 .wait_for_vblank = &dce4_wait_for_vblank,
2066                 .set_backlight_level = &atombios_set_backlight_level,
2067                 .get_backlight_level = &atombios_get_backlight_level,
2068         },
2069         .copy = {
2070                 .blit = &r600_copy_blit,
2071                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2072                 .dma = &evergreen_copy_dma,
2073                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2074                 .copy = &evergreen_copy_dma,
2075                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2076         },
2077         .surface = {
2078                 .set_reg = r600_set_surface_reg,
2079                 .clear_reg = r600_clear_surface_reg,
2080         },
2081         .hpd = {
2082                 .init = &evergreen_hpd_init,
2083                 .fini = &evergreen_hpd_fini,
2084                 .sense = &evergreen_hpd_sense,
2085                 .set_polarity = &evergreen_hpd_set_polarity,
2086         },
2087         .pm = {
2088                 .misc = &evergreen_pm_misc,
2089                 .prepare = &evergreen_pm_prepare,
2090                 .finish = &evergreen_pm_finish,
2091                 .init_profile = &sumo_pm_init_profile,
2092                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2093                 .get_engine_clock = &radeon_atom_get_engine_clock,
2094                 .set_engine_clock = &radeon_atom_set_engine_clock,
2095                 .get_memory_clock = NULL,
2096                 .set_memory_clock = NULL,
2097                 .get_pcie_lanes = NULL,
2098                 .set_pcie_lanes = NULL,
2099                 .set_clock_gating = NULL,
2100                 .set_uvd_clocks = &sumo_set_uvd_clocks,
2101                 .get_temperature = &tn_get_temp,
2102         },
2103         .dpm = {
2104                 .init = &trinity_dpm_init,
2105                 .setup_asic = &trinity_dpm_setup_asic,
2106                 .enable = &trinity_dpm_enable,
2107                 .disable = &trinity_dpm_disable,
2108                 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
2109                 .set_power_state = &trinity_dpm_set_power_state,
2110                 .post_set_power_state = &trinity_dpm_post_set_power_state,
2111                 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
2112                 .fini = &trinity_dpm_fini,
2113                 .get_sclk = &trinity_dpm_get_sclk,
2114                 .get_mclk = &trinity_dpm_get_mclk,
2115                 .print_power_state = &trinity_dpm_print_power_state,
2116                 .debugfs_print_current_performance_level = &trinity_dpm_debugfs_print_current_performance_level,
2117         },
2118         .pflip = {
2119                 .pre_page_flip = &evergreen_pre_page_flip,
2120                 .page_flip = &evergreen_page_flip,
2121                 .post_page_flip = &evergreen_post_page_flip,
2122         },
2123 };
2124
2125 static struct radeon_asic si_asic = {
2126         .init = &si_init,
2127         .fini = &si_fini,
2128         .suspend = &si_suspend,
2129         .resume = &si_resume,
2130         .asic_reset = &si_asic_reset,
2131         .vga_set_state = &r600_vga_set_state,
2132         .ioctl_wait_idle = r600_ioctl_wait_idle,
2133         .gui_idle = &r600_gui_idle,
2134         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2135         .get_xclk = &si_get_xclk,
2136         .get_gpu_clock_counter = &si_get_gpu_clock_counter,
2137         .gart = {
2138                 .tlb_flush = &si_pcie_gart_tlb_flush,
2139                 .set_page = &rs600_gart_set_page,
2140         },
2141         .vm = {
2142                 .init = &si_vm_init,
2143                 .fini = &si_vm_fini,
2144                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2145                 .set_page = &si_vm_set_page,
2146         },
2147         .ring = {
2148                 [RADEON_RING_TYPE_GFX_INDEX] = {
2149                         .ib_execute = &si_ring_ib_execute,
2150                         .ib_parse = &si_ib_parse,
2151                         .emit_fence = &si_fence_ring_emit,
2152                         .emit_semaphore = &r600_semaphore_ring_emit,
2153                         .cs_parse = NULL,
2154                         .ring_test = &r600_ring_test,
2155                         .ib_test = &r600_ib_test,
2156                         .is_lockup = &si_gfx_is_lockup,
2157                         .vm_flush = &si_vm_flush,
2158                         .get_rptr = &radeon_ring_generic_get_rptr,
2159                         .get_wptr = &radeon_ring_generic_get_wptr,
2160                         .set_wptr = &radeon_ring_generic_set_wptr,
2161                 },
2162                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2163                         .ib_execute = &si_ring_ib_execute,
2164                         .ib_parse = &si_ib_parse,
2165                         .emit_fence = &si_fence_ring_emit,
2166                         .emit_semaphore = &r600_semaphore_ring_emit,
2167                         .cs_parse = NULL,
2168                         .ring_test = &r600_ring_test,
2169                         .ib_test = &r600_ib_test,
2170                         .is_lockup = &si_gfx_is_lockup,
2171                         .vm_flush = &si_vm_flush,
2172                         .get_rptr = &radeon_ring_generic_get_rptr,
2173                         .get_wptr = &radeon_ring_generic_get_wptr,
2174                         .set_wptr = &radeon_ring_generic_set_wptr,
2175                 },
2176                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2177                         .ib_execute = &si_ring_ib_execute,
2178                         .ib_parse = &si_ib_parse,
2179                         .emit_fence = &si_fence_ring_emit,
2180                         .emit_semaphore = &r600_semaphore_ring_emit,
2181                         .cs_parse = NULL,
2182                         .ring_test = &r600_ring_test,
2183                         .ib_test = &r600_ib_test,
2184                         .is_lockup = &si_gfx_is_lockup,
2185                         .vm_flush = &si_vm_flush,
2186                         .get_rptr = &radeon_ring_generic_get_rptr,
2187                         .get_wptr = &radeon_ring_generic_get_wptr,
2188                         .set_wptr = &radeon_ring_generic_set_wptr,
2189                 },
2190                 [R600_RING_TYPE_DMA_INDEX] = {
2191                         .ib_execute = &cayman_dma_ring_ib_execute,
2192                         .ib_parse = &evergreen_dma_ib_parse,
2193                         .emit_fence = &evergreen_dma_fence_ring_emit,
2194                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
2195                         .cs_parse = NULL,
2196                         .ring_test = &r600_dma_ring_test,
2197                         .ib_test = &r600_dma_ib_test,
2198                         .is_lockup = &si_dma_is_lockup,
2199                         .vm_flush = &si_dma_vm_flush,
2200                         .get_rptr = &radeon_ring_generic_get_rptr,
2201                         .get_wptr = &radeon_ring_generic_get_wptr,
2202                         .set_wptr = &radeon_ring_generic_set_wptr,
2203                 },
2204                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2205                         .ib_execute = &cayman_dma_ring_ib_execute,
2206                         .ib_parse = &evergreen_dma_ib_parse,
2207                         .emit_fence = &evergreen_dma_fence_ring_emit,
2208                         .emit_semaphore = &r600_dma_semaphore_ring_emit,
2209                         .cs_parse = NULL,
2210                         .ring_test = &r600_dma_ring_test,
2211                         .ib_test = &r600_dma_ib_test,
2212                         .is_lockup = &si_dma_is_lockup,
2213                         .vm_flush = &si_dma_vm_flush,
2214                         .get_rptr = &radeon_ring_generic_get_rptr,
2215                         .get_wptr = &radeon_ring_generic_get_wptr,
2216                         .set_wptr = &radeon_ring_generic_set_wptr,
2217                 },
2218                 [R600_RING_TYPE_UVD_INDEX] = {
2219                         .ib_execute = &r600_uvd_ib_execute,
2220                         .emit_fence = &r600_uvd_fence_emit,
2221                         .emit_semaphore = &cayman_uvd_semaphore_emit,
2222                         .cs_parse = &radeon_uvd_cs_parse,
2223                         .ring_test = &r600_uvd_ring_test,
2224                         .ib_test = &r600_uvd_ib_test,
2225                         .is_lockup = &radeon_ring_test_lockup,
2226                         .get_rptr = &radeon_ring_generic_get_rptr,
2227                         .get_wptr = &radeon_ring_generic_get_wptr,
2228                         .set_wptr = &radeon_ring_generic_set_wptr,
2229                 }
2230         },
2231         .irq = {
2232                 .set = &si_irq_set,
2233                 .process = &si_irq_process,
2234         },
2235         .display = {
2236                 .bandwidth_update = &dce6_bandwidth_update,
2237                 .get_vblank_counter = &evergreen_get_vblank_counter,
2238                 .wait_for_vblank = &dce4_wait_for_vblank,
2239                 .set_backlight_level = &atombios_set_backlight_level,
2240                 .get_backlight_level = &atombios_get_backlight_level,
2241         },
2242         .copy = {
2243                 .blit = NULL,
2244                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2245                 .dma = &si_copy_dma,
2246                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2247                 .copy = &si_copy_dma,
2248                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2249         },
2250         .surface = {
2251                 .set_reg = r600_set_surface_reg,
2252                 .clear_reg = r600_clear_surface_reg,
2253         },
2254         .hpd = {
2255                 .init = &evergreen_hpd_init,
2256                 .fini = &evergreen_hpd_fini,
2257                 .sense = &evergreen_hpd_sense,
2258                 .set_polarity = &evergreen_hpd_set_polarity,
2259         },
2260         .pm = {
2261                 .misc = &evergreen_pm_misc,
2262                 .prepare = &evergreen_pm_prepare,
2263                 .finish = &evergreen_pm_finish,
2264                 .init_profile = &sumo_pm_init_profile,
2265                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2266                 .get_engine_clock = &radeon_atom_get_engine_clock,
2267                 .set_engine_clock = &radeon_atom_set_engine_clock,
2268                 .get_memory_clock = &radeon_atom_get_memory_clock,
2269                 .set_memory_clock = &radeon_atom_set_memory_clock,
2270                 .get_pcie_lanes = &r600_get_pcie_lanes,
2271                 .set_pcie_lanes = &r600_set_pcie_lanes,
2272                 .set_clock_gating = NULL,
2273                 .set_uvd_clocks = &si_set_uvd_clocks,
2274                 .get_temperature = &si_get_temp,
2275         },
2276         .dpm = {
2277                 .init = &si_dpm_init,
2278                 .setup_asic = &si_dpm_setup_asic,
2279                 .enable = &si_dpm_enable,
2280                 .disable = &si_dpm_disable,
2281                 .pre_set_power_state = &si_dpm_pre_set_power_state,
2282                 .set_power_state = &si_dpm_set_power_state,
2283                 .post_set_power_state = &si_dpm_post_set_power_state,
2284                 .display_configuration_changed = &si_dpm_display_configuration_changed,
2285                 .fini = &si_dpm_fini,
2286                 .get_sclk = &ni_dpm_get_sclk,
2287                 .get_mclk = &ni_dpm_get_mclk,
2288                 .print_power_state = &ni_dpm_print_power_state,
2289                 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
2290         },
2291         .pflip = {
2292                 .pre_page_flip = &evergreen_pre_page_flip,
2293                 .page_flip = &evergreen_page_flip,
2294                 .post_page_flip = &evergreen_post_page_flip,
2295         },
2296 };
2297
2298 static struct radeon_asic ci_asic = {
2299         .init = &cik_init,
2300         .fini = &cik_fini,
2301         .suspend = &cik_suspend,
2302         .resume = &cik_resume,
2303         .asic_reset = &cik_asic_reset,
2304         .vga_set_state = &r600_vga_set_state,
2305         .ioctl_wait_idle = NULL,
2306         .gui_idle = &r600_gui_idle,
2307         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2308         .get_xclk = &cik_get_xclk,
2309         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2310         .gart = {
2311                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2312                 .set_page = &rs600_gart_set_page,
2313         },
2314         .vm = {
2315                 .init = &cik_vm_init,
2316                 .fini = &cik_vm_fini,
2317                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2318                 .set_page = &cik_vm_set_page,
2319         },
2320         .ring = {
2321                 [RADEON_RING_TYPE_GFX_INDEX] = {
2322                         .ib_execute = &cik_ring_ib_execute,
2323                         .ib_parse = &cik_ib_parse,
2324                         .emit_fence = &cik_fence_gfx_ring_emit,
2325                         .emit_semaphore = &cik_semaphore_ring_emit,
2326                         .cs_parse = NULL,
2327                         .ring_test = &cik_ring_test,
2328                         .ib_test = &cik_ib_test,
2329                         .is_lockup = &cik_gfx_is_lockup,
2330                         .vm_flush = &cik_vm_flush,
2331                         .get_rptr = &radeon_ring_generic_get_rptr,
2332                         .get_wptr = &radeon_ring_generic_get_wptr,
2333                         .set_wptr = &radeon_ring_generic_set_wptr,
2334                 },
2335                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2336                         .ib_execute = &cik_ring_ib_execute,
2337                         .ib_parse = &cik_ib_parse,
2338                         .emit_fence = &cik_fence_compute_ring_emit,
2339                         .emit_semaphore = &cik_semaphore_ring_emit,
2340                         .cs_parse = NULL,
2341                         .ring_test = &cik_ring_test,
2342                         .ib_test = &cik_ib_test,
2343                         .is_lockup = &cik_gfx_is_lockup,
2344                         .vm_flush = &cik_vm_flush,
2345                         .get_rptr = &cik_compute_ring_get_rptr,
2346                         .get_wptr = &cik_compute_ring_get_wptr,
2347                         .set_wptr = &cik_compute_ring_set_wptr,
2348                 },
2349                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2350                         .ib_execute = &cik_ring_ib_execute,
2351                         .ib_parse = &cik_ib_parse,
2352                         .emit_fence = &cik_fence_compute_ring_emit,
2353                         .emit_semaphore = &cik_semaphore_ring_emit,
2354                         .cs_parse = NULL,
2355                         .ring_test = &cik_ring_test,
2356                         .ib_test = &cik_ib_test,
2357                         .is_lockup = &cik_gfx_is_lockup,
2358                         .vm_flush = &cik_vm_flush,
2359                         .get_rptr = &cik_compute_ring_get_rptr,
2360                         .get_wptr = &cik_compute_ring_get_wptr,
2361                         .set_wptr = &cik_compute_ring_set_wptr,
2362                 },
2363                 [R600_RING_TYPE_DMA_INDEX] = {
2364                         .ib_execute = &cik_sdma_ring_ib_execute,
2365                         .ib_parse = &cik_ib_parse,
2366                         .emit_fence = &cik_sdma_fence_ring_emit,
2367                         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2368                         .cs_parse = NULL,
2369                         .ring_test = &cik_sdma_ring_test,
2370                         .ib_test = &cik_sdma_ib_test,
2371                         .is_lockup = &cik_sdma_is_lockup,
2372                         .vm_flush = &cik_dma_vm_flush,
2373                         .get_rptr = &radeon_ring_generic_get_rptr,
2374                         .get_wptr = &radeon_ring_generic_get_wptr,
2375                         .set_wptr = &radeon_ring_generic_set_wptr,
2376                 },
2377                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2378                         .ib_execute = &cik_sdma_ring_ib_execute,
2379                         .ib_parse = &cik_ib_parse,
2380                         .emit_fence = &cik_sdma_fence_ring_emit,
2381                         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2382                         .cs_parse = NULL,
2383                         .ring_test = &cik_sdma_ring_test,
2384                         .ib_test = &cik_sdma_ib_test,
2385                         .is_lockup = &cik_sdma_is_lockup,
2386                         .vm_flush = &cik_dma_vm_flush,
2387                         .get_rptr = &radeon_ring_generic_get_rptr,
2388                         .get_wptr = &radeon_ring_generic_get_wptr,
2389                         .set_wptr = &radeon_ring_generic_set_wptr,
2390                 },
2391                 [R600_RING_TYPE_UVD_INDEX] = {
2392                         .ib_execute = &r600_uvd_ib_execute,
2393                         .emit_fence = &r600_uvd_fence_emit,
2394                         .emit_semaphore = &cayman_uvd_semaphore_emit,
2395                         .cs_parse = &radeon_uvd_cs_parse,
2396                         .ring_test = &r600_uvd_ring_test,
2397                         .ib_test = &r600_uvd_ib_test,
2398                         .is_lockup = &radeon_ring_test_lockup,
2399                         .get_rptr = &radeon_ring_generic_get_rptr,
2400                         .get_wptr = &radeon_ring_generic_get_wptr,
2401                         .set_wptr = &radeon_ring_generic_set_wptr,
2402                 }
2403         },
2404         .irq = {
2405                 .set = &cik_irq_set,
2406                 .process = &cik_irq_process,
2407         },
2408         .display = {
2409                 .bandwidth_update = &dce8_bandwidth_update,
2410                 .get_vblank_counter = &evergreen_get_vblank_counter,
2411                 .wait_for_vblank = &dce4_wait_for_vblank,
2412         },
2413         .copy = {
2414                 .blit = NULL,
2415                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2416                 .dma = &cik_copy_dma,
2417                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2418                 .copy = &cik_copy_dma,
2419                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2420         },
2421         .surface = {
2422                 .set_reg = r600_set_surface_reg,
2423                 .clear_reg = r600_clear_surface_reg,
2424         },
2425         .hpd = {
2426                 .init = &evergreen_hpd_init,
2427                 .fini = &evergreen_hpd_fini,
2428                 .sense = &evergreen_hpd_sense,
2429                 .set_polarity = &evergreen_hpd_set_polarity,
2430         },
2431         .pm = {
2432                 .misc = &evergreen_pm_misc,
2433                 .prepare = &evergreen_pm_prepare,
2434                 .finish = &evergreen_pm_finish,
2435                 .init_profile = &sumo_pm_init_profile,
2436                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2437                 .get_engine_clock = &radeon_atom_get_engine_clock,
2438                 .set_engine_clock = &radeon_atom_set_engine_clock,
2439                 .get_memory_clock = &radeon_atom_get_memory_clock,
2440                 .set_memory_clock = &radeon_atom_set_memory_clock,
2441                 .get_pcie_lanes = NULL,
2442                 .set_pcie_lanes = NULL,
2443                 .set_clock_gating = NULL,
2444                 .set_uvd_clocks = &cik_set_uvd_clocks,
2445         },
2446         .pflip = {
2447                 .pre_page_flip = &evergreen_pre_page_flip,
2448                 .page_flip = &evergreen_page_flip,
2449                 .post_page_flip = &evergreen_post_page_flip,
2450         },
2451 };
2452
2453 static struct radeon_asic kv_asic = {
2454         .init = &cik_init,
2455         .fini = &cik_fini,
2456         .suspend = &cik_suspend,
2457         .resume = &cik_resume,
2458         .asic_reset = &cik_asic_reset,
2459         .vga_set_state = &r600_vga_set_state,
2460         .ioctl_wait_idle = NULL,
2461         .gui_idle = &r600_gui_idle,
2462         .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2463         .get_xclk = &cik_get_xclk,
2464         .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2465         .gart = {
2466                 .tlb_flush = &cik_pcie_gart_tlb_flush,
2467                 .set_page = &rs600_gart_set_page,
2468         },
2469         .vm = {
2470                 .init = &cik_vm_init,
2471                 .fini = &cik_vm_fini,
2472                 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2473                 .set_page = &cik_vm_set_page,
2474         },
2475         .ring = {
2476                 [RADEON_RING_TYPE_GFX_INDEX] = {
2477                         .ib_execute = &cik_ring_ib_execute,
2478                         .ib_parse = &cik_ib_parse,
2479                         .emit_fence = &cik_fence_gfx_ring_emit,
2480                         .emit_semaphore = &cik_semaphore_ring_emit,
2481                         .cs_parse = NULL,
2482                         .ring_test = &cik_ring_test,
2483                         .ib_test = &cik_ib_test,
2484                         .is_lockup = &cik_gfx_is_lockup,
2485                         .vm_flush = &cik_vm_flush,
2486                         .get_rptr = &radeon_ring_generic_get_rptr,
2487                         .get_wptr = &radeon_ring_generic_get_wptr,
2488                         .set_wptr = &radeon_ring_generic_set_wptr,
2489                 },
2490                 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2491                         .ib_execute = &cik_ring_ib_execute,
2492                         .ib_parse = &cik_ib_parse,
2493                         .emit_fence = &cik_fence_compute_ring_emit,
2494                         .emit_semaphore = &cik_semaphore_ring_emit,
2495                         .cs_parse = NULL,
2496                         .ring_test = &cik_ring_test,
2497                         .ib_test = &cik_ib_test,
2498                         .is_lockup = &cik_gfx_is_lockup,
2499                         .vm_flush = &cik_vm_flush,
2500                         .get_rptr = &cik_compute_ring_get_rptr,
2501                         .get_wptr = &cik_compute_ring_get_wptr,
2502                         .set_wptr = &cik_compute_ring_set_wptr,
2503                 },
2504                 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2505                         .ib_execute = &cik_ring_ib_execute,
2506                         .ib_parse = &cik_ib_parse,
2507                         .emit_fence = &cik_fence_compute_ring_emit,
2508                         .emit_semaphore = &cik_semaphore_ring_emit,
2509                         .cs_parse = NULL,
2510                         .ring_test = &cik_ring_test,
2511                         .ib_test = &cik_ib_test,
2512                         .is_lockup = &cik_gfx_is_lockup,
2513                         .vm_flush = &cik_vm_flush,
2514                         .get_rptr = &cik_compute_ring_get_rptr,
2515                         .get_wptr = &cik_compute_ring_get_wptr,
2516                         .set_wptr = &cik_compute_ring_set_wptr,
2517                 },
2518                 [R600_RING_TYPE_DMA_INDEX] = {
2519                         .ib_execute = &cik_sdma_ring_ib_execute,
2520                         .ib_parse = &cik_ib_parse,
2521                         .emit_fence = &cik_sdma_fence_ring_emit,
2522                         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2523                         .cs_parse = NULL,
2524                         .ring_test = &cik_sdma_ring_test,
2525                         .ib_test = &cik_sdma_ib_test,
2526                         .is_lockup = &cik_sdma_is_lockup,
2527                         .vm_flush = &cik_dma_vm_flush,
2528                         .get_rptr = &radeon_ring_generic_get_rptr,
2529                         .get_wptr = &radeon_ring_generic_get_wptr,
2530                         .set_wptr = &radeon_ring_generic_set_wptr,
2531                 },
2532                 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2533                         .ib_execute = &cik_sdma_ring_ib_execute,
2534                         .ib_parse = &cik_ib_parse,
2535                         .emit_fence = &cik_sdma_fence_ring_emit,
2536                         .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2537                         .cs_parse = NULL,
2538                         .ring_test = &cik_sdma_ring_test,
2539                         .ib_test = &cik_sdma_ib_test,
2540                         .is_lockup = &cik_sdma_is_lockup,
2541                         .vm_flush = &cik_dma_vm_flush,
2542                         .get_rptr = &radeon_ring_generic_get_rptr,
2543                         .get_wptr = &radeon_ring_generic_get_wptr,
2544                         .set_wptr = &radeon_ring_generic_set_wptr,
2545                 },
2546                 [R600_RING_TYPE_UVD_INDEX] = {
2547                         .ib_execute = &r600_uvd_ib_execute,
2548                         .emit_fence = &r600_uvd_fence_emit,
2549                         .emit_semaphore = &cayman_uvd_semaphore_emit,
2550                         .cs_parse = &radeon_uvd_cs_parse,
2551                         .ring_test = &r600_uvd_ring_test,
2552                         .ib_test = &r600_uvd_ib_test,
2553                         .is_lockup = &radeon_ring_test_lockup,
2554                         .get_rptr = &radeon_ring_generic_get_rptr,
2555                         .get_wptr = &radeon_ring_generic_get_wptr,
2556                         .set_wptr = &radeon_ring_generic_set_wptr,
2557                 }
2558         },
2559         .irq = {
2560                 .set = &cik_irq_set,
2561                 .process = &cik_irq_process,
2562         },
2563         .display = {
2564                 .bandwidth_update = &dce8_bandwidth_update,
2565                 .get_vblank_counter = &evergreen_get_vblank_counter,
2566                 .wait_for_vblank = &dce4_wait_for_vblank,
2567         },
2568         .copy = {
2569                 .blit = NULL,
2570                 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2571                 .dma = &cik_copy_dma,
2572                 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2573                 .copy = &cik_copy_dma,
2574                 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2575         },
2576         .surface = {
2577                 .set_reg = r600_set_surface_reg,
2578                 .clear_reg = r600_clear_surface_reg,
2579         },
2580         .hpd = {
2581                 .init = &evergreen_hpd_init,
2582                 .fini = &evergreen_hpd_fini,
2583                 .sense = &evergreen_hpd_sense,
2584                 .set_polarity = &evergreen_hpd_set_polarity,
2585         },
2586         .pm = {
2587                 .misc = &evergreen_pm_misc,
2588                 .prepare = &evergreen_pm_prepare,
2589                 .finish = &evergreen_pm_finish,
2590                 .init_profile = &sumo_pm_init_profile,
2591                 .get_dynpm_state = &r600_pm_get_dynpm_state,
2592                 .get_engine_clock = &radeon_atom_get_engine_clock,
2593                 .set_engine_clock = &radeon_atom_set_engine_clock,
2594                 .get_memory_clock = &radeon_atom_get_memory_clock,
2595                 .set_memory_clock = &radeon_atom_set_memory_clock,
2596                 .get_pcie_lanes = NULL,
2597                 .set_pcie_lanes = NULL,
2598                 .set_clock_gating = NULL,
2599                 .set_uvd_clocks = &cik_set_uvd_clocks,
2600         },
2601         .pflip = {
2602                 .pre_page_flip = &evergreen_pre_page_flip,
2603                 .page_flip = &evergreen_page_flip,
2604                 .post_page_flip = &evergreen_post_page_flip,
2605         },
2606 };
2607
2608 /**
2609  * radeon_asic_init - register asic specific callbacks
2610  *
2611  * @rdev: radeon device pointer
2612  *
2613  * Registers the appropriate asic specific callbacks for each
2614  * chip family.  Also sets other asics specific info like the number
2615  * of crtcs and the register aperture accessors (all asics).
2616  * Returns 0 for success.
2617  */
2618 int radeon_asic_init(struct radeon_device *rdev)
2619 {
2620         radeon_register_accessor_init(rdev);
2621
2622         /* set the number of crtcs */
2623         if (rdev->flags & RADEON_SINGLE_CRTC)
2624                 rdev->num_crtc = 1;
2625         else
2626                 rdev->num_crtc = 2;
2627
2628         rdev->has_uvd = false;
2629
2630         switch (rdev->family) {
2631         case CHIP_R100:
2632         case CHIP_RV100:
2633         case CHIP_RS100:
2634         case CHIP_RV200:
2635         case CHIP_RS200:
2636                 rdev->asic = &r100_asic;
2637                 break;
2638         case CHIP_R200:
2639         case CHIP_RV250:
2640         case CHIP_RS300:
2641         case CHIP_RV280:
2642                 rdev->asic = &r200_asic;
2643                 break;
2644         case CHIP_R300:
2645         case CHIP_R350:
2646         case CHIP_RV350:
2647         case CHIP_RV380:
2648                 if (rdev->flags & RADEON_IS_PCIE)
2649                         rdev->asic = &r300_asic_pcie;
2650                 else
2651                         rdev->asic = &r300_asic;
2652                 break;
2653         case CHIP_R420:
2654         case CHIP_R423:
2655         case CHIP_RV410:
2656                 rdev->asic = &r420_asic;
2657                 /* handle macs */
2658                 if (rdev->bios == NULL) {
2659                         rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2660                         rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2661                         rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2662                         rdev->asic->pm.set_memory_clock = NULL;
2663                         rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2664                 }
2665                 break;
2666         case CHIP_RS400:
2667         case CHIP_RS480:
2668                 rdev->asic = &rs400_asic;
2669                 break;
2670         case CHIP_RS600:
2671                 rdev->asic = &rs600_asic;
2672                 break;
2673         case CHIP_RS690:
2674         case CHIP_RS740:
2675                 rdev->asic = &rs690_asic;
2676                 break;
2677         case CHIP_RV515:
2678                 rdev->asic = &rv515_asic;
2679                 break;
2680         case CHIP_R520:
2681         case CHIP_RV530:
2682         case CHIP_RV560:
2683         case CHIP_RV570:
2684         case CHIP_R580:
2685                 rdev->asic = &r520_asic;
2686                 break;
2687         case CHIP_R600:
2688                 rdev->asic = &r600_asic;
2689                 break;
2690         case CHIP_RV610:
2691         case CHIP_RV630:
2692         case CHIP_RV620:
2693         case CHIP_RV635:
2694         case CHIP_RV670:
2695                 rdev->asic = &rv6xx_asic;
2696                 rdev->has_uvd = true;
2697                 break;
2698         case CHIP_RS780:
2699         case CHIP_RS880:
2700                 rdev->asic = &rs780_asic;
2701                 rdev->has_uvd = true;
2702                 break;
2703         case CHIP_RV770:
2704         case CHIP_RV730:
2705         case CHIP_RV710:
2706         case CHIP_RV740:
2707                 rdev->asic = &rv770_asic;
2708                 rdev->has_uvd = true;
2709                 break;
2710         case CHIP_CEDAR:
2711         case CHIP_REDWOOD:
2712         case CHIP_JUNIPER:
2713         case CHIP_CYPRESS:
2714         case CHIP_HEMLOCK:
2715                 /* set num crtcs */
2716                 if (rdev->family == CHIP_CEDAR)
2717                         rdev->num_crtc = 4;
2718                 else
2719                         rdev->num_crtc = 6;
2720                 rdev->asic = &evergreen_asic;
2721                 rdev->has_uvd = true;
2722                 break;
2723         case CHIP_PALM:
2724         case CHIP_SUMO:
2725         case CHIP_SUMO2:
2726                 rdev->asic = &sumo_asic;
2727                 rdev->has_uvd = true;
2728                 break;
2729         case CHIP_BARTS:
2730         case CHIP_TURKS:
2731         case CHIP_CAICOS:
2732                 /* set num crtcs */
2733                 if (rdev->family == CHIP_CAICOS)
2734                         rdev->num_crtc = 4;
2735                 else
2736                         rdev->num_crtc = 6;
2737                 rdev->asic = &btc_asic;
2738                 rdev->has_uvd = true;
2739                 break;
2740         case CHIP_CAYMAN:
2741                 rdev->asic = &cayman_asic;
2742                 /* set num crtcs */
2743                 rdev->num_crtc = 6;
2744                 rdev->has_uvd = true;
2745                 break;
2746         case CHIP_ARUBA:
2747                 rdev->asic = &trinity_asic;
2748                 /* set num crtcs */
2749                 rdev->num_crtc = 4;
2750                 rdev->has_uvd = true;
2751                 break;
2752         case CHIP_TAHITI:
2753         case CHIP_PITCAIRN:
2754         case CHIP_VERDE:
2755         case CHIP_OLAND:
2756         case CHIP_HAINAN:
2757                 rdev->asic = &si_asic;
2758                 /* set num crtcs */
2759                 if (rdev->family == CHIP_HAINAN)
2760                         rdev->num_crtc = 0;
2761                 else if (rdev->family == CHIP_OLAND)
2762                         rdev->num_crtc = 2;
2763                 else
2764                         rdev->num_crtc = 6;
2765                 if (rdev->family == CHIP_HAINAN)
2766                         rdev->has_uvd = false;
2767                 else
2768                         rdev->has_uvd = true;
2769                 break;
2770         case CHIP_BONAIRE:
2771                 rdev->asic = &ci_asic;
2772                 rdev->num_crtc = 6;
2773                 break;
2774         case CHIP_KAVERI:
2775         case CHIP_KABINI:
2776                 rdev->asic = &kv_asic;
2777                 /* set num crtcs */
2778                 if (rdev->family == CHIP_KAVERI)
2779                         rdev->num_crtc = 4;
2780                 else
2781                         rdev->num_crtc = 2;
2782                 break;
2783         default:
2784                 /* FIXME: not supported yet */
2785                 return -EINVAL;
2786         }
2787
2788         if (rdev->flags & RADEON_IS_IGP) {
2789                 rdev->asic->pm.get_memory_clock = NULL;
2790                 rdev->asic->pm.set_memory_clock = NULL;
2791         }
2792
2793         return 0;
2794 }
2795