arch/arm/plat-omap/sram.c

   1 /*
   2  * linux/arch/arm/plat-omap/sram.c
   3  *
   4  * OMAP SRAM detection and management
   5  *
   6  * Copyright (C) 2005 Nokia Corporation
   7  * Written by Tony Lindgren <tony@atomide.com>
   8  *
   9  * Copyright (C) 2009 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License version 2 as
  14  * published by the Free Software Foundation.
  15  */
  16 #undef DEBUG
  17
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/io.h>
  22
  23 #include <asm/tlb.h>
  24 #include <asm/cacheflush.h>
  25
  26 #include <asm/mach/map.h>
  27
  28 #include <plat/sram.h>
  29 #include <plat/board.h>
  30 #include <plat/cpu.h>
  31
  32 #include "sram.h"
  33
  34 /* XXX These "sideways" includes are a sign that something is wrong */
  35 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
  36 # include "../mach-omap2/prm2xxx_3xxx.h"
  37 # include "../mach-omap2/sdrc.h"
  38 #endif
  39
  40 #define OMAP1_SRAM_PA           0x20000000
  41 #define OMAP2_SRAM_PUB_PA       (OMAP2_SRAM_PA + 0xf800)
  42 #define OMAP3_SRAM_PUB_PA       (OMAP3_SRAM_PA + 0x8000)
  43 #ifdef CONFIG_OMAP4_ERRATA_I688
  44 #define OMAP4_SRAM_PUB_PA       OMAP4_SRAM_PA
  45 #else
  46 #define OMAP4_SRAM_PUB_PA       (OMAP4_SRAM_PA + 0x4000)
  47 #endif
  48
  49 #if defined(CONFIG_ARCH_OMAP2PLUS)
  50 #define SRAM_BOOTLOADER_SZ      0x00
  51 #else
  52 #define SRAM_BOOTLOADER_SZ      0x80
  53 #endif
  54
  55 #define OMAP24XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68005048)
  56 #define OMAP24XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68005050)
  57 #define OMAP24XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68005058)
  58
  59 #define OMAP34XX_VA_REQINFOPERM0        OMAP2_L3_IO_ADDRESS(0x68012848)
  60 #define OMAP34XX_VA_READPERM0           OMAP2_L3_IO_ADDRESS(0x68012850)
  61 #define OMAP34XX_VA_WRITEPERM0          OMAP2_L3_IO_ADDRESS(0x68012858)
  62 #define OMAP34XX_VA_ADDR_MATCH2         OMAP2_L3_IO_ADDRESS(0x68012880)
  63 #define OMAP34XX_VA_SMS_RG_ATT0         OMAP2_L3_IO_ADDRESS(0x6C000048)
  64
  65 #define GP_DEVICE               0x300
  66
  67 #define ROUND_DOWN(value,boundary)      ((value) & (~((boundary)-1)))
  68
  69 static unsigned long omap_sram_start;
  70 static void __iomem *omap_sram_base;
  71 static unsigned long omap_sram_size;
  72 static void __iomem *omap_sram_ceil;
  73
  74 /*
  75  * Depending on the target RAMFS firewall setup, the public usable amount of
  76  * SRAM varies.  The default accessible size for all device types is 2k. A GP
  77  * device allows ARM11 but not other initiators for full size. This
  78  * functionality seems ok until some nice security API happens.
  79  */
  80 static int is_sram_locked(void)
  81 {
  82         if (OMAP2_DEVICE_TYPE_GP == omap_type()) {
  83                 /* RAMFW: R/W access to all initiators for all qualifier sets */
  84                 if (cpu_is_omap242x()) {
  85                         __raw_writel(0xFF, OMAP24XX_VA_REQINFOPERM0); /* all q-vects */
  86                         __raw_writel(0xCFDE, OMAP24XX_VA_READPERM0);  /* all i-read */
  87                         __raw_writel(0xCFDE, OMAP24XX_VA_WRITEPERM0); /* all i-write */
  88                 }
  89                 if (cpu_is_omap34xx()) {
  90                         __raw_writel(0xFFFF, OMAP34XX_VA_REQINFOPERM0); /* all q-vects */
  91                         __raw_writel(0xFFFF, OMAP34XX_VA_READPERM0);  /* all i-read */
  92                         __raw_writel(0xFFFF, OMAP34XX_VA_WRITEPERM0); /* all i-write */
  93                         __raw_writel(0x0, OMAP34XX_VA_ADDR_MATCH2);
  94                         __raw_writel(0xFFFFFFFF, OMAP34XX_VA_SMS_RG_ATT0);
  95                 }
  96                 return 0;
  97         } else
  98                 return 1; /* assume locked with no PPA or security driver */
  99 }
 100
 101 /*
 102  * The amount of SRAM depends on the core type.
 103  * Note that we cannot try to test for SRAM here because writes
 104  * to secure SRAM will hang the system. Also the SRAM is not
 105  * yet mapped at this point.
 106  */
 107 static void __init omap_detect_sram(void)
 108 {
 109         if (cpu_class_is_omap2()) {
 110                 if (is_sram_locked()) {
 111                         if (cpu_is_omap34xx()) {
 112                                 omap_sram_start = OMAP3_SRAM_PUB_PA;
 113                                 if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) ||
 114                                     (omap_type() == OMAP2_DEVICE_TYPE_SEC)) {
 115                                         omap_sram_size = 0x7000; /* 28K */
 116                                 } else {
 117                                         omap_sram_size = 0x8000; /* 32K */
 118                                 }
 119                         } else if (cpu_is_omap44xx()) {
 120                                 omap_sram_start = OMAP4_SRAM_PUB_PA;
 121                                 omap_sram_size = 0xa000; /* 40K */
 122                         } else {
 123                                 omap_sram_start = OMAP2_SRAM_PUB_PA;
 124                                 omap_sram_size = 0x800; /* 2K */
 125                         }
 126                 } else {
 127                         if (cpu_is_omap34xx()) {
 128                                 omap_sram_start = OMAP3_SRAM_PA;
 129                                 omap_sram_size = 0x10000; /* 64K */
 130                         } else if (cpu_is_omap44xx()) {
 131                                 omap_sram_start = OMAP4_SRAM_PA;
 132                                 omap_sram_size = 0xe000; /* 56K */
 133                         } else {
 134                                 omap_sram_start = OMAP2_SRAM_PA;
 135                                 if (cpu_is_omap242x())
 136                                         omap_sram_size = 0xa0000; /* 640K */
 137                                 else if (cpu_is_omap243x())
 138                                         omap_sram_size = 0x10000; /* 64K */
 139                         }
 140                 }
 141         } else {
 142                 omap_sram_start = OMAP1_SRAM_PA;
 143
 144                 if (cpu_is_omap7xx())
 145                         omap_sram_size = 0x32000;       /* 200K */
 146                 else if (cpu_is_omap15xx())
 147                         omap_sram_size = 0x30000;       /* 192K */
 148                 else if (cpu_is_omap1610() || cpu_is_omap1621() ||
 149                      cpu_is_omap1710())
 150                         omap_sram_size = 0x4000;        /* 16K */
 151                 else if (cpu_is_omap1611())
 152                         omap_sram_size = SZ_256K;
 153                 else {
 154                         pr_err("Could not detect SRAM size\n");
 155                         omap_sram_size = 0x4000;
 156                 }
 157         }
 158 }
 159
 160 /*
 161  * Note that we cannot use ioremap for SRAM, as clock init needs SRAM early.
 162  */
 163 static void __init omap_map_sram(void)
 164 {
 165         int cached = 1;
 166
 167         if (omap_sram_size == 0)
 168                 return;
 169
 170 #ifdef CONFIG_OMAP4_ERRATA_I688
 171                 omap_sram_start += PAGE_SIZE;
 172                 omap_sram_size -= SZ_16K;
 173 #endif
 174         if (cpu_is_omap34xx()) {
 175                 /*
 176                  * SRAM must be marked as non-cached on OMAP3 since the
 177                  * CORE DPLL M2 divider change code (in SRAM) runs with the
 178                  * SDRAM controller disabled, and if it is marked cached,
 179                  * the ARM may attempt to write cache lines back to SDRAM
 180                  * which will cause the system to hang.
 181                  */
 182                 cached = 0;
 183         }
 184
 185         omap_sram_start = ROUND_DOWN(omap_sram_start, PAGE_SIZE);
 186         omap_sram_base = __arm_ioremap_exec(omap_sram_start, omap_sram_size,
 187                                                 cached);
 188         if (!omap_sram_base) {
 189                 pr_err("SRAM: Could not map\n");
 190                 return;
 191         }
 192
 193         omap_sram_ceil = omap_sram_base + omap_sram_size;
 194
 195         /*
 196          * Looks like we need to preserve some bootloader code at the
 197          * beginning of SRAM for jumping to flash for reboot to work...
 198          */
 199         memset((void *)omap_sram_base + SRAM_BOOTLOADER_SZ, 0,
 200                omap_sram_size - SRAM_BOOTLOADER_SZ);
 201 }
 202
 203 /*
 204  * Memory allocator for SRAM: calculates the new ceiling address
 205  * for pushing a function using the fncpy API.
 206  *
 207  * Note that fncpy requires the returned address to be aligned
 208  * to an 8-byte boundary.
 209  */
 210 void *omap_sram_push_address(unsigned long size)
 211 {
 212         unsigned long available, new_ceil = (unsigned long)omap_sram_ceil;
 213
 214         available = omap_sram_ceil - (omap_sram_base + SRAM_BOOTLOADER_SZ);
 215
 216         if (size > available) {
 217                 pr_err("Not enough space in SRAM\n");
 218                 return NULL;
 219         }
 220
 221         new_ceil -= size;
 222         new_ceil = ROUND_DOWN(new_ceil, FNCPY_ALIGN);
 223         omap_sram_ceil = IOMEM(new_ceil);
 224
 225         return (void *)omap_sram_ceil;
 226 }
 227
 228 #ifdef CONFIG_ARCH_OMAP1
 229
 230 static void (*_omap_sram_reprogram_clock)(u32 dpllctl, u32 ckctl);
 231
 232 void omap_sram_reprogram_clock(u32 dpllctl, u32 ckctl)
 233 {
 234         BUG_ON(!_omap_sram_reprogram_clock);
 235         _omap_sram_reprogram_clock(dpllctl, ckctl);
 236 }
 237
 238 static int __init omap1_sram_init(void)
 239 {
 240         _omap_sram_reprogram_clock =
 241                         omap_sram_push(omap1_sram_reprogram_clock,
 242                                         omap1_sram_reprogram_clock_sz);
 243
 244         return 0;
 245 }
 246
 247 #else
 248 #define omap1_sram_init()       do {} while (0)
 249 #endif
 250
 251 #if defined(CONFIG_ARCH_OMAP2)
 252
 253 static void (*_omap2_sram_ddr_init)(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 254                               u32 base_cs, u32 force_unlock);
 255
 256 void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
 257                    u32 base_cs, u32 force_unlock)
 258 {
 259         BUG_ON(!_omap2_sram_ddr_init);
 260         _omap2_sram_ddr_init(slow_dll_ctrl, fast_dll_ctrl,
 261                              base_cs, force_unlock);
 262 }
 263
 264 static void (*_omap2_sram_reprogram_sdrc)(u32 perf_level, u32 dll_val,
 265                                           u32 mem_type);
 266
 267 void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val, u32 mem_type)
 268 {
 269         BUG_ON(!_omap2_sram_reprogram_sdrc);
 270         _omap2_sram_reprogram_sdrc(perf_level, dll_val, mem_type);
 271 }
 272
 273 static u32 (*_omap2_set_prcm)(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
 274
 275 u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass)
 276 {
 277         BUG_ON(!_omap2_set_prcm);
 278         return _omap2_set_prcm(dpll_ctrl_val, sdrc_rfr_val, bypass);
 279 }
 280 #endif
 281
 282 #ifdef CONFIG_SOC_OMAP2420
 283 static int __init omap242x_sram_init(void)
 284 {
 285         _omap2_sram_ddr_init = omap_sram_push(omap242x_sram_ddr_init,
 286                                         omap242x_sram_ddr_init_sz);
 287
 288         _omap2_sram_reprogram_sdrc = omap_sram_push(omap242x_sram_reprogram_sdrc,
 289                                             omap242x_sram_reprogram_sdrc_sz);
 290
 291         _omap2_set_prcm = omap_sram_push(omap242x_sram_set_prcm,
 292                                          omap242x_sram_set_prcm_sz);
 293
 294         return 0;
 295 }
 296 #else
 297 static inline int omap242x_sram_init(void)
 298 {
 299         return 0;
 300 }
 301 #endif
 302
 303 #ifdef CONFIG_SOC_OMAP2430
 304 static int __init omap243x_sram_init(void)
 305 {
 306         _omap2_sram_ddr_init = omap_sram_push(omap243x_sram_ddr_init,
 307                                         omap243x_sram_ddr_init_sz);
 308
 309         _omap2_sram_reprogram_sdrc = omap_sram_push(omap243x_sram_reprogram_sdrc,
 310                                             omap243x_sram_reprogram_sdrc_sz);
 311
 312         _omap2_set_prcm = omap_sram_push(omap243x_sram_set_prcm,
 313                                          omap243x_sram_set_prcm_sz);
 314
 315         return 0;
 316 }
 317 #else
 318 static inline int omap243x_sram_init(void)
 319 {
 320         return 0;
 321 }
 322 #endif
 323
 324 #ifdef CONFIG_ARCH_OMAP3
 325
 326 static u32 (*_omap3_sram_configure_core_dpll)(
 327                         u32 m2, u32 unlock_dll, u32 f, u32 inc,
 328                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 329                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 330                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 331                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
 332
 333 u32 omap3_configure_core_dpll(u32 m2, u32 unlock_dll, u32 f, u32 inc,
 334                         u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
 335                         u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
 336                         u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
 337                         u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1)
 338 {
 339         BUG_ON(!_omap3_sram_configure_core_dpll);
 340         return _omap3_sram_configure_core_dpll(
 341                         m2, unlock_dll, f, inc,
 342                         sdrc_rfr_ctrl_0, sdrc_actim_ctrl_a_0,
 343                         sdrc_actim_ctrl_b_0, sdrc_mr_0,
 344                         sdrc_rfr_ctrl_1, sdrc_actim_ctrl_a_1,
 345                         sdrc_actim_ctrl_b_1, sdrc_mr_1);
 346 }
 347
 348 #ifdef CONFIG_PM
 349 void omap3_sram_restore_context(void)
 350 {
 351         omap_sram_ceil = omap_sram_base + omap_sram_size;
 352
 353         _omap3_sram_configure_core_dpll =
 354                 omap_sram_push(omap3_sram_configure_core_dpll,
 355                                omap3_sram_configure_core_dpll_sz);
 356         omap_push_sram_idle();
 357 }
 358 #endif /* CONFIG_PM */
 359
 360 #endif /* CONFIG_ARCH_OMAP3 */
 361
 362 static inline int omap34xx_sram_init(void)
 363 {
 364 #if defined(CONFIG_ARCH_OMAP3) && defined(CONFIG_PM)
 365         omap3_sram_restore_context();
 366 #endif
 367         return 0;
 368 }
 369
 370 int __init omap_sram_init(void)
 371 {
 372         omap_detect_sram();
 373         omap_map_sram();
 374
 375         if (!(cpu_class_is_omap2()))
 376                 omap1_sram_init();
 377         else if (cpu_is_omap242x())
 378                 omap242x_sram_init();
 379         else if (cpu_is_omap2430())
 380                 omap243x_sram_init();
 381         else if (cpu_is_omap34xx())
 382                 omap34xx_sram_init();
 383
 384         return 0;
 385 }