drivers/usb/host/xhci-mem.c

   1 /*
   2  * xHCI host controller driver
   3  *
   4  * Copyright (C) 2008 Intel Corp.
   5  *
   6  * Author: Sarah Sharp
   7  * Some code borrowed from the Linux EHCI driver.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16  * for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software Foundation,
  20  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/usb.h>
  24 #include <linux/pci.h>
  25 #include <linux/slab.h>
  26 #include <linux/dmapool.h>
  27
  28 #include "xhci.h"
  29
  30 /*
  31  * Allocates a generic ring segment from the ring pool, sets the dma address,
  32  * initializes the segment to zero, and sets the private next pointer to NULL.
  33  *
  34  * Section 4.11.1.1:
  35  * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  36  */
  37 static struct xhci_segment *xhci_segment_alloc(struct xhci_hcd *xhci,
  38                                         unsigned int cycle_state, gfp_t flags)
  39 {
  40         struct xhci_segment *seg;
  41         dma_addr_t      dma;
  42         int             i;
  43
  44         seg = kzalloc(sizeof *seg, flags);
  45         if (!seg)
  46                 return NULL;
  47
  48         seg->trbs = dma_pool_alloc(xhci->segment_pool, flags, &dma);
  49         if (!seg->trbs) {
  50                 kfree(seg);
  51                 return NULL;
  52         }
  53
  54         memset(seg->trbs, 0, TRB_SEGMENT_SIZE);
  55         /* If the cycle state is 0, set the cycle bit to 1 for all the TRBs */
  56         if (cycle_state == 0) {
  57                 for (i = 0; i < TRBS_PER_SEGMENT; i++)
  58                         seg->trbs[i].link.control |= TRB_CYCLE;
  59         }
  60         seg->dma = dma;
  61         seg->next = NULL;
  62
  63         return seg;
  64 }
  65
  66 static void xhci_segment_free(struct xhci_hcd *xhci, struct xhci_segment *seg)
  67 {
  68         if (seg->trbs) {
  69                 dma_pool_free(xhci->segment_pool, seg->trbs, seg->dma);
  70                 seg->trbs = NULL;
  71         }
  72         kfree(seg);
  73 }
  74
  75 static void xhci_free_segments_for_ring(struct xhci_hcd *xhci,
  76                                 struct xhci_segment *first)
  77 {
  78         struct xhci_segment *seg;
  79
  80         seg = first->next;
  81         while (seg != first) {
  82                 struct xhci_segment *next = seg->next;
  83                 xhci_segment_free(xhci, seg);
  84                 seg = next;
  85         }
  86         xhci_segment_free(xhci, first);
  87 }
  88
  89 /*
  90  * Make the prev segment point to the next segment.
  91  *
  92  * Change the last TRB in the prev segment to be a Link TRB which points to the
  93  * DMA address of the next segment.  The caller needs to set any Link TRB
  94  * related flags, such as End TRB, Toggle Cycle, and no snoop.
  95  */
  96 static void xhci_link_segments(struct xhci_hcd *xhci, struct xhci_segment *prev,
  97                 struct xhci_segment *next, enum xhci_ring_type type)
  98 {
  99         u32 val;
 100
 101         if (!prev || !next)
 102                 return;
 103         prev->next = next;
 104         if (type != TYPE_EVENT) {
 105                 prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr =
 106                         cpu_to_le64(next->dma);
 107
 108                 /* Set the last TRB in the segment to have a TRB type ID of Link TRB */
 109                 val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
 110                 val &= ~TRB_TYPE_BITMASK;
 111                 val |= TRB_TYPE(TRB_LINK);
 112                 /* Always set the chain bit with 0.95 hardware */
 113                 /* Set chain bit for isoc rings on AMD 0.96 host */
 114                 if (xhci_link_trb_quirk(xhci) ||
 115                                 (type == TYPE_ISOC &&
 116                                  (xhci->quirks & XHCI_AMD_0x96_HOST)))
 117                         val |= TRB_CHAIN;
 118                 prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
 119         }
 120 }
 121
 122 /*
 123  * Link the ring to the new segments.
 124  * Set Toggle Cycle for the new ring if needed.
 125  */
 126 static void xhci_link_rings(struct xhci_hcd *xhci, struct xhci_ring *ring,
 127                 struct xhci_segment *first, struct xhci_segment *last,
 128                 unsigned int num_segs)
 129 {
 130         struct xhci_segment *next;
 131
 132         if (!ring || !first || !last)
 133                 return;
 134
 135         next = ring->enq_seg->next;
 136         xhci_link_segments(xhci, ring->enq_seg, first, ring->type);
 137         xhci_link_segments(xhci, last, next, ring->type);
 138         ring->num_segs += num_segs;
 139         ring->num_trbs_free += (TRBS_PER_SEGMENT - 1) * num_segs;
 140
 141         if (ring->type != TYPE_EVENT && ring->enq_seg == ring->last_seg) {
 142                 ring->last_seg->trbs[TRBS_PER_SEGMENT-1].link.control
 143                         &= ~cpu_to_le32(LINK_TOGGLE);
 144                 last->trbs[TRBS_PER_SEGMENT-1].link.control
 145                         |= cpu_to_le32(LINK_TOGGLE);
 146                 ring->last_seg = last;
 147         }
 148 }
 149
 150 /* XXX: Do we need the hcd structure in all these functions? */
 151 void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring)
 152 {
 153         if (!ring)
 154                 return;
 155
 156         if (ring->first_seg)
 157                 xhci_free_segments_for_ring(xhci, ring->first_seg);
 158
 159         kfree(ring);
 160 }
 161
 162 static void xhci_initialize_ring_info(struct xhci_ring *ring,
 163                                         unsigned int cycle_state)
 164 {
 165         /* The ring is empty, so the enqueue pointer == dequeue pointer */
 166         ring->enqueue = ring->first_seg->trbs;
 167         ring->enq_seg = ring->first_seg;
 168         ring->dequeue = ring->enqueue;
 169         ring->deq_seg = ring->first_seg;
 170         /* The ring is initialized to 0. The producer must write 1 to the cycle
 171          * bit to handover ownership of the TRB, so PCS = 1.  The consumer must
 172          * compare CCS to the cycle bit to check ownership, so CCS = 1.
 173          *
 174          * New rings are initialized with cycle state equal to 1; if we are
 175          * handling ring expansion, set the cycle state equal to the old ring.
 176          */
 177         ring->cycle_state = cycle_state;
 178         /* Not necessary for new rings, but needed for re-initialized rings */
 179         ring->enq_updates = 0;
 180         ring->deq_updates = 0;
 181
 182         /*
 183          * Each segment has a link TRB, and leave an extra TRB for SW
 184          * accounting purpose
 185          */
 186         ring->num_trbs_free = ring->num_segs * (TRBS_PER_SEGMENT - 1) - 1;
 187 }
 188
 189 /* Allocate segments and link them for a ring */
 190 static int xhci_alloc_segments_for_ring(struct xhci_hcd *xhci,
 191                 struct xhci_segment **first, struct xhci_segment **last,
 192                 unsigned int num_segs, unsigned int cycle_state,
 193                 enum xhci_ring_type type, gfp_t flags)
 194 {
 195         struct xhci_segment *prev;
 196
 197         prev = xhci_segment_alloc(xhci, cycle_state, flags);
 198         if (!prev)
 199                 return -ENOMEM;
 200         num_segs--;
 201
 202         *first = prev;
 203         while (num_segs > 0) {
 204                 struct xhci_segment     *next;
 205
 206                 next = xhci_segment_alloc(xhci, cycle_state, flags);
 207                 if (!next) {
 208                         prev = *first;
 209                         while (prev) {
 210                                 next = prev->next;
 211                                 xhci_segment_free(xhci, prev);
 212                                 prev = next;
 213                         }
 214                         return -ENOMEM;
 215                 }
 216                 xhci_link_segments(xhci, prev, next, type);
 217
 218                 prev = next;
 219                 num_segs--;
 220         }
 221         xhci_link_segments(xhci, prev, *first, type);
 222         *last = prev;
 223
 224         return 0;
 225 }
 226
 227 /**
 228  * Create a new ring with zero or more segments.
 229  *
 230  * Link each segment together into a ring.
 231  * Set the end flag and the cycle toggle bit on the last segment.
 232  * See section 4.9.1 and figures 15 and 16.
 233  */
 234 static struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
 235                 unsigned int num_segs, unsigned int cycle_state,
 236                 enum xhci_ring_type type, gfp_t flags)
 237 {
 238         struct xhci_ring        *ring;
 239         int ret;
 240
 241         ring = kzalloc(sizeof *(ring), flags);
 242         if (!ring)
 243                 return NULL;
 244
 245         ring->num_segs = num_segs;
 246         INIT_LIST_HEAD(&ring->td_list);
 247         ring->type = type;
 248         if (num_segs == 0)
 249                 return ring;
 250
 251         ret = xhci_alloc_segments_for_ring(xhci, &ring->first_seg,
 252                         &ring->last_seg, num_segs, cycle_state, type, flags);
 253         if (ret)
 254                 goto fail;
 255
 256         /* Only event ring does not use link TRB */
 257         if (type != TYPE_EVENT) {
 258                 /* See section 4.9.2.1 and 6.4.4.1 */
 259                 ring->last_seg->trbs[TRBS_PER_SEGMENT - 1].link.control |=
 260                         cpu_to_le32(LINK_TOGGLE);
 261         }
 262         xhci_initialize_ring_info(ring, cycle_state);
 263         return ring;
 264
 265 fail:
 266         kfree(ring);
 267         return NULL;
 268 }
 269
 270 void xhci_free_or_cache_endpoint_ring(struct xhci_hcd *xhci,
 271                 struct xhci_virt_device *virt_dev,
 272                 unsigned int ep_index)
 273 {
 274         int rings_cached;
 275
 276         rings_cached = virt_dev->num_rings_cached;
 277         if (rings_cached < XHCI_MAX_RINGS_CACHED) {
 278                 virt_dev->ring_cache[rings_cached] =
 279                         virt_dev->eps[ep_index].ring;
 280                 virt_dev->num_rings_cached++;
 281                 xhci_dbg(xhci, "Cached old ring, "
 282                                 "%d ring%s cached\n",
 283                                 virt_dev->num_rings_cached,
 284                                 (virt_dev->num_rings_cached > 1) ? "s" : "");
 285         } else {
 286                 xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
 287                 xhci_dbg(xhci, "Ring cache full (%d rings), "
 288                                 "freeing ring\n",
 289                                 virt_dev->num_rings_cached);
 290         }
 291         virt_dev->eps[ep_index].ring = NULL;
 292 }
 293
 294 /* Zero an endpoint ring (except for link TRBs) and move the enqueue and dequeue
 295  * pointers to the beginning of the ring.
 296  */
 297 static void xhci_reinit_cached_ring(struct xhci_hcd *xhci,
 298                         struct xhci_ring *ring, unsigned int cycle_state,
 299                         enum xhci_ring_type type)
 300 {
 301         struct xhci_segment     *seg = ring->first_seg;
 302         int i;
 303
 304         do {
 305                 memset(seg->trbs, 0,
 306                                 sizeof(union xhci_trb)*TRBS_PER_SEGMENT);
 307                 if (cycle_state == 0) {
 308                         for (i = 0; i < TRBS_PER_SEGMENT; i++)
 309                                 seg->trbs[i].link.control |= TRB_CYCLE;
 310                 }
 311                 /* All endpoint rings have link TRBs */
 312                 xhci_link_segments(xhci, seg, seg->next, type);
 313                 seg = seg->next;
 314         } while (seg != ring->first_seg);
 315         ring->type = type;
 316         xhci_initialize_ring_info(ring, cycle_state);
 317         /* td list should be empty since all URBs have been cancelled,
 318          * but just in case...
 319          */
 320         INIT_LIST_HEAD(&ring->td_list);
 321 }
 322
 323 /*
 324  * Expand an existing ring.
 325  * Look for a cached ring or allocate a new ring which has same segment numbers
 326  * and link the two rings.
 327  */
 328 int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
 329                                 unsigned int num_trbs, gfp_t flags)
 330 {
 331         struct xhci_segment     *first;
 332         struct xhci_segment     *last;
 333         unsigned int            num_segs;
 334         unsigned int            num_segs_needed;
 335         int                     ret;
 336
 337         num_segs_needed = (num_trbs + (TRBS_PER_SEGMENT - 1) - 1) /
 338                                 (TRBS_PER_SEGMENT - 1);
 339
 340         /* Allocate number of segments we needed, or double the ring size */
 341         num_segs = ring->num_segs > num_segs_needed ?
 342                         ring->num_segs : num_segs_needed;
 343
 344         ret = xhci_alloc_segments_for_ring(xhci, &first, &last,
 345                         num_segs, ring->cycle_state, ring->type, flags);
 346         if (ret)
 347                 return -ENOMEM;
 348
 349         xhci_link_rings(xhci, ring, first, last, num_segs);
 350         xhci_dbg(xhci, "ring expansion succeed, now has %d segments\n",
 351                         ring->num_segs);
 352
 353         return 0;
 354 }
 355
 356 #define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
 357
 358 static struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
 359                                                     int type, gfp_t flags)
 360 {
 361         struct xhci_container_ctx *ctx;
 362
 363         if ((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT))
 364                 return NULL;
 365
 366         ctx = kzalloc(sizeof(*ctx), flags);
 367         if (!ctx)
 368                 return NULL;
 369
 370         ctx->type = type;
 371         ctx->size = HCC_64BYTE_CONTEXT(xhci->hcc_params) ? 2048 : 1024;
 372         if (type == XHCI_CTX_TYPE_INPUT)
 373                 ctx->size += CTX_SIZE(xhci->hcc_params);
 374
 375         ctx->bytes = dma_pool_alloc(xhci->device_pool, flags, &ctx->dma);
 376         if (!ctx->bytes) {
 377                 kfree(ctx);
 378                 return NULL;
 379         }
 380         memset(ctx->bytes, 0, ctx->size);
 381         return ctx;
 382 }
 383
 384 static void xhci_free_container_ctx(struct xhci_hcd *xhci,
 385                              struct xhci_container_ctx *ctx)
 386 {
 387         if (!ctx)
 388                 return;
 389         dma_pool_free(xhci->device_pool, ctx->bytes, ctx->dma);
 390         kfree(ctx);
 391 }
 392
 393 struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
 394                                               struct xhci_container_ctx *ctx)
 395 {
 396         if (ctx->type != XHCI_CTX_TYPE_INPUT)
 397                 return NULL;
 398
 399         return (struct xhci_input_control_ctx *)ctx->bytes;
 400 }
 401
 402 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci,
 403                                         struct xhci_container_ctx *ctx)
 404 {
 405         if (ctx->type == XHCI_CTX_TYPE_DEVICE)
 406                 return (struct xhci_slot_ctx *)ctx->bytes;
 407
 408         return (struct xhci_slot_ctx *)
 409                 (ctx->bytes + CTX_SIZE(xhci->hcc_params));
 410 }
 411
 412 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci,
 413                                     struct xhci_container_ctx *ctx,
 414                                     unsigned int ep_index)
 415 {
 416         /* increment ep index by offset of start of ep ctx array */
 417         ep_index++;
 418         if (ctx->type == XHCI_CTX_TYPE_INPUT)
 419                 ep_index++;
 420
 421         return (struct xhci_ep_ctx *)
 422                 (ctx->bytes + (ep_index * CTX_SIZE(xhci->hcc_params)));
 423 }
 424
 425
 426 /***************** Streams structures manipulation *************************/
 427
 428 static void xhci_free_stream_ctx(struct xhci_hcd *xhci,
 429                 unsigned int num_stream_ctxs,
 430                 struct xhci_stream_ctx *stream_ctx, dma_addr_t dma)
 431 {
 432         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 433
 434         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 435                 dma_free_coherent(&pdev->dev,
 436                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 437                                 stream_ctx, dma);
 438         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 439                 return dma_pool_free(xhci->small_streams_pool,
 440                                 stream_ctx, dma);
 441         else
 442                 return dma_pool_free(xhci->medium_streams_pool,
 443                                 stream_ctx, dma);
 444 }
 445
 446 /*
 447  * The stream context array for each endpoint with bulk streams enabled can
 448  * vary in size, based on:
 449  *  - how many streams the endpoint supports,
 450  *  - the maximum primary stream array size the host controller supports,
 451  *  - and how many streams the device driver asks for.
 452  *
 453  * The stream context array must be a power of 2, and can be as small as
 454  * 64 bytes or as large as 1MB.
 455  */
 456 static struct xhci_stream_ctx *xhci_alloc_stream_ctx(struct xhci_hcd *xhci,
 457                 unsigned int num_stream_ctxs, dma_addr_t *dma,
 458                 gfp_t mem_flags)
 459 {
 460         struct pci_dev *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
 461
 462         if (num_stream_ctxs > MEDIUM_STREAM_ARRAY_SIZE)
 463                 return dma_alloc_coherent(&pdev->dev,
 464                                 sizeof(struct xhci_stream_ctx)*num_stream_ctxs,
 465                                 dma, mem_flags);
 466         else if (num_stream_ctxs <= SMALL_STREAM_ARRAY_SIZE)
 467                 return dma_pool_alloc(xhci->small_streams_pool,
 468                                 mem_flags, dma);
 469         else
 470                 return dma_pool_alloc(xhci->medium_streams_pool,
 471                                 mem_flags, dma);
 472 }
 473
 474 struct xhci_ring *xhci_dma_to_transfer_ring(
 475                 struct xhci_virt_ep *ep,
 476                 u64 address)
 477 {
 478         if (ep->ep_state & EP_HAS_STREAMS)
 479                 return radix_tree_lookup(&ep->stream_info->trb_address_map,
 480                                 address >> TRB_SEGMENT_SHIFT);
 481         return ep->ring;
 482 }
 483
 484 /* Only use this when you know stream_info is valid */
 485 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 486 static struct xhci_ring *dma_to_stream_ring(
 487                 struct xhci_stream_info *stream_info,
 488                 u64 address)
 489 {
 490         return radix_tree_lookup(&stream_info->trb_address_map,
 491                         address >> TRB_SEGMENT_SHIFT);
 492 }
 493 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 494
 495 struct xhci_ring *xhci_stream_id_to_ring(
 496                 struct xhci_virt_device *dev,
 497                 unsigned int ep_index,
 498                 unsigned int stream_id)
 499 {
 500         struct xhci_virt_ep *ep = &dev->eps[ep_index];
 501
 502         if (stream_id == 0)
 503                 return ep->ring;
 504         if (!ep->stream_info)
 505                 return NULL;
 506
 507         if (stream_id > ep->stream_info->num_streams)
 508                 return NULL;
 509         return ep->stream_info->stream_rings[stream_id];
 510 }
 511
 512 #ifdef CONFIG_USB_XHCI_HCD_DEBUGGING
 513 static int xhci_test_radix_tree(struct xhci_hcd *xhci,
 514                 unsigned int num_streams,
 515                 struct xhci_stream_info *stream_info)
 516 {
 517         u32 cur_stream;
 518         struct xhci_ring *cur_ring;
 519         u64 addr;
 520
 521         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 522                 struct xhci_ring *mapped_ring;
 523                 int trb_size = sizeof(union xhci_trb);
 524
 525                 cur_ring = stream_info->stream_rings[cur_stream];
 526                 for (addr = cur_ring->first_seg->dma;
 527                                 addr < cur_ring->first_seg->dma + TRB_SEGMENT_SIZE;
 528                                 addr += trb_size) {
 529                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 530                         if (cur_ring != mapped_ring) {
 531                                 xhci_warn(xhci, "WARN: DMA address 0x%08llx "
 532                                                 "didn't map to stream ID %u; "
 533                                                 "mapped to ring %p\n",
 534                                                 (unsigned long long) addr,
 535                                                 cur_stream,
 536                                                 mapped_ring);
 537                                 return -EINVAL;
 538                         }
 539                 }
 540                 /* One TRB after the end of the ring segment shouldn't return a
 541                  * pointer to the current ring (although it may be a part of a
 542                  * different ring).
 543                  */
 544                 mapped_ring = dma_to_stream_ring(stream_info, addr);
 545                 if (mapped_ring != cur_ring) {
 546                         /* One TRB before should also fail */
 547                         addr = cur_ring->first_seg->dma - trb_size;
 548                         mapped_ring = dma_to_stream_ring(stream_info, addr);
 549                 }
 550                 if (mapped_ring == cur_ring) {
 551                         xhci_warn(xhci, "WARN: Bad DMA address 0x%08llx "
 552                                         "mapped to valid stream ID %u; "
 553                                         "mapped ring = %p\n",
 554                                         (unsigned long long) addr,
 555                                         cur_stream,
 556                                         mapped_ring);
 557                         return -EINVAL;
 558                 }
 559         }
 560         return 0;
 561 }
 562 #endif  /* CONFIG_USB_XHCI_HCD_DEBUGGING */
 563
 564 /*
 565  * Change an endpoint's internal structure so it supports stream IDs.  The
 566  * number of requested streams includes stream 0, which cannot be used by device
 567  * drivers.
 568  *
 569  * The number of stream contexts in the stream context array may be bigger than
 570  * the number of streams the driver wants to use.  This is because the number of
 571  * stream context array entries must be a power of two.
 572  *
 573  * We need a radix tree for mapping physical addresses of TRBs to which stream
 574  * ID they belong to.  We need to do this because the host controller won't tell
 575  * us which stream ring the TRB came from.  We could store the stream ID in an
 576  * event data TRB, but that doesn't help us for the cancellation case, since the
 577  * endpoint may stop before it reaches that event data TRB.
 578  *
 579  * The radix tree maps the upper portion of the TRB DMA address to a ring
 580  * segment that has the same upper portion of DMA addresses.  For example, say I
 581  * have segments of size 1KB, that are always 64-byte aligned.  A segment may
 582  * start at 0x10c91000 and end at 0x10c913f0.  If I use the upper 10 bits, the
 583  * key to the stream ID is 0x43244.  I can use the DMA address of the TRB to
 584  * pass the radix tree a key to get the right stream ID:
 585  *
 586  *      0x10c90fff >> 10 = 0x43243
 587  *      0x10c912c0 >> 10 = 0x43244
 588  *      0x10c91400 >> 10 = 0x43245
 589  *
 590  * Obviously, only those TRBs with DMA addresses that are within the segment
 591  * will make the radix tree return the stream ID for that ring.
 592  *
 593  * Caveats for the radix tree:
 594  *
 595  * The radix tree uses an unsigned long as a key pair.  On 32-bit systems, an
 596  * unsigned long will be 32-bits; on a 64-bit system an unsigned long will be
 597  * 64-bits.  Since we only request 32-bit DMA addresses, we can use that as the
 598  * key on 32-bit or 64-bit systems (it would also be fine if we asked for 64-bit
 599  * PCI DMA addresses on a 64-bit system).  There might be a problem on 32-bit
 600  * extended systems (where the DMA address can be bigger than 32-bits),
 601  * if we allow the PCI dma mask to be bigger than 32-bits.  So don't do that.
 602  */
 603 struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
 604                 unsigned int num_stream_ctxs,
 605                 unsigned int num_streams, gfp_t mem_flags)
 606 {
 607         struct xhci_stream_info *stream_info;
 608         u32 cur_stream;
 609         struct xhci_ring *cur_ring;
 610         unsigned long key;
 611         u64 addr;
 612         int ret;
 613
 614         xhci_dbg(xhci, "Allocating %u streams and %u "
 615                         "stream context array entries.\n",
 616                         num_streams, num_stream_ctxs);
 617         if (xhci->cmd_ring_reserved_trbs == MAX_RSVD_CMD_TRBS) {
 618                 xhci_dbg(xhci, "Command ring has no reserved TRBs available\n");
 619                 return NULL;
 620         }
 621         xhci->cmd_ring_reserved_trbs++;
 622
 623         stream_info = kzalloc(sizeof(struct xhci_stream_info), mem_flags);
 624         if (!stream_info)
 625                 goto cleanup_trbs;
 626
 627         stream_info->num_streams = num_streams;
 628         stream_info->num_stream_ctxs = num_stream_ctxs;
 629
 630         /* Initialize the array of virtual pointers to stream rings. */
 631         stream_info->stream_rings = kzalloc(
 632                         sizeof(struct xhci_ring *)*num_streams,
 633                         mem_flags);
 634         if (!stream_info->stream_rings)
 635                 goto cleanup_info;
 636
 637         /* Initialize the array of DMA addresses for stream rings for the HW. */
 638         stream_info->stream_ctx_array = xhci_alloc_stream_ctx(xhci,
 639                         num_stream_ctxs, &stream_info->ctx_array_dma,
 640                         mem_flags);
 641         if (!stream_info->stream_ctx_array)
 642                 goto cleanup_ctx;
 643         memset(stream_info->stream_ctx_array, 0,
 644                         sizeof(struct xhci_stream_ctx)*num_stream_ctxs);
 645
 646         /* Allocate everything needed to free the stream rings later */
 647         stream_info->free_streams_command =
 648                 xhci_alloc_command(xhci, true, true, mem_flags);
 649         if (!stream_info->free_streams_command)
 650                 goto cleanup_ctx;
 651
 652         INIT_RADIX_TREE(&stream_info->trb_address_map, GFP_ATOMIC);
 653
 654         /* Allocate rings for all the streams that the driver will use,
 655          * and add their segment DMA addresses to the radix tree.
 656          * Stream 0 is reserved.
 657          */
 658         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 659                 stream_info->stream_rings[cur_stream] =
 660                         xhci_ring_alloc(xhci, 2, 1, TYPE_STREAM, mem_flags);
 661                 cur_ring = stream_info->stream_rings[cur_stream];
 662                 if (!cur_ring)
 663                         goto cleanup_rings;
 664                 cur_ring->stream_id = cur_stream;
 665                 /* Set deq ptr, cycle bit, and stream context type */
 666                 addr = cur_ring->first_seg->dma |
 667                         SCT_FOR_CTX(SCT_PRI_TR) |
 668                         cur_ring->cycle_state;
 669                 stream_info->stream_ctx_array[cur_stream].stream_ring =
 670                         cpu_to_le64(addr);
 671                 xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
 672                                 cur_stream, (unsigned long long) addr);
 673
 674                 key = (unsigned long)
 675                         (cur_ring->first_seg->dma >> TRB_SEGMENT_SHIFT);
 676                 ret = radix_tree_insert(&stream_info->trb_address_map,
 677                                 key, cur_ring);
 678                 if (ret) {
 679                         xhci_ring_free(xhci, cur_ring);
 680                         stream_info->stream_rings[cur_stream] = NULL;
 681                         goto cleanup_rings;
 682                 }
 683         }
 684         /* Leave the other unused stream ring pointers in the stream context
 685          * array initialized to zero.  This will cause the xHC to give us an
 686          * error if the device asks for a stream ID we don't have setup (if it
 687          * was any other way, the host controller would assume the ring is
 688          * "empty" and wait forever for data to be queued to that stream ID).
 689          */
 690 #if XHCI_DEBUG
 691         /* Do a little test on the radix tree to make sure it returns the
 692          * correct values.
 693          */
 694         if (xhci_test_radix_tree(xhci, num_streams, stream_info))
 695                 goto cleanup_rings;
 696 #endif
 697
 698         return stream_info;
 699
 700 cleanup_rings:
 701         for (cur_stream = 1; cur_stream < num_streams; cur_stream++) {
 702                 cur_ring = stream_info->stream_rings[cur_stream];
 703                 if (cur_ring) {
 704                         addr = cur_ring->first_seg->dma;
 705                         radix_tree_delete(&stream_info->trb_address_map,
 706                                         addr >> TRB_SEGMENT_SHIFT);
 707                         xhci_ring_free(xhci, cur_ring);
 708                         stream_info->stream_rings[cur_stream] = NULL;
 709                 }
 710         }
 711         xhci_free_command(xhci, stream_info->free_streams_command);
 712 cleanup_ctx:
 713         kfree(stream_info->stream_rings);
 714 cleanup_info:
 715         kfree(stream_info);
 716 cleanup_trbs:
 717         xhci->cmd_ring_reserved_trbs--;
 718         return NULL;
 719 }
 720 /*
 721  * Sets the MaxPStreams field and the Linear Stream Array field.
 722  * Sets the dequeue pointer to the stream context array.
 723  */
 724 void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
 725                 struct xhci_ep_ctx *ep_ctx,
 726                 struct xhci_stream_info *stream_info)
 727 {
 728         u32 max_primary_streams;
 729         /* MaxPStreams is the number of stream context array entries, not the
 730          * number we're actually using.  Must be in 2^(MaxPstreams + 1) format.
 731          * fls(0) = 0, fls(0x1) = 1, fls(0x10) = 2, fls(0x100) = 3, etc.
 732          */
 733         max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
 734         xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
 735                         1 << (max_primary_streams + 1));
 736         ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
 737         ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
 738                                        | EP_HAS_LSA);
 739         ep_ctx->deq  = cpu_to_le64(stream_info->ctx_array_dma);
 740 }
 741
 742 /*
 743  * Sets the MaxPStreams field and the Linear Stream Array field to 0.
 744  * Reinstalls the "normal" endpoint ring (at its previous dequeue mark,
 745  * not at the beginning of the ring).
 746  */
 747 void xhci_setup_no_streams_ep_input_ctx(struct xhci_hcd *xhci,
 748                 struct xhci_ep_ctx *ep_ctx,
 749                 struct xhci_virt_ep *ep)
 750 {
 751         dma_addr_t addr;
 752         ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
 753         addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
 754         ep_ctx->deq  = cpu_to_le64(addr | ep->ring->cycle_state);
 755 }
 756
 757 /* Frees all stream contexts associated with the endpoint,
 758  *
 759  * Caller should fix the endpoint context streams fields.
 760  */
 761 void xhci_free_stream_info(struct xhci_hcd *xhci,
 762                 struct xhci_stream_info *stream_info)
 763 {
 764         int cur_stream;
 765         struct xhci_ring *cur_ring;
 766         dma_addr_t addr;
 767
 768         if (!stream_info)
 769                 return;
 770
 771         for (cur_stream = 1; cur_stream < stream_info->num_streams;
 772                         cur_stream++) {
 773                 cur_ring = stream_info->stream_rings[cur_stream];
 774                 if (cur_ring) {
 775                         addr = cur_ring->first_seg->dma;
 776                         radix_tree_delete(&stream_info->trb_address_map,
 777                                         addr >> TRB_SEGMENT_SHIFT);
 778                         xhci_ring_free(xhci, cur_ring);
 779                         stream_info->stream_rings[cur_stream] = NULL;
 780                 }
 781         }
 782         xhci_free_command(xhci, stream_info->free_streams_command);
 783         xhci->cmd_ring_reserved_trbs--;
 784         if (stream_info->stream_ctx_array)
 785                 xhci_free_stream_ctx(xhci,
 786                                 stream_info->num_stream_ctxs,
 787                                 stream_info->stream_ctx_array,
 788                                 stream_info->ctx_array_dma);
 789
 790         if (stream_info)
 791                 kfree(stream_info->stream_rings);
 792         kfree(stream_info);
 793 }
 794
 795
 796 /***************** Device context manipulation *************************/
 797
 798 static void xhci_init_endpoint_timer(struct xhci_hcd *xhci,
 799                 struct xhci_virt_ep *ep)
 800 {
 801         init_timer(&ep->stop_cmd_timer);
 802         ep->stop_cmd_timer.data = (unsigned long) ep;
 803         ep->stop_cmd_timer.function = xhci_stop_endpoint_command_watchdog;
 804         ep->xhci = xhci;
 805 }
 806
 807 static void xhci_free_tt_info(struct xhci_hcd *xhci,
 808                 struct xhci_virt_device *virt_dev,
 809                 int slot_id)
 810 {
 811         struct list_head *tt_list_head;
 812         struct xhci_tt_bw_info *tt_info, *next;
 813         bool slot_found = false;
 814
 815         /* If the device never made it past the Set Address stage,
 816          * it may not have the real_port set correctly.
 817          */
 818         if (virt_dev->real_port == 0 ||
 819                         virt_dev->real_port > HCS_MAX_PORTS(xhci->hcs_params1)) {
 820                 xhci_dbg(xhci, "Bad real port.\n");
 821                 return;
 822         }
 823
 824         tt_list_head = &(xhci->rh_bw[virt_dev->real_port - 1].tts);
 825         list_for_each_entry_safe(tt_info, next, tt_list_head, tt_list) {
 826                 /* Multi-TT hubs will have more than one entry */
 827                 if (tt_info->slot_id == slot_id) {
 828                         slot_found = true;
 829                         list_del(&tt_info->tt_list);
 830                         kfree(tt_info);
 831                 } else if (slot_found) {
 832                         break;
 833                 }
 834         }
 835 }
 836
 837 int xhci_alloc_tt_info(struct xhci_hcd *xhci,
 838                 struct xhci_virt_device *virt_dev,
 839                 struct usb_device *hdev,
 840                 struct usb_tt *tt, gfp_t mem_flags)
 841 {
 842         struct xhci_tt_bw_info          *tt_info;
 843         unsigned int                    num_ports;
 844         int                             i, j;
 845
 846         if (!tt->multi)
 847                 num_ports = 1;
 848         else
 849                 num_ports = hdev->maxchild;
 850
 851         for (i = 0; i < num_ports; i++, tt_info++) {
 852                 struct xhci_interval_bw_table *bw_table;
 853
 854                 tt_info = kzalloc(sizeof(*tt_info), mem_flags);
 855                 if (!tt_info)
 856                         goto free_tts;
 857                 INIT_LIST_HEAD(&tt_info->tt_list);
 858                 list_add(&tt_info->tt_list,
 859                                 &xhci->rh_bw[virt_dev->real_port - 1].tts);
 860                 tt_info->slot_id = virt_dev->udev->slot_id;
 861                 if (tt->multi)
 862                         tt_info->ttport = i+1;
 863                 bw_table = &tt_info->bw_table;
 864                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
 865                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
 866         }
 867         return 0;
 868
 869 free_tts:
 870         xhci_free_tt_info(xhci, virt_dev, virt_dev->udev->slot_id);
 871         return -ENOMEM;
 872 }
 873
 874
 875 /* All the xhci_tds in the ring's TD list should be freed at this point.
 876  * Should be called with xhci->lock held if there is any chance the TT lists
 877  * will be manipulated by the configure endpoint, allocate device, or update
 878  * hub functions while this function is removing the TT entries from the list.
 879  */
 880 void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id)
 881 {
 882         struct xhci_virt_device *dev;
 883         int i;
 884         int old_active_eps = 0;
 885
 886         /* Slot ID 0 is reserved */
 887         if (slot_id == 0 || !xhci->devs[slot_id])
 888                 return;
 889
 890         dev = xhci->devs[slot_id];
 891         xhci->dcbaa->dev_context_ptrs[slot_id] = 0;
 892         if (!dev)
 893                 return;
 894
 895         if (dev->tt_info)
 896                 old_active_eps = dev->tt_info->active_eps;
 897
 898         for (i = 0; i < 31; ++i) {
 899                 if (dev->eps[i].ring)
 900                         xhci_ring_free(xhci, dev->eps[i].ring);
 901                 if (dev->eps[i].stream_info)
 902                         xhci_free_stream_info(xhci,
 903                                         dev->eps[i].stream_info);
 904                 /* Endpoints on the TT/root port lists should have been removed
 905                  * when usb_disable_device() was called for the device.
 906                  * We can't drop them anyway, because the udev might have gone
 907                  * away by this point, and we can't tell what speed it was.
 908                  */
 909                 if (!list_empty(&dev->eps[i].bw_endpoint_list))
 910                         xhci_warn(xhci, "Slot %u endpoint %u "
 911                                         "not removed from BW list!\n",
 912                                         slot_id, i);
 913         }
 914         /* If this is a hub, free the TT(s) from the TT list */
 915         xhci_free_tt_info(xhci, dev, slot_id);
 916         /* If necessary, update the number of active TTs on this root port */
 917         xhci_update_tt_active_eps(xhci, dev, old_active_eps);
 918
 919         if (dev->ring_cache) {
 920                 for (i = 0; i < dev->num_rings_cached; i++)
 921                         xhci_ring_free(xhci, dev->ring_cache[i]);
 922                 kfree(dev->ring_cache);
 923         }
 924
 925         if (dev->in_ctx)
 926                 xhci_free_container_ctx(xhci, dev->in_ctx);
 927         if (dev->out_ctx)
 928                 xhci_free_container_ctx(xhci, dev->out_ctx);
 929
 930         kfree(xhci->devs[slot_id]);
 931         xhci->devs[slot_id] = NULL;
 932 }
 933
 934 int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id,
 935                 struct usb_device *udev, gfp_t flags)
 936 {
 937         struct xhci_virt_device *dev;
 938         int i;
 939
 940         /* Slot ID 0 is reserved */
 941         if (slot_id == 0 || xhci->devs[slot_id]) {
 942                 xhci_warn(xhci, "Bad Slot ID %d\n", slot_id);
 943                 return 0;
 944         }
 945
 946         xhci->devs[slot_id] = kzalloc(sizeof(*xhci->devs[slot_id]), flags);
 947         if (!xhci->devs[slot_id])
 948                 return 0;
 949         dev = xhci->devs[slot_id];
 950
 951         /* Allocate the (output) device context that will be used in the HC. */
 952         dev->out_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_DEVICE, flags);
 953         if (!dev->out_ctx)
 954                 goto fail;
 955
 956         xhci_dbg(xhci, "Slot %d output ctx = 0x%llx (dma)\n", slot_id,
 957                         (unsigned long long)dev->out_ctx->dma);
 958
 959         /* Allocate the (input) device context for address device command */
 960         dev->in_ctx = xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT, flags);
 961         if (!dev->in_ctx)
 962                 goto fail;
 963
 964         xhci_dbg(xhci, "Slot %d input ctx = 0x%llx (dma)\n", slot_id,
 965                         (unsigned long long)dev->in_ctx->dma);
 966
 967         /* Initialize the cancellation list and watchdog timers for each ep */
 968         for (i = 0; i < 31; i++) {
 969                 xhci_init_endpoint_timer(xhci, &dev->eps[i]);
 970                 INIT_LIST_HEAD(&dev->eps[i].cancelled_td_list);
 971                 INIT_LIST_HEAD(&dev->eps[i].bw_endpoint_list);
 972         }
 973
 974         /* Allocate endpoint 0 ring */
 975         dev->eps[0].ring = xhci_ring_alloc(xhci, 2, 1, TYPE_CTRL, flags);
 976         if (!dev->eps[0].ring)
 977                 goto fail;
 978
 979         /* Allocate pointers to the ring cache */
 980         dev->ring_cache = kzalloc(
 981                         sizeof(struct xhci_ring *)*XHCI_MAX_RINGS_CACHED,
 982                         flags);
 983         if (!dev->ring_cache)
 984                 goto fail;
 985         dev->num_rings_cached = 0;
 986
 987         init_completion(&dev->cmd_completion);
 988         INIT_LIST_HEAD(&dev->cmd_list);
 989         dev->udev = udev;
 990
 991         /* Point to output device context in dcbaa. */
 992         xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
 993         xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
 994                  slot_id,
 995                  &xhci->dcbaa->dev_context_ptrs[slot_id],
 996                  le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
 997
 998         return 1;
 999 fail:
1000         xhci_free_virt_device(xhci, slot_id);
1001         return 0;
1002 }
1003
1004 void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
1005                 struct usb_device *udev)
1006 {
1007         struct xhci_virt_device *virt_dev;
1008         struct xhci_ep_ctx      *ep0_ctx;
1009         struct xhci_ring        *ep_ring;
1010
1011         virt_dev = xhci->devs[udev->slot_id];
1012         ep0_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, 0);
1013         ep_ring = virt_dev->eps[0].ring;
1014         /*
1015          * FIXME we don't keep track of the dequeue pointer very well after a
1016          * Set TR dequeue pointer, so we're setting the dequeue pointer of the
1017          * host to our enqueue pointer.  This should only be called after a
1018          * configured device has reset, so all control transfers should have
1019          * been completed or cancelled before the reset.
1020          */
1021         ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
1022                                                         ep_ring->enqueue)
1023                                    | ep_ring->cycle_state);
1024 }
1025
1026 /*
1027  * The xHCI roothub may have ports of differing speeds in any order in the port
1028  * status registers.  xhci->port_array provides an array of the port speed for
1029  * each offset into the port status registers.
1030  *
1031  * The xHCI hardware wants to know the roothub port number that the USB device
1032  * is attached to (or the roothub port its ancestor hub is attached to).  All we
1033  * know is the index of that port under either the USB 2.0 or the USB 3.0
1034  * roothub, but that doesn't give us the real index into the HW port status
1035  * registers. Call xhci_find_raw_port_number() to get real index.
1036  */
1037 static u32 xhci_find_real_port_number(struct xhci_hcd *xhci,
1038                 struct usb_device *udev)
1039 {
1040         struct usb_device *top_dev;
1041         struct usb_hcd *hcd;
1042
1043         if (udev->speed == USB_SPEED_SUPER)
1044                 hcd = xhci->shared_hcd;
1045         else
1046                 hcd = xhci->main_hcd;
1047
1048         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1049                         top_dev = top_dev->parent)
1050                 /* Found device below root hub */;
1051
1052         return  xhci_find_raw_port_number(hcd, top_dev->portnum);
1053 }
1054
1055 /* Setup an xHCI virtual device for a Set Address command */
1056 int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev)
1057 {
1058         struct xhci_virt_device *dev;
1059         struct xhci_ep_ctx      *ep0_ctx;
1060         struct xhci_slot_ctx    *slot_ctx;
1061         u32                     port_num;
1062         u32                     max_packets;
1063         struct usb_device *top_dev;
1064
1065         dev = xhci->devs[udev->slot_id];
1066         /* Slot ID 0 is reserved */
1067         if (udev->slot_id == 0 || !dev) {
1068                 xhci_warn(xhci, "Slot ID %d is not assigned to this device\n",
1069                                 udev->slot_id);
1070                 return -EINVAL;
1071         }
1072         ep0_ctx = xhci_get_ep_ctx(xhci, dev->in_ctx, 0);
1073         slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
1074
1075         /* 3) Only the control endpoint is valid - one endpoint context */
1076         slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | udev->route);
1077         switch (udev->speed) {
1078         case USB_SPEED_SUPER:
1079                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
1080                 max_packets = MAX_PACKET(512);
1081                 break;
1082         case USB_SPEED_HIGH:
1083                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
1084                 max_packets = MAX_PACKET(64);
1085                 break;
1086         /* USB core guesses at a 64-byte max packet first for FS devices */
1087         case USB_SPEED_FULL:
1088                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
1089                 max_packets = MAX_PACKET(64);
1090                 break;
1091         case USB_SPEED_LOW:
1092                 slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
1093                 max_packets = MAX_PACKET(8);
1094                 break;
1095         case USB_SPEED_WIRELESS:
1096                 xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
1097                 return -EINVAL;
1098                 break;
1099         default:
1100                 /* Speed was set earlier, this shouldn't happen. */
1101                 return -EINVAL;
1102         }
1103         /* Find the root hub port this device is under */
1104         port_num = xhci_find_real_port_number(xhci, udev);
1105         if (!port_num)
1106                 return -EINVAL;
1107         slot_ctx->dev_info2 |= cpu_to_le32(ROOT_HUB_PORT(port_num));
1108         /* Set the port number in the virtual_device to the faked port number */
1109         for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
1110                         top_dev = top_dev->parent)
1111                 /* Found device below root hub */;
1112         dev->fake_port = top_dev->portnum;
1113         dev->real_port = port_num;
1114         xhci_dbg(xhci, "Set root hub portnum to %d\n", port_num);
1115         xhci_dbg(xhci, "Set fake root hub portnum to %d\n", dev->fake_port);
1116
1117         /* Find the right bandwidth table that this device will be a part of.
1118          * If this is a full speed device attached directly to a root port (or a
1119          * decendent of one), it counts as a primary bandwidth domain, not a
1120          * secondary bandwidth domain under a TT.  An xhci_tt_info structure
1121          * will never be created for the HS root hub.
1122          */
1123         if (!udev->tt || !udev->tt->hub->parent) {
1124                 dev->bw_table = &xhci->rh_bw[port_num - 1].bw_table;
1125         } else {
1126                 struct xhci_root_port_bw_info *rh_bw;
1127                 struct xhci_tt_bw_info *tt_bw;
1128
1129                 rh_bw = &xhci->rh_bw[port_num - 1];
1130                 /* Find the right TT. */
1131                 list_for_each_entry(tt_bw, &rh_bw->tts, tt_list) {
1132                         if (tt_bw->slot_id != udev->tt->hub->slot_id)
1133                                 continue;
1134
1135                         if (!dev->udev->tt->multi ||
1136                                         (udev->tt->multi &&
1137                                          tt_bw->ttport == dev->udev->ttport)) {
1138                                 dev->bw_table = &tt_bw->bw_table;
1139                                 dev->tt_info = tt_bw;
1140                                 break;
1141                         }
1142                 }
1143                 if (!dev->tt_info)
1144                         xhci_warn(xhci, "WARN: Didn't find a matching TT\n");
1145         }
1146
1147         /* Is this a LS/FS device under an external HS hub? */
1148         if (udev->tt && udev->tt->hub->parent) {
1149                 slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
1150                                                 (udev->ttport << 8));
1151                 if (udev->tt->multi)
1152                         slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
1153         }
1154         xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
1155         xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
1156
1157         /* Step 4 - ring already allocated */
1158         /* Step 5 */
1159         ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
1160
1161         /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
1162         ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3) |
1163                                          max_packets);
1164
1165         ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
1166                                    dev->eps[0].ring->cycle_state);
1167
1168         /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
1169
1170         return 0;
1171 }
1172
1173 /*
1174  * Convert interval expressed as 2^(bInterval - 1) == interval into
1175  * straight exponent value 2^n == interval.
1176  *
1177  */
1178 static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
1179                 struct usb_host_endpoint *ep)
1180 {
1181         unsigned int interval;
1182
1183         interval = clamp_val(ep->desc.bInterval, 1, 16) - 1;
1184         if (interval != ep->desc.bInterval - 1)
1185                 dev_warn(&udev->dev,
1186                          "ep %#x - rounding interval to %d %sframes\n",
1187                          ep->desc.bEndpointAddress,
1188                          1 << interval,
1189                          udev->speed == USB_SPEED_FULL ? "" : "micro");
1190
1191         if (udev->speed == USB_SPEED_FULL) {
1192                 /*
1193                  * Full speed isoc endpoints specify interval in frames,
1194                  * not microframes. We are using microframes everywhere,
1195                  * so adjust accordingly.
1196                  */
1197                 interval += 3;  /* 1 frame = 2^3 uframes */
1198         }
1199
1200         return interval;
1201 }
1202
1203 /*
1204  * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
1205  * microframes, rounded down to nearest power of 2.
1206  */
1207 static unsigned int xhci_microframes_to_exponent(struct usb_device *udev,
1208                 struct usb_host_endpoint *ep, unsigned int desc_interval,
1209                 unsigned int min_exponent, unsigned int max_exponent)
1210 {
1211         unsigned int interval;
1212
1213         interval = fls(desc_interval) - 1;
1214         interval = clamp_val(interval, min_exponent, max_exponent);
1215         if ((1 << interval) != desc_interval)
1216                 dev_warn(&udev->dev,
1217                          "ep %#x - rounding interval to %d microframes, ep desc says %d microframes\n",
1218                          ep->desc.bEndpointAddress,
1219                          1 << interval,
1220                          desc_interval);
1221
1222         return interval;
1223 }
1224
1225 static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
1226                 struct usb_host_endpoint *ep)
1227 {
1228         if (ep->desc.bInterval == 0)
1229                 return 0;
1230         return xhci_microframes_to_exponent(udev, ep,
1231                         ep->desc.bInterval, 0, 15);
1232 }
1233
1234
1235 static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
1236                 struct usb_host_endpoint *ep)
1237 {
1238         return xhci_microframes_to_exponent(udev, ep,
1239                         ep->desc.bInterval * 8, 3, 10);
1240 }
1241
1242 /* Return the polling or NAK interval.
1243  *
1244  * The polling interval is expressed in "microframes".  If xHCI's Interval field
1245  * is set to N, it will service the endpoint every 2^(Interval)*125us.
1246  *
1247  * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
1248  * is set to 0.
1249  */
1250 static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
1251                 struct usb_host_endpoint *ep)
1252 {
1253         unsigned int interval = 0;
1254
1255         switch (udev->speed) {
1256         case USB_SPEED_HIGH:
1257                 /* Max NAK rate */
1258                 if (usb_endpoint_xfer_control(&ep->desc) ||
1259                     usb_endpoint_xfer_bulk(&ep->desc)) {
1260                         interval = xhci_parse_microframe_interval(udev, ep);
1261                         break;
1262                 }
1263                 /* Fall through - SS and HS isoc/int have same decoding */
1264
1265         case USB_SPEED_SUPER:
1266                 if (usb_endpoint_xfer_int(&ep->desc) ||
1267                     usb_endpoint_xfer_isoc(&ep->desc)) {
1268                         interval = xhci_parse_exponent_interval(udev, ep);
1269                 }
1270                 break;
1271
1272         case USB_SPEED_FULL:
1273                 if (usb_endpoint_xfer_isoc(&ep->desc)) {
1274                         interval = xhci_parse_exponent_interval(udev, ep);
1275                         break;
1276                 }
1277                 /*
1278                  * Fall through for interrupt endpoint interval decoding
1279                  * since it uses the same rules as low speed interrupt
1280                  * endpoints.
1281                  */
1282
1283         case USB_SPEED_LOW:
1284                 if (usb_endpoint_xfer_int(&ep->desc) ||
1285                     usb_endpoint_xfer_isoc(&ep->desc)) {
1286
1287                         interval = xhci_parse_frame_interval(udev, ep);
1288                 }
1289                 break;
1290
1291         default:
1292                 BUG();
1293         }
1294         return EP_INTERVAL(interval);
1295 }
1296
1297 /* The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
1298  * High speed endpoint descriptors can define "the number of additional
1299  * transaction opportunities per microframe", but that goes in the Max Burst
1300  * endpoint context field.
1301  */
1302 static u32 xhci_get_endpoint_mult(struct usb_device *udev,
1303                 struct usb_host_endpoint *ep)
1304 {
1305         if (udev->speed != USB_SPEED_SUPER ||
1306                         !usb_endpoint_xfer_isoc(&ep->desc))
1307                 return 0;
1308         return ep->ss_ep_comp.bmAttributes;
1309 }
1310
1311 static u32 xhci_get_endpoint_type(struct usb_device *udev,
1312                 struct usb_host_endpoint *ep)
1313 {
1314         int in;
1315         u32 type;
1316
1317         in = usb_endpoint_dir_in(&ep->desc);
1318         if (usb_endpoint_xfer_control(&ep->desc)) {
1319                 type = EP_TYPE(CTRL_EP);
1320         } else if (usb_endpoint_xfer_bulk(&ep->desc)) {
1321                 if (in)
1322                         type = EP_TYPE(BULK_IN_EP);
1323                 else
1324                         type = EP_TYPE(BULK_OUT_EP);
1325         } else if (usb_endpoint_xfer_isoc(&ep->desc)) {
1326                 if (in)
1327                         type = EP_TYPE(ISOC_IN_EP);
1328                 else
1329                         type = EP_TYPE(ISOC_OUT_EP);
1330         } else if (usb_endpoint_xfer_int(&ep->desc)) {
1331                 if (in)
1332                         type = EP_TYPE(INT_IN_EP);
1333                 else
1334                         type = EP_TYPE(INT_OUT_EP);
1335         } else {
1336                 type = 0;
1337         }
1338         return type;
1339 }
1340
1341 /* Return the maximum endpoint service interval time (ESIT) payload.
1342  * Basically, this is the maxpacket size, multiplied by the burst size
1343  * and mult size.
1344  */
1345 static u32 xhci_get_max_esit_payload(struct xhci_hcd *xhci,
1346                 struct usb_device *udev,
1347                 struct usb_host_endpoint *ep)
1348 {
1349         int max_burst;
1350         int max_packet;
1351
1352         /* Only applies for interrupt or isochronous endpoints */
1353         if (usb_endpoint_xfer_control(&ep->desc) ||
1354                         usb_endpoint_xfer_bulk(&ep->desc))
1355                 return 0;
1356
1357         if (udev->speed == USB_SPEED_SUPER)
1358                 return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
1359
1360         max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1361         max_burst = (usb_endpoint_maxp(&ep->desc) & 0x1800) >> 11;
1362         /* A 0 in max burst means 1 transfer per ESIT */
1363         return max_packet * (max_burst + 1);
1364 }
1365
1366 /* Set up an endpoint with one ring segment.  Do not allocate stream rings.
1367  * Drivers will have to call usb_alloc_streams() to do that.
1368  */
1369 int xhci_endpoint_init(struct xhci_hcd *xhci,
1370                 struct xhci_virt_device *virt_dev,
1371                 struct usb_device *udev,
1372                 struct usb_host_endpoint *ep,
1373                 gfp_t mem_flags)
1374 {
1375         unsigned int ep_index;
1376         struct xhci_ep_ctx *ep_ctx;
1377         struct xhci_ring *ep_ring;
1378         unsigned int max_packet;
1379         unsigned int max_burst;
1380         enum xhci_ring_type type;
1381         u32 max_esit_payload;
1382         u32 endpoint_type;
1383
1384         ep_index = xhci_get_endpoint_index(&ep->desc);
1385         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1386
1387         endpoint_type = xhci_get_endpoint_type(udev, ep);
1388         if (!endpoint_type)
1389                 return -EINVAL;
1390         ep_ctx->ep_info2 = cpu_to_le32(endpoint_type);
1391
1392         type = usb_endpoint_type(&ep->desc);
1393         /* Set up the endpoint ring */
1394         virt_dev->eps[ep_index].new_ring =
1395                 xhci_ring_alloc(xhci, 2, 1, type, mem_flags);
1396         if (!virt_dev->eps[ep_index].new_ring) {
1397                 /* Attempt to use the ring cache */
1398                 if (virt_dev->num_rings_cached == 0)
1399                         return -ENOMEM;
1400                 virt_dev->eps[ep_index].new_ring =
1401                         virt_dev->ring_cache[virt_dev->num_rings_cached];
1402                 virt_dev->ring_cache[virt_dev->num_rings_cached] = NULL;
1403                 virt_dev->num_rings_cached--;
1404                 xhci_reinit_cached_ring(xhci, virt_dev->eps[ep_index].new_ring,
1405                                         1, type);
1406         }
1407         virt_dev->eps[ep_index].skip = false;
1408         ep_ring = virt_dev->eps[ep_index].new_ring;
1409         ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
1410
1411         ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
1412                                       | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
1413
1414         /* FIXME dig Mult and streams info out of ep companion desc */
1415
1416         /* Allow 3 retries for everything but isoc;
1417          * CErr shall be set to 0 for Isoch endpoints.
1418          */
1419         if (!usb_endpoint_xfer_isoc(&ep->desc))
1420                 ep_ctx->ep_info2 |= cpu_to_le32(ERROR_COUNT(3));
1421         else
1422                 ep_ctx->ep_info2 |= cpu_to_le32(ERROR_COUNT(0));
1423
1424         /* Set the max packet size and max burst */
1425         max_packet = GET_MAX_PACKET(usb_endpoint_maxp(&ep->desc));
1426         max_burst = 0;
1427         switch (udev->speed) {
1428         case USB_SPEED_SUPER:
1429                 /* dig out max burst from ep companion desc */
1430                 max_burst = ep->ss_ep_comp.bMaxBurst;
1431                 break;
1432         case USB_SPEED_HIGH:
1433                 /* Some devices get this wrong */
1434                 if (usb_endpoint_xfer_bulk(&ep->desc))
1435                         max_packet = 512;
1436                 /* bits 11:12 specify the number of additional transaction
1437                  * opportunities per microframe (USB 2.0, section 9.6.6)
1438                  */
1439                 if (usb_endpoint_xfer_isoc(&ep->desc) ||
1440                                 usb_endpoint_xfer_int(&ep->desc)) {
1441                         max_burst = (usb_endpoint_maxp(&ep->desc)
1442                                      & 0x1800) >> 11;
1443                 }
1444                 break;
1445         case USB_SPEED_FULL:
1446         case USB_SPEED_LOW:
1447                 break;
1448         default:
1449                 BUG();
1450         }
1451         ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet) |
1452                         MAX_BURST(max_burst));
1453         max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
1454         ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
1455
1456         /*
1457          * XXX no idea how to calculate the average TRB buffer length for bulk
1458          * endpoints, as the driver gives us no clue how big each scatter gather
1459          * list entry (or buffer) is going to be.
1460          *
1461          * For isochronous and interrupt endpoints, we set it to the max
1462          * available, until we have new API in the USB core to allow drivers to
1463          * declare how much bandwidth they actually need.
1464          *
1465          * Normally, it would be calculated by taking the total of the buffer
1466          * lengths in the TD and then dividing by the number of TRBs in a TD,
1467          * including link TRBs, No-op TRBs, and Event data TRBs.  Since we don't
1468          * use Event Data TRBs, and we don't chain in a link TRB on short
1469          * transfers, we're basically dividing by 1.
1470          *
1471          * xHCI 1.0 specification indicates that the Average TRB Length should
1472          * be set to 8 for control endpoints.
1473          */
1474         if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
1475                 ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
1476         else
1477                 ep_ctx->tx_info |=
1478                          cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
1479
1480         /* FIXME Debug endpoint context */
1481         return 0;
1482 }
1483
1484 void xhci_endpoint_zero(struct xhci_hcd *xhci,
1485                 struct xhci_virt_device *virt_dev,
1486                 struct usb_host_endpoint *ep)
1487 {
1488         unsigned int ep_index;
1489         struct xhci_ep_ctx *ep_ctx;
1490
1491         ep_index = xhci_get_endpoint_index(&ep->desc);
1492         ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
1493
1494         ep_ctx->ep_info = 0;
1495         ep_ctx->ep_info2 = 0;
1496         ep_ctx->deq = 0;
1497         ep_ctx->tx_info = 0;
1498         /* Don't free the endpoint ring until the set interface or configuration
1499          * request succeeds.
1500          */
1501 }
1502
1503 void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info)
1504 {
1505         bw_info->ep_interval = 0;
1506         bw_info->mult = 0;
1507         bw_info->num_packets = 0;
1508         bw_info->max_packet_size = 0;
1509         bw_info->type = 0;
1510         bw_info->max_esit_payload = 0;
1511 }
1512
1513 void xhci_update_bw_info(struct xhci_hcd *xhci,
1514                 struct xhci_container_ctx *in_ctx,
1515                 struct xhci_input_control_ctx *ctrl_ctx,
1516                 struct xhci_virt_device *virt_dev)
1517 {
1518         struct xhci_bw_info *bw_info;
1519         struct xhci_ep_ctx *ep_ctx;
1520         unsigned int ep_type;
1521         int i;
1522
1523         for (i = 1; i < 31; ++i) {
1524                 bw_info = &virt_dev->eps[i].bw_info;
1525
1526                 /* We can't tell what endpoint type is being dropped, but
1527                  * unconditionally clearing the bandwidth info for non-periodic
1528                  * endpoints should be harmless because the info will never be
1529                  * set in the first place.
1530                  */
1531                 if (!EP_IS_ADDED(ctrl_ctx, i) && EP_IS_DROPPED(ctrl_ctx, i)) {
1532                         /* Dropped endpoint */
1533                         xhci_clear_endpoint_bw_info(bw_info);
1534                         continue;
1535                 }
1536
1537                 if (EP_IS_ADDED(ctrl_ctx, i)) {
1538                         ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, i);
1539                         ep_type = CTX_TO_EP_TYPE(le32_to_cpu(ep_ctx->ep_info2));
1540
1541                         /* Ignore non-periodic endpoints */
1542                         if (ep_type != ISOC_OUT_EP && ep_type != INT_OUT_EP &&
1543                                         ep_type != ISOC_IN_EP &&
1544                                         ep_type != INT_IN_EP)
1545                                 continue;
1546
1547                         /* Added or changed endpoint */
1548                         bw_info->ep_interval = CTX_TO_EP_INTERVAL(
1549                                         le32_to_cpu(ep_ctx->ep_info));
1550                         /* Number of packets and mult are zero-based in the
1551                          * input context, but we want one-based for the
1552                          * interval table.
1553                          */
1554                         bw_info->mult = CTX_TO_EP_MULT(
1555                                         le32_to_cpu(ep_ctx->ep_info)) + 1;
1556                         bw_info->num_packets = CTX_TO_MAX_BURST(
1557                                         le32_to_cpu(ep_ctx->ep_info2)) + 1;
1558                         bw_info->max_packet_size = MAX_PACKET_DECODED(
1559                                         le32_to_cpu(ep_ctx->ep_info2));
1560                         bw_info->type = ep_type;
1561                         bw_info->max_esit_payload = CTX_TO_MAX_ESIT_PAYLOAD(
1562                                         le32_to_cpu(ep_ctx->tx_info));
1563                 }
1564         }
1565 }
1566
1567 /* Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
1568  * Useful when you want to change one particular aspect of the endpoint and then
1569  * issue a configure endpoint command.
1570  */
1571 void xhci_endpoint_copy(struct xhci_hcd *xhci,
1572                 struct xhci_container_ctx *in_ctx,
1573                 struct xhci_container_ctx *out_ctx,
1574                 unsigned int ep_index)
1575 {
1576         struct xhci_ep_ctx *out_ep_ctx;
1577         struct xhci_ep_ctx *in_ep_ctx;
1578
1579         out_ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
1580         in_ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
1581
1582         in_ep_ctx->ep_info = out_ep_ctx->ep_info;
1583         in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
1584         in_ep_ctx->deq = out_ep_ctx->deq;
1585         in_ep_ctx->tx_info = out_ep_ctx->tx_info;
1586 }
1587
1588 /* Copy output xhci_slot_ctx to the input xhci_slot_ctx.
1589  * Useful when you want to change one particular aspect of the endpoint and then
1590  * issue a configure endpoint command.  Only the context entries field matters,
1591  * but we'll copy the whole thing anyway.
1592  */
1593 void xhci_slot_copy(struct xhci_hcd *xhci,
1594                 struct xhci_container_ctx *in_ctx,
1595                 struct xhci_container_ctx *out_ctx)
1596 {
1597         struct xhci_slot_ctx *in_slot_ctx;
1598         struct xhci_slot_ctx *out_slot_ctx;
1599
1600         in_slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
1601         out_slot_ctx = xhci_get_slot_ctx(xhci, out_ctx);
1602
1603         in_slot_ctx->dev_info = out_slot_ctx->dev_info;
1604         in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
1605         in_slot_ctx->tt_info = out_slot_ctx->tt_info;
1606         in_slot_ctx->dev_state = out_slot_ctx->dev_state;
1607 }
1608
1609 /* Set up the scratchpad buffer array and scratchpad buffers, if needed. */
1610 static int scratchpad_alloc(struct xhci_hcd *xhci, gfp_t flags)
1611 {
1612         int i;
1613         struct device *dev = xhci_to_hcd(xhci)->self.controller;
1614         int num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1615
1616         xhci_dbg(xhci, "Allocating %d scratchpad buffers\n", num_sp);
1617
1618         if (!num_sp)
1619                 return 0;
1620
1621         xhci->scratchpad = kzalloc(sizeof(*xhci->scratchpad), flags);
1622         if (!xhci->scratchpad)
1623                 goto fail_sp;
1624
1625         xhci->scratchpad->sp_array = dma_alloc_coherent(dev,
1626                                      num_sp * sizeof(u64),
1627                                      &xhci->scratchpad->sp_dma, flags);
1628         if (!xhci->scratchpad->sp_array)
1629                 goto fail_sp2;
1630
1631         xhci->scratchpad->sp_buffers = kzalloc(sizeof(void *) * num_sp, flags);
1632         if (!xhci->scratchpad->sp_buffers)
1633                 goto fail_sp3;
1634
1635         xhci->scratchpad->sp_dma_buffers =
1636                 kzalloc(sizeof(dma_addr_t) * num_sp, flags);
1637
1638         if (!xhci->scratchpad->sp_dma_buffers)
1639                 goto fail_sp4;
1640
1641         xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
1642         for (i = 0; i < num_sp; i++) {
1643                 dma_addr_t dma;
1644                 void *buf = dma_alloc_coherent(dev, xhci->page_size, &dma,
1645                                 flags);
1646                 if (!buf)
1647                         goto fail_sp5;
1648
1649                 xhci->scratchpad->sp_array[i] = dma;
1650                 xhci->scratchpad->sp_buffers[i] = buf;
1651                 xhci->scratchpad->sp_dma_buffers[i] = dma;
1652         }
1653
1654         return 0;
1655
1656  fail_sp5:
1657         for (i = i - 1; i >= 0; i--) {
1658                 dma_free_coherent(dev, xhci->page_size,
1659                                     xhci->scratchpad->sp_buffers[i],
1660                                     xhci->scratchpad->sp_dma_buffers[i]);
1661         }
1662         kfree(xhci->scratchpad->sp_dma_buffers);
1663
1664  fail_sp4:
1665         kfree(xhci->scratchpad->sp_buffers);
1666
1667  fail_sp3:
1668         dma_free_coherent(dev, num_sp * sizeof(u64),
1669                             xhci->scratchpad->sp_array,
1670                             xhci->scratchpad->sp_dma);
1671
1672  fail_sp2:
1673         kfree(xhci->scratchpad);
1674         xhci->scratchpad = NULL;
1675
1676  fail_sp:
1677         return -ENOMEM;
1678 }
1679
1680 static void scratchpad_free(struct xhci_hcd *xhci)
1681 {
1682         int num_sp;
1683         int i;
1684         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1685
1686         if (!xhci->scratchpad)
1687                 return;
1688
1689         num_sp = HCS_MAX_SCRATCHPAD(xhci->hcs_params2);
1690
1691         for (i = 0; i < num_sp; i++) {
1692                 dma_free_coherent(&pdev->dev, xhci->page_size,
1693                                     xhci->scratchpad->sp_buffers[i],
1694                                     xhci->scratchpad->sp_dma_buffers[i]);
1695         }
1696         kfree(xhci->scratchpad->sp_dma_buffers);
1697         kfree(xhci->scratchpad->sp_buffers);
1698         dma_free_coherent(&pdev->dev, num_sp * sizeof(u64),
1699                             xhci->scratchpad->sp_array,
1700                             xhci->scratchpad->sp_dma);
1701         kfree(xhci->scratchpad);
1702         xhci->scratchpad = NULL;
1703 }
1704
1705 struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
1706                 bool allocate_in_ctx, bool allocate_completion,
1707                 gfp_t mem_flags)
1708 {
1709         struct xhci_command *command;
1710
1711         command = kzalloc(sizeof(*command), mem_flags);
1712         if (!command)
1713                 return NULL;
1714
1715         if (allocate_in_ctx) {
1716                 command->in_ctx =
1717                         xhci_alloc_container_ctx(xhci, XHCI_CTX_TYPE_INPUT,
1718                                         mem_flags);
1719                 if (!command->in_ctx) {
1720                         kfree(command);
1721                         return NULL;
1722                 }
1723         }
1724
1725         if (allocate_completion) {
1726                 command->completion =
1727                         kzalloc(sizeof(struct completion), mem_flags);
1728                 if (!command->completion) {
1729                         xhci_free_container_ctx(xhci, command->in_ctx);
1730                         kfree(command);
1731                         return NULL;
1732                 }
1733                 init_completion(command->completion);
1734         }
1735
1736         command->status = 0;
1737         INIT_LIST_HEAD(&command->cmd_list);
1738         return command;
1739 }
1740
1741 void xhci_urb_free_priv(struct xhci_hcd *xhci, struct urb_priv *urb_priv)
1742 {
1743         if (urb_priv) {
1744                 kfree(urb_priv->td[0]);
1745                 kfree(urb_priv);
1746         }
1747 }
1748
1749 void xhci_free_command(struct xhci_hcd *xhci,
1750                 struct xhci_command *command)
1751 {
1752         xhci_free_container_ctx(xhci,
1753                         command->in_ctx);
1754         kfree(command->completion);
1755         kfree(command);
1756 }
1757
1758 void xhci_mem_cleanup(struct xhci_hcd *xhci)
1759 {
1760         struct pci_dev  *pdev = to_pci_dev(xhci_to_hcd(xhci)->self.controller);
1761         struct dev_info *dev_info, *next;
1762         struct xhci_cd  *cur_cd, *next_cd;
1763         unsigned long   flags;
1764         int size;
1765         int i, j, num_ports;
1766
1767         /* Free the Event Ring Segment Table and the actual Event Ring */
1768         size = sizeof(struct xhci_erst_entry)*(xhci->erst.num_entries);
1769         if (xhci->erst.entries)
1770                 dma_free_coherent(&pdev->dev, size,
1771                                 xhci->erst.entries, xhci->erst.erst_dma_addr);
1772         xhci->erst.entries = NULL;
1773         xhci_dbg(xhci, "Freed ERST\n");
1774         if (xhci->event_ring)
1775                 xhci_ring_free(xhci, xhci->event_ring);
1776         xhci->event_ring = NULL;
1777         xhci_dbg(xhci, "Freed event ring\n");
1778
1779         if (xhci->lpm_command)
1780                 xhci_free_command(xhci, xhci->lpm_command);
1781         xhci->cmd_ring_reserved_trbs = 0;
1782         if (xhci->cmd_ring)
1783                 xhci_ring_free(xhci, xhci->cmd_ring);
1784         xhci->cmd_ring = NULL;
1785         xhci_dbg(xhci, "Freed command ring\n");
1786         list_for_each_entry_safe(cur_cd, next_cd,
1787                         &xhci->cancel_cmd_list, cancel_cmd_list) {
1788                 list_del(&cur_cd->cancel_cmd_list);
1789                 kfree(cur_cd);
1790         }
1791
1792         for (i = 1; i < MAX_HC_SLOTS; ++i)
1793                 xhci_free_virt_device(xhci, i);
1794
1795         if (xhci->segment_pool)
1796                 dma_pool_destroy(xhci->segment_pool);
1797         xhci->segment_pool = NULL;
1798         xhci_dbg(xhci, "Freed segment pool\n");
1799
1800         if (xhci->device_pool)
1801                 dma_pool_destroy(xhci->device_pool);
1802         xhci->device_pool = NULL;
1803         xhci_dbg(xhci, "Freed device context pool\n");
1804
1805         if (xhci->small_streams_pool)
1806                 dma_pool_destroy(xhci->small_streams_pool);
1807         xhci->small_streams_pool = NULL;
1808         xhci_dbg(xhci, "Freed small stream array pool\n");
1809
1810         if (xhci->medium_streams_pool)
1811                 dma_pool_destroy(xhci->medium_streams_pool);
1812         xhci->medium_streams_pool = NULL;
1813         xhci_dbg(xhci, "Freed medium stream array pool\n");
1814
1815         if (xhci->dcbaa)
1816                 dma_free_coherent(&pdev->dev, sizeof(*xhci->dcbaa),
1817                                 xhci->dcbaa, xhci->dcbaa->dma);
1818         xhci->dcbaa = NULL;
1819
1820         scratchpad_free(xhci);
1821
1822         spin_lock_irqsave(&xhci->lock, flags);
1823         list_for_each_entry_safe(dev_info, next, &xhci->lpm_failed_devs, list) {
1824                 list_del(&dev_info->list);
1825                 kfree(dev_info);
1826         }
1827         spin_unlock_irqrestore(&xhci->lock, flags);
1828
1829         if (!xhci->rh_bw)
1830                 goto no_bw;
1831
1832         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1833         for (i = 0; i < num_ports; i++) {
1834                 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
1835                 for (j = 0; j < XHCI_MAX_INTERVAL; j++) {
1836                         struct list_head *ep = &bwt->interval_bw[j].endpoints;
1837                         while (!list_empty(ep))
1838                                 list_del_init(ep->next);
1839                 }
1840         }
1841
1842         for (i = 0; i < num_ports; i++) {
1843                 struct xhci_tt_bw_info *tt, *n;
1844                 list_for_each_entry_safe(tt, n, &xhci->rh_bw[i].tts, tt_list) {
1845                         list_del(&tt->tt_list);
1846                         kfree(tt);
1847                 }
1848         }
1849
1850 no_bw:
1851         xhci->num_usb2_ports = 0;
1852         xhci->num_usb3_ports = 0;
1853         xhci->num_active_eps = 0;
1854         kfree(xhci->usb2_ports);
1855         kfree(xhci->usb3_ports);
1856         kfree(xhci->port_array);
1857         kfree(xhci->rh_bw);
1858         kfree(xhci->ext_caps);
1859
1860         xhci->page_size = 0;
1861         xhci->page_shift = 0;
1862         xhci->bus_state[0].bus_suspended = 0;
1863         xhci->bus_state[1].bus_suspended = 0;
1864 }
1865
1866 static int xhci_test_trb_in_td(struct xhci_hcd *xhci,
1867                 struct xhci_segment *input_seg,
1868                 union xhci_trb *start_trb,
1869                 union xhci_trb *end_trb,
1870                 dma_addr_t input_dma,
1871                 struct xhci_segment *result_seg,
1872                 char *test_name, int test_number)
1873 {
1874         unsigned long long start_dma;
1875         unsigned long long end_dma;
1876         struct xhci_segment *seg;
1877
1878         start_dma = xhci_trb_virt_to_dma(input_seg, start_trb);
1879         end_dma = xhci_trb_virt_to_dma(input_seg, end_trb);
1880
1881         seg = trb_in_td(input_seg, start_trb, end_trb, input_dma);
1882         if (seg != result_seg) {
1883                 xhci_warn(xhci, "WARN: %s TRB math test %d failed!\n",
1884                                 test_name, test_number);
1885                 xhci_warn(xhci, "Tested TRB math w/ seg %p and "
1886                                 "input DMA 0x%llx\n",
1887                                 input_seg,
1888                                 (unsigned long long) input_dma);
1889                 xhci_warn(xhci, "starting TRB %p (0x%llx DMA), "
1890                                 "ending TRB %p (0x%llx DMA)\n",
1891                                 start_trb, start_dma,
1892                                 end_trb, end_dma);
1893                 xhci_warn(xhci, "Expected seg %p, got seg %p\n",
1894                                 result_seg, seg);
1895                 return -1;
1896         }
1897         return 0;
1898 }
1899
1900 /* TRB math checks for xhci_trb_in_td(), using the command and event rings. */
1901 static int xhci_check_trb_in_td_math(struct xhci_hcd *xhci, gfp_t mem_flags)
1902 {
1903         struct {
1904                 dma_addr_t              input_dma;
1905                 struct xhci_segment     *result_seg;
1906         } simple_test_vector [] = {
1907                 /* A zeroed DMA field should fail */
1908                 { 0, NULL },
1909                 /* One TRB before the ring start should fail */
1910                 { xhci->event_ring->first_seg->dma - 16, NULL },
1911                 /* One byte before the ring start should fail */
1912                 { xhci->event_ring->first_seg->dma - 1, NULL },
1913                 /* Starting TRB should succeed */
1914                 { xhci->event_ring->first_seg->dma, xhci->event_ring->first_seg },
1915                 /* Ending TRB should succeed */
1916                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16,
1917                         xhci->event_ring->first_seg },
1918                 /* One byte after the ring end should fail */
1919                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 1)*16 + 1, NULL },
1920                 /* One TRB after the ring end should fail */
1921                 { xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT)*16, NULL },
1922                 /* An address of all ones should fail */
1923                 { (dma_addr_t) (~0), NULL },
1924         };
1925         struct {
1926                 struct xhci_segment     *input_seg;
1927                 union xhci_trb          *start_trb;
1928                 union xhci_trb          *end_trb;
1929                 dma_addr_t              input_dma;
1930                 struct xhci_segment     *result_seg;
1931         } complex_test_vector [] = {
1932                 /* Test feeding a valid DMA address from a different ring */
1933                 {       .input_seg = xhci->event_ring->first_seg,
1934                         .start_trb = xhci->event_ring->first_seg->trbs,
1935                         .end_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1936                         .input_dma = xhci->cmd_ring->first_seg->dma,
1937                         .result_seg = NULL,
1938                 },
1939                 /* Test feeding a valid end TRB from a different ring */
1940                 {       .input_seg = xhci->event_ring->first_seg,
1941                         .start_trb = xhci->event_ring->first_seg->trbs,
1942                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1943                         .input_dma = xhci->cmd_ring->first_seg->dma,
1944                         .result_seg = NULL,
1945                 },
1946                 /* Test feeding a valid start and end TRB from a different ring */
1947                 {       .input_seg = xhci->event_ring->first_seg,
1948                         .start_trb = xhci->cmd_ring->first_seg->trbs,
1949                         .end_trb = &xhci->cmd_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1950                         .input_dma = xhci->cmd_ring->first_seg->dma,
1951                         .result_seg = NULL,
1952                 },
1953                 /* TRB in this ring, but after this TD */
1954                 {       .input_seg = xhci->event_ring->first_seg,
1955                         .start_trb = &xhci->event_ring->first_seg->trbs[0],
1956                         .end_trb = &xhci->event_ring->first_seg->trbs[3],
1957                         .input_dma = xhci->event_ring->first_seg->dma + 4*16,
1958                         .result_seg = NULL,
1959                 },
1960                 /* TRB in this ring, but before this TD */
1961                 {       .input_seg = xhci->event_ring->first_seg,
1962                         .start_trb = &xhci->event_ring->first_seg->trbs[3],
1963                         .end_trb = &xhci->event_ring->first_seg->trbs[6],
1964                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1965                         .result_seg = NULL,
1966                 },
1967                 /* TRB in this ring, but after this wrapped TD */
1968                 {       .input_seg = xhci->event_ring->first_seg,
1969                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1970                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1971                         .input_dma = xhci->event_ring->first_seg->dma + 2*16,
1972                         .result_seg = NULL,
1973                 },
1974                 /* TRB in this ring, but before this wrapped TD */
1975                 {       .input_seg = xhci->event_ring->first_seg,
1976                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1977                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1978                         .input_dma = xhci->event_ring->first_seg->dma + (TRBS_PER_SEGMENT - 4)*16,
1979                         .result_seg = NULL,
1980                 },
1981                 /* TRB not in this ring, and we have a wrapped TD */
1982                 {       .input_seg = xhci->event_ring->first_seg,
1983                         .start_trb = &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 3],
1984                         .end_trb = &xhci->event_ring->first_seg->trbs[1],
1985                         .input_dma = xhci->cmd_ring->first_seg->dma + 2*16,
1986                         .result_seg = NULL,
1987                 },
1988         };
1989
1990         unsigned int num_tests;
1991         int i, ret;
1992
1993         num_tests = ARRAY_SIZE(simple_test_vector);
1994         for (i = 0; i < num_tests; i++) {
1995                 ret = xhci_test_trb_in_td(xhci,
1996                                 xhci->event_ring->first_seg,
1997                                 xhci->event_ring->first_seg->trbs,
1998                                 &xhci->event_ring->first_seg->trbs[TRBS_PER_SEGMENT - 1],
1999                                 simple_test_vector[i].input_dma,
2000                                 simple_test_vector[i].result_seg,
2001                                 "Simple", i);
2002                 if (ret < 0)
2003                         return ret;
2004         }
2005
2006         num_tests = ARRAY_SIZE(complex_test_vector);
2007         for (i = 0; i < num_tests; i++) {
2008                 ret = xhci_test_trb_in_td(xhci,
2009                                 complex_test_vector[i].input_seg,
2010                                 complex_test_vector[i].start_trb,
2011                                 complex_test_vector[i].end_trb,
2012                                 complex_test_vector[i].input_dma,
2013                                 complex_test_vector[i].result_seg,
2014                                 "Complex", i);
2015                 if (ret < 0)
2016                         return ret;
2017         }
2018         xhci_dbg(xhci, "TRB math tests passed.\n");
2019         return 0;
2020 }
2021
2022 static void xhci_set_hc_event_deq(struct xhci_hcd *xhci)
2023 {
2024         u64 temp;
2025         dma_addr_t deq;
2026
2027         deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2028                         xhci->event_ring->dequeue);
2029         if (deq == 0 && !in_interrupt())
2030                 xhci_warn(xhci, "WARN something wrong with SW event ring "
2031                                 "dequeue ptr.\n");
2032         /* Update HC event ring dequeue pointer */
2033         temp = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2034         temp &= ERST_PTR_MASK;
2035         /* Don't clear the EHB bit (which is RW1C) because
2036          * there might be more events to service.
2037          */
2038         temp &= ~ERST_EHB;
2039         xhci_dbg(xhci, "// Write event ring dequeue pointer, "
2040                         "preserving EHB bit\n");
2041         xhci_write_64(xhci, ((u64) deq & (u64) ~ERST_PTR_MASK) | temp,
2042                         &xhci->ir_set->erst_dequeue);
2043 }
2044
2045 static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
2046                 __le32 __iomem *addr, u8 major_revision, int max_caps)
2047 {
2048         u32 temp, port_offset, port_count;
2049         int i;
2050
2051         if (major_revision > 0x03) {
2052                 xhci_warn(xhci, "Ignoring unknown port speed, "
2053                                 "Ext Cap %p, revision = 0x%x\n",
2054                                 addr, major_revision);
2055                 /* Ignoring port protocol we can't understand. FIXME */
2056                 return;
2057         }
2058
2059         /* Port offset and count in the third dword, see section 7.2 */
2060         temp = xhci_readl(xhci, addr + 2);
2061         port_offset = XHCI_EXT_PORT_OFF(temp);
2062         port_count = XHCI_EXT_PORT_COUNT(temp);
2063         xhci_dbg(xhci, "Ext Cap %p, port offset = %u, "
2064                         "count = %u, revision = 0x%x\n",
2065                         addr, port_offset, port_count, major_revision);
2066         /* Port count includes the current port offset */
2067         if (port_offset == 0 || (port_offset + port_count - 1) > num_ports)
2068                 /* WTF? "Valid values are ‘1’ to MaxPorts" */
2069                 return;
2070
2071         /* cache usb2 port capabilities */
2072         if (major_revision < 0x03 && xhci->num_ext_caps < max_caps)
2073                 xhci->ext_caps[xhci->num_ext_caps++] = temp;
2074
2075         /* Check the host's USB2 LPM capability */
2076         if ((xhci->hci_version == 0x96) && (major_revision != 0x03) &&
2077                         (temp & XHCI_L1C)) {
2078                 xhci_dbg(xhci, "xHCI 0.96: support USB2 software lpm\n");
2079                 xhci->sw_lpm_support = 1;
2080         }
2081
2082         if ((xhci->hci_version >= 0x100) && (major_revision != 0x03)) {
2083                 xhci_dbg(xhci, "xHCI 1.0: support USB2 software lpm\n");
2084                 xhci->sw_lpm_support = 1;
2085                 if (temp & XHCI_HLC) {
2086                         xhci_dbg(xhci, "xHCI 1.0: support USB2 hardware lpm\n");
2087                         xhci->hw_lpm_support = 1;
2088                 }
2089         }
2090
2091         port_offset--;
2092         for (i = port_offset; i < (port_offset + port_count); i++) {
2093                 /* Duplicate entry.  Ignore the port if the revisions differ. */
2094                 if (xhci->port_array[i] != 0) {
2095                         xhci_warn(xhci, "Duplicate port entry, Ext Cap %p,"
2096                                         " port %u\n", addr, i);
2097                         xhci_warn(xhci, "Port was marked as USB %u, "
2098                                         "duplicated as USB %u\n",
2099                                         xhci->port_array[i], major_revision);
2100                         /* Only adjust the roothub port counts if we haven't
2101                          * found a similar duplicate.
2102                          */
2103                         if (xhci->port_array[i] != major_revision &&
2104                                 xhci->port_array[i] != DUPLICATE_ENTRY) {
2105                                 if (xhci->port_array[i] == 0x03)
2106                                         xhci->num_usb3_ports--;
2107                                 else
2108                                         xhci->num_usb2_ports--;
2109                                 xhci->port_array[i] = DUPLICATE_ENTRY;
2110                         }
2111                         /* FIXME: Should we disable the port? */
2112                         continue;
2113                 }
2114                 xhci->port_array[i] = major_revision;
2115                 if (major_revision == 0x03)
2116                         xhci->num_usb3_ports++;
2117                 else
2118                         xhci->num_usb2_ports++;
2119         }
2120         /* FIXME: Should we disable ports not in the Extended Capabilities? */
2121 }
2122
2123 /*
2124  * Scan the Extended Capabilities for the "Supported Protocol Capabilities" that
2125  * specify what speeds each port is supposed to be.  We can't count on the port
2126  * speed bits in the PORTSC register being correct until a device is connected,
2127  * but we need to set up the two fake roothubs with the correct number of USB
2128  * 3.0 and USB 2.0 ports at host controller initialization time.
2129  */
2130 static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
2131 {
2132         __le32 __iomem *addr, *tmp_addr;
2133         u32 offset, tmp_offset;
2134         unsigned int num_ports;
2135         int i, j, port_index;
2136         int cap_count = 0;
2137
2138         addr = &xhci->cap_regs->hcc_params;
2139         offset = XHCI_HCC_EXT_CAPS(xhci_readl(xhci, addr));
2140         if (offset == 0) {
2141                 xhci_err(xhci, "No Extended Capability registers, "
2142                                 "unable to set up roothub.\n");
2143                 return -ENODEV;
2144         }
2145
2146         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
2147         xhci->port_array = kzalloc(sizeof(*xhci->port_array)*num_ports, flags);
2148         if (!xhci->port_array)
2149                 return -ENOMEM;
2150
2151         xhci->rh_bw = kzalloc(sizeof(*xhci->rh_bw)*num_ports, flags);
2152         if (!xhci->rh_bw)
2153                 return -ENOMEM;
2154         for (i = 0; i < num_ports; i++) {
2155                 struct xhci_interval_bw_table *bw_table;
2156
2157                 INIT_LIST_HEAD(&xhci->rh_bw[i].tts);
2158                 bw_table = &xhci->rh_bw[i].bw_table;
2159                 for (j = 0; j < XHCI_MAX_INTERVAL; j++)
2160                         INIT_LIST_HEAD(&bw_table->interval_bw[j].endpoints);
2161         }
2162
2163         /*
2164          * For whatever reason, the first capability offset is from the
2165          * capability register base, not from the HCCPARAMS register.
2166          * See section 5.3.6 for offset calculation.
2167          */
2168         addr = &xhci->cap_regs->hc_capbase + offset;
2169
2170         tmp_addr = addr;
2171         tmp_offset = offset;
2172
2173         /* count extended protocol capability entries for later caching */
2174         do {
2175                 u32 cap_id;
2176                 cap_id = xhci_readl(xhci, tmp_addr);
2177                 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2178                         cap_count++;
2179                 tmp_offset = XHCI_EXT_CAPS_NEXT(cap_id);
2180                 tmp_addr += tmp_offset;
2181         } while (tmp_offset);
2182
2183         xhci->ext_caps = kzalloc(sizeof(*xhci->ext_caps) * cap_count, flags);
2184         if (!xhci->ext_caps)
2185                 return -ENOMEM;
2186
2187         while (1) {
2188                 u32 cap_id;
2189
2190                 cap_id = xhci_readl(xhci, addr);
2191                 if (XHCI_EXT_CAPS_ID(cap_id) == XHCI_EXT_CAPS_PROTOCOL)
2192                         xhci_add_in_port(xhci, num_ports, addr,
2193                                         (u8) XHCI_EXT_PORT_MAJOR(cap_id),
2194                                         cap_count);
2195                 offset = XHCI_EXT_CAPS_NEXT(cap_id);
2196                 if (!offset || (xhci->num_usb2_ports + xhci->num_usb3_ports)
2197                                 == num_ports)
2198                         break;
2199                 /*
2200                  * Once you're into the Extended Capabilities, the offset is
2201                  * always relative to the register holding the offset.
2202                  */
2203                 addr += offset;
2204         }
2205
2206         if (xhci->num_usb2_ports == 0 && xhci->num_usb3_ports == 0) {
2207                 xhci_warn(xhci, "No ports on the roothubs?\n");
2208                 return -ENODEV;
2209         }
2210         xhci_dbg(xhci, "Found %u USB 2.0 ports and %u USB 3.0 ports.\n",
2211                         xhci->num_usb2_ports, xhci->num_usb3_ports);
2212
2213         /* Place limits on the number of roothub ports so that the hub
2214          * descriptors aren't longer than the USB core will allocate.
2215          */
2216         if (xhci->num_usb3_ports > 15) {
2217                 xhci_dbg(xhci, "Limiting USB 3.0 roothub ports to 15.\n");
2218                 xhci->num_usb3_ports = 15;
2219         }
2220         if (xhci->num_usb2_ports > USB_MAXCHILDREN) {
2221                 xhci_dbg(xhci, "Limiting USB 2.0 roothub ports to %u.\n",
2222                                 USB_MAXCHILDREN);
2223                 xhci->num_usb2_ports = USB_MAXCHILDREN;
2224         }
2225
2226         /*
2227          * Note we could have all USB 3.0 ports, or all USB 2.0 ports.
2228          * Not sure how the USB core will handle a hub with no ports...
2229          */
2230         if (xhci->num_usb2_ports) {
2231                 xhci->usb2_ports = kmalloc(sizeof(*xhci->usb2_ports)*
2232                                 xhci->num_usb2_ports, flags);
2233                 if (!xhci->usb2_ports)
2234                         return -ENOMEM;
2235
2236                 port_index = 0;
2237                 for (i = 0; i < num_ports; i++) {
2238                         if (xhci->port_array[i] == 0x03 ||
2239                                         xhci->port_array[i] == 0 ||
2240                                         xhci->port_array[i] == DUPLICATE_ENTRY)
2241                                 continue;
2242
2243                         xhci->usb2_ports[port_index] =
2244                                 &xhci->op_regs->port_status_base +
2245                                 NUM_PORT_REGS*i;
2246                         xhci_dbg(xhci, "USB 2.0 port at index %u, "
2247                                         "addr = %p\n", i,
2248                                         xhci->usb2_ports[port_index]);
2249                         port_index++;
2250                         if (port_index == xhci->num_usb2_ports)
2251                                 break;
2252                 }
2253         }
2254         if (xhci->num_usb3_ports) {
2255                 xhci->usb3_ports = kmalloc(sizeof(*xhci->usb3_ports)*
2256                                 xhci->num_usb3_ports, flags);
2257                 if (!xhci->usb3_ports)
2258                         return -ENOMEM;
2259
2260                 port_index = 0;
2261                 for (i = 0; i < num_ports; i++)
2262                         if (xhci->port_array[i] == 0x03) {
2263                                 xhci->usb3_ports[port_index] =
2264                                         &xhci->op_regs->port_status_base +
2265                                         NUM_PORT_REGS*i;
2266                                 xhci_dbg(xhci, "USB 3.0 port at index %u, "
2267                                                 "addr = %p\n", i,
2268                                                 xhci->usb3_ports[port_index]);
2269                                 port_index++;
2270                                 if (port_index == xhci->num_usb3_ports)
2271                                         break;
2272                         }
2273         }
2274         return 0;
2275 }
2276
2277 int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
2278 {
2279         dma_addr_t      dma;
2280         struct device   *dev = xhci_to_hcd(xhci)->self.controller;
2281         unsigned int    val, val2;
2282         u64             val_64;
2283         struct xhci_segment     *seg;
2284         u32 page_size, temp;
2285         int i;
2286
2287         INIT_LIST_HEAD(&xhci->lpm_failed_devs);
2288         INIT_LIST_HEAD(&xhci->cancel_cmd_list);
2289
2290         page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
2291         xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
2292         for (i = 0; i < 16; i++) {
2293                 if ((0x1 & page_size) != 0)
2294                         break;
2295                 page_size = page_size >> 1;
2296         }
2297         if (i < 16)
2298                 xhci_dbg(xhci, "Supported page size of %iK\n", (1 << (i+12)) / 1024);
2299         else
2300                 xhci_warn(xhci, "WARN: no supported page size\n");
2301         /* Use 4K pages, since that's common and the minimum the HC supports */
2302         xhci->page_shift = 12;
2303         xhci->page_size = 1 << xhci->page_shift;
2304         xhci_dbg(xhci, "HCD page size set to %iK\n", xhci->page_size / 1024);
2305
2306         /*
2307          * Program the Number of Device Slots Enabled field in the CONFIG
2308          * register with the max value of slots the HC can handle.
2309          */
2310         val = HCS_MAX_SLOTS(xhci_readl(xhci, &xhci->cap_regs->hcs_params1));
2311         xhci_dbg(xhci, "// xHC can handle at most %d device slots.\n",
2312                         (unsigned int) val);
2313         val2 = xhci_readl(xhci, &xhci->op_regs->config_reg);
2314         val |= (val2 & ~HCS_SLOTS_MASK);
2315         xhci_dbg(xhci, "// Setting Max device slots reg = 0x%x.\n",
2316                         (unsigned int) val);
2317         xhci_writel(xhci, val, &xhci->op_regs->config_reg);
2318
2319         /*
2320          * Section 5.4.8 - doorbell array must be
2321          * "physically contiguous and 64-byte (cache line) aligned".
2322          */
2323         xhci->dcbaa = dma_alloc_coherent(dev, sizeof(*xhci->dcbaa), &dma,
2324                         GFP_KERNEL);
2325         if (!xhci->dcbaa)
2326                 goto fail;
2327         memset(xhci->dcbaa, 0, sizeof *(xhci->dcbaa));
2328         xhci->dcbaa->dma = dma;
2329         xhci_dbg(xhci, "// Device context base array address = 0x%llx (DMA), %p (virt)\n",
2330                         (unsigned long long)xhci->dcbaa->dma, xhci->dcbaa);
2331         xhci_write_64(xhci, dma, &xhci->op_regs->dcbaa_ptr);
2332
2333         /*
2334          * Initialize the ring segment pool.  The ring must be a contiguous
2335          * structure comprised of TRBs.  The TRBs must be 16 byte aligned,
2336          * however, the command ring segment needs 64-byte aligned segments,
2337          * so we pick the greater alignment need.
2338          */
2339         xhci->segment_pool = dma_pool_create("xHCI ring segments", dev,
2340                         TRB_SEGMENT_SIZE, 64, xhci->page_size);
2341
2342         /* See Table 46 and Note on Figure 55 */
2343         xhci->device_pool = dma_pool_create("xHCI input/output contexts", dev,
2344                         2112, 64, xhci->page_size);
2345         if (!xhci->segment_pool || !xhci->device_pool)
2346                 goto fail;
2347
2348         /* Linear stream context arrays don't have any boundary restrictions,
2349          * and only need to be 16-byte aligned.
2350          */
2351         xhci->small_streams_pool =
2352                 dma_pool_create("xHCI 256 byte stream ctx arrays",
2353                         dev, SMALL_STREAM_ARRAY_SIZE, 16, 0);
2354         xhci->medium_streams_pool =
2355                 dma_pool_create("xHCI 1KB stream ctx arrays",
2356                         dev, MEDIUM_STREAM_ARRAY_SIZE, 16, 0);
2357         /* Any stream context array bigger than MEDIUM_STREAM_ARRAY_SIZE
2358          * will be allocated with dma_alloc_coherent()
2359          */
2360
2361         if (!xhci->small_streams_pool || !xhci->medium_streams_pool)
2362                 goto fail;
2363
2364         /* Set up the command ring to have one segments for now. */
2365         xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, flags);
2366         if (!xhci->cmd_ring)
2367                 goto fail;
2368         xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
2369         xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
2370                         (unsigned long long)xhci->cmd_ring->first_seg->dma);
2371
2372         /* Set the address in the Command Ring Control register */
2373         val_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
2374         val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
2375                 (xhci->cmd_ring->first_seg->dma & (u64) ~CMD_RING_RSVD_BITS) |
2376                 xhci->cmd_ring->cycle_state;
2377         xhci_dbg(xhci, "// Setting command ring address to 0x%x\n", val);
2378         xhci_write_64(xhci, val_64, &xhci->op_regs->cmd_ring);
2379         xhci_dbg_cmd_ptrs(xhci);
2380
2381         xhci->lpm_command = xhci_alloc_command(xhci, true, true, flags);
2382         if (!xhci->lpm_command)
2383                 goto fail;
2384
2385         /* Reserve one command ring TRB for disabling LPM.
2386          * Since the USB core grabs the shared usb_bus bandwidth mutex before
2387          * disabling LPM, we only need to reserve one TRB for all devices.
2388          */
2389         xhci->cmd_ring_reserved_trbs++;
2390
2391         val = xhci_readl(xhci, &xhci->cap_regs->db_off);
2392         val &= DBOFF_MASK;
2393         xhci_dbg(xhci, "// Doorbell array is located at offset 0x%x"
2394                         " from cap regs base addr\n", val);
2395         xhci->dba = (void __iomem *) xhci->cap_regs + val;
2396         xhci_dbg_regs(xhci);
2397         xhci_print_run_regs(xhci);
2398         /* Set ir_set to interrupt register set 0 */
2399         xhci->ir_set = &xhci->run_regs->ir_set[0];
2400
2401         /*
2402          * Event ring setup: Allocate a normal ring, but also setup
2403          * the event ring segment table (ERST).  Section 4.9.3.
2404          */
2405         xhci_dbg(xhci, "// Allocating event ring\n");
2406         xhci->event_ring = xhci_ring_alloc(xhci, ERST_NUM_SEGS, 1, TYPE_EVENT,
2407                                                 flags);
2408         if (!xhci->event_ring)
2409                 goto fail;
2410         if (xhci_check_trb_in_td_math(xhci, flags) < 0)
2411                 goto fail;
2412
2413         xhci->erst.entries = dma_alloc_coherent(dev,
2414                         sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS, &dma,
2415                         GFP_KERNEL);
2416         if (!xhci->erst.entries)
2417                 goto fail;
2418         xhci_dbg(xhci, "// Allocated event ring segment table at 0x%llx\n",
2419                         (unsigned long long)dma);
2420
2421         memset(xhci->erst.entries, 0, sizeof(struct xhci_erst_entry)*ERST_NUM_SEGS);
2422         xhci->erst.num_entries = ERST_NUM_SEGS;
2423         xhci->erst.erst_dma_addr = dma;
2424         xhci_dbg(xhci, "Set ERST to 0; private num segs = %i, virt addr = %p, dma addr = 0x%llx\n",
2425                         xhci->erst.num_entries,
2426                         xhci->erst.entries,
2427                         (unsigned long long)xhci->erst.erst_dma_addr);
2428
2429         /* set ring base address and size for each segment table entry */
2430         for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
2431                 struct xhci_erst_entry *entry = &xhci->erst.entries[val];
2432                 entry->seg_addr = cpu_to_le64(seg->dma);
2433                 entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
2434                 entry->rsvd = 0;
2435                 seg = seg->next;
2436         }
2437
2438         /* set ERST count with the number of entries in the segment table */
2439         val = xhci_readl(xhci, &xhci->ir_set->erst_size);
2440         val &= ERST_SIZE_MASK;
2441         val |= ERST_NUM_SEGS;
2442         xhci_dbg(xhci, "// Write ERST size = %i to ir_set 0 (some bits preserved)\n",
2443                         val);
2444         xhci_writel(xhci, val, &xhci->ir_set->erst_size);
2445
2446         xhci_dbg(xhci, "// Set ERST entries to point to event ring.\n");
2447         /* set the segment table base address */
2448         xhci_dbg(xhci, "// Set ERST base address for ir_set 0 = 0x%llx\n",
2449                         (unsigned long long)xhci->erst.erst_dma_addr);
2450         val_64 = xhci_read_64(xhci, &xhci->ir_set->erst_base);
2451         val_64 &= ERST_PTR_MASK;
2452         val_64 |= (xhci->erst.erst_dma_addr & (u64) ~ERST_PTR_MASK);
2453         xhci_write_64(xhci, val_64, &xhci->ir_set->erst_base);
2454
2455         /* Set the event ring dequeue address */
2456         xhci_set_hc_event_deq(xhci);
2457         xhci_dbg(xhci, "Wrote ERST address to ir_set 0.\n");
2458         xhci_print_ir_set(xhci, 0);
2459
2460         /*
2461          * XXX: Might need to set the Interrupter Moderation Register to
2462          * something other than the default (~1ms minimum between interrupts).
2463          * See section 5.5.1.2.
2464          */
2465         init_completion(&xhci->addr_dev);
2466         for (i = 0; i < MAX_HC_SLOTS; ++i)
2467                 xhci->devs[i] = NULL;
2468         for (i = 0; i < USB_MAXCHILDREN; ++i) {
2469                 xhci->bus_state[0].resume_done[i] = 0;
2470                 xhci->bus_state[1].resume_done[i] = 0;
2471         }
2472
2473         if (scratchpad_alloc(xhci, flags))
2474                 goto fail;
2475         if (xhci_setup_port_arrays(xhci, flags))
2476                 goto fail;
2477
2478         /* Enable USB 3.0 device notifications for function remote wake, which
2479          * is necessary for allowing USB 3.0 devices to do remote wakeup from
2480          * U3 (device suspend).
2481          */
2482         temp = xhci_readl(xhci, &xhci->op_regs->dev_notification);
2483         temp &= ~DEV_NOTE_MASK;
2484         temp |= DEV_NOTE_FWAKE;
2485         xhci_writel(xhci, temp, &xhci->op_regs->dev_notification);
2486
2487         return 0;
2488
2489 fail:
2490         xhci_warn(xhci, "Couldn't initialize memory\n");
2491         xhci_halt(xhci);
2492         xhci_reset(xhci);
2493         xhci_mem_cleanup(xhci);
2494         return -ENOMEM;
2495 }