drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <eugeni.dodonov@intel.com>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 #define FORCEWAKE_ACK_TIMEOUT_MS 2
  35
  36 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
  37  * framebuffer contents in-memory, aiming at reducing the required bandwidth
  38  * during in-memory transfers and, therefore, reduce the power packet.
  39  *
  40  * The benefits of FBC are mostly visible with solid backgrounds and
  41  * variation-less patterns.
  42  *
  43  * FBC-related functionality can be enabled by the means of the
  44  * i915.i915_enable_fbc parameter
  45  */
  46
  47 static bool intel_crtc_active(struct drm_crtc *crtc)
  48 {
  49         /* Be paranoid as we can arrive here with only partial
  50          * state retrieved from the hardware during setup.
  51          */
  52         return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
  53 }
  54
  55 static void i8xx_disable_fbc(struct drm_device *dev)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58         u32 fbc_ctl;
  59
  60         /* Disable compression */
  61         fbc_ctl = I915_READ(FBC_CONTROL);
  62         if ((fbc_ctl & FBC_CTL_EN) == 0)
  63                 return;
  64
  65         fbc_ctl &= ~FBC_CTL_EN;
  66         I915_WRITE(FBC_CONTROL, fbc_ctl);
  67
  68         /* Wait for compressing bit to clear */
  69         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
  70                 DRM_DEBUG_KMS("FBC idle timed out\n");
  71                 return;
  72         }
  73
  74         DRM_DEBUG_KMS("disabled FBC\n");
  75 }
  76
  77 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
  78 {
  79         struct drm_device *dev = crtc->dev;
  80         struct drm_i915_private *dev_priv = dev->dev_private;
  81         struct drm_framebuffer *fb = crtc->fb;
  82         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
  83         struct drm_i915_gem_object *obj = intel_fb->obj;
  84         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  85         int cfb_pitch;
  86         int plane, i;
  87         u32 fbc_ctl, fbc_ctl2;
  88
  89         cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
  90         if (fb->pitches[0] < cfb_pitch)
  91                 cfb_pitch = fb->pitches[0];
  92
  93         /* FBC_CTL wants 64B units */
  94         cfb_pitch = (cfb_pitch / 64) - 1;
  95         plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
  96
  97         /* Clear old tags */
  98         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
  99                 I915_WRITE(FBC_TAG + (i * 4), 0);
 100
 101         /* Set it up... */
 102         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
 103         fbc_ctl2 |= plane;
 104         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
 105         I915_WRITE(FBC_FENCE_OFF, crtc->y);
 106
 107         /* enable it... */
 108         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
 109         if (IS_I945GM(dev))
 110                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
 111         fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
 112         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
 113         fbc_ctl |= obj->fence_reg;
 114         I915_WRITE(FBC_CONTROL, fbc_ctl);
 115
 116         DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
 117                       cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
 118 }
 119
 120 static bool i8xx_fbc_enabled(struct drm_device *dev)
 121 {
 122         struct drm_i915_private *dev_priv = dev->dev_private;
 123
 124         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
 125 }
 126
 127 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 128 {
 129         struct drm_device *dev = crtc->dev;
 130         struct drm_i915_private *dev_priv = dev->dev_private;
 131         struct drm_framebuffer *fb = crtc->fb;
 132         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 133         struct drm_i915_gem_object *obj = intel_fb->obj;
 134         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 135         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 136         unsigned long stall_watermark = 200;
 137         u32 dpfc_ctl;
 138
 139         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
 140         dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
 141         I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
 142
 143         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 144                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 145                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 146         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
 147
 148         /* enable it... */
 149         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
 150
 151         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 152 }
 153
 154 static void g4x_disable_fbc(struct drm_device *dev)
 155 {
 156         struct drm_i915_private *dev_priv = dev->dev_private;
 157         u32 dpfc_ctl;
 158
 159         /* Disable compression */
 160         dpfc_ctl = I915_READ(DPFC_CONTROL);
 161         if (dpfc_ctl & DPFC_CTL_EN) {
 162                 dpfc_ctl &= ~DPFC_CTL_EN;
 163                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
 164
 165                 DRM_DEBUG_KMS("disabled FBC\n");
 166         }
 167 }
 168
 169 static bool g4x_fbc_enabled(struct drm_device *dev)
 170 {
 171         struct drm_i915_private *dev_priv = dev->dev_private;
 172
 173         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
 174 }
 175
 176 static void sandybridge_blit_fbc_update(struct drm_device *dev)
 177 {
 178         struct drm_i915_private *dev_priv = dev->dev_private;
 179         u32 blt_ecoskpd;
 180
 181         /* Make sure blitter notifies FBC of writes */
 182         gen6_gt_force_wake_get(dev_priv);
 183         blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
 184         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
 185                 GEN6_BLITTER_LOCK_SHIFT;
 186         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 187         blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
 188         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 189         blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
 190                          GEN6_BLITTER_LOCK_SHIFT);
 191         I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
 192         POSTING_READ(GEN6_BLITTER_ECOSKPD);
 193         gen6_gt_force_wake_put(dev_priv);
 194 }
 195
 196 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 197 {
 198         struct drm_device *dev = crtc->dev;
 199         struct drm_i915_private *dev_priv = dev->dev_private;
 200         struct drm_framebuffer *fb = crtc->fb;
 201         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
 202         struct drm_i915_gem_object *obj = intel_fb->obj;
 203         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 204         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
 205         unsigned long stall_watermark = 200;
 206         u32 dpfc_ctl;
 207
 208         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 209         dpfc_ctl &= DPFC_RESERVED;
 210         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
 211         /* Set persistent mode for front-buffer rendering, ala X. */
 212         dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
 213         dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
 214         I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
 215
 216         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
 217                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
 218                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
 219         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
 220         I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
 221         /* enable it... */
 222         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
 223
 224         if (IS_GEN6(dev)) {
 225                 I915_WRITE(SNB_DPFC_CTL_SA,
 226                            SNB_CPU_FENCE_ENABLE | obj->fence_reg);
 227                 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
 228                 sandybridge_blit_fbc_update(dev);
 229         }
 230
 231         DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
 232 }
 233
 234 static void ironlake_disable_fbc(struct drm_device *dev)
 235 {
 236         struct drm_i915_private *dev_priv = dev->dev_private;
 237         u32 dpfc_ctl;
 238
 239         /* Disable compression */
 240         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
 241         if (dpfc_ctl & DPFC_CTL_EN) {
 242                 dpfc_ctl &= ~DPFC_CTL_EN;
 243                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
 244
 245                 DRM_DEBUG_KMS("disabled FBC\n");
 246         }
 247 }
 248
 249 static bool ironlake_fbc_enabled(struct drm_device *dev)
 250 {
 251         struct drm_i915_private *dev_priv = dev->dev_private;
 252
 253         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
 254 }
 255
 256 bool intel_fbc_enabled(struct drm_device *dev)
 257 {
 258         struct drm_i915_private *dev_priv = dev->dev_private;
 259
 260         if (!dev_priv->display.fbc_enabled)
 261                 return false;
 262
 263         return dev_priv->display.fbc_enabled(dev);
 264 }
 265
 266 static void intel_fbc_work_fn(struct work_struct *__work)
 267 {
 268         struct intel_fbc_work *work =
 269                 container_of(to_delayed_work(__work),
 270                              struct intel_fbc_work, work);
 271         struct drm_device *dev = work->crtc->dev;
 272         struct drm_i915_private *dev_priv = dev->dev_private;
 273
 274         mutex_lock(&dev->struct_mutex);
 275         if (work == dev_priv->fbc_work) {
 276                 /* Double check that we haven't switched fb without cancelling
 277                  * the prior work.
 278                  */
 279                 if (work->crtc->fb == work->fb) {
 280                         dev_priv->display.enable_fbc(work->crtc,
 281                                                      work->interval);
 282
 283                         dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
 284                         dev_priv->cfb_fb = work->crtc->fb->base.id;
 285                         dev_priv->cfb_y = work->crtc->y;
 286                 }
 287
 288                 dev_priv->fbc_work = NULL;
 289         }
 290         mutex_unlock(&dev->struct_mutex);
 291
 292         kfree(work);
 293 }
 294
 295 static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
 296 {
 297         if (dev_priv->fbc_work == NULL)
 298                 return;
 299
 300         DRM_DEBUG_KMS("cancelling pending FBC enable\n");
 301
 302         /* Synchronisation is provided by struct_mutex and checking of
 303          * dev_priv->fbc_work, so we can perform the cancellation
 304          * entirely asynchronously.
 305          */
 306         if (cancel_delayed_work(&dev_priv->fbc_work->work))
 307                 /* tasklet was killed before being run, clean up */
 308                 kfree(dev_priv->fbc_work);
 309
 310         /* Mark the work as no longer wanted so that if it does
 311          * wake-up (because the work was already running and waiting
 312          * for our mutex), it will discover that is no longer
 313          * necessary to run.
 314          */
 315         dev_priv->fbc_work = NULL;
 316 }
 317
 318 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
 319 {
 320         struct intel_fbc_work *work;
 321         struct drm_device *dev = crtc->dev;
 322         struct drm_i915_private *dev_priv = dev->dev_private;
 323
 324         if (!dev_priv->display.enable_fbc)
 325                 return;
 326
 327         intel_cancel_fbc_work(dev_priv);
 328
 329         work = kzalloc(sizeof *work, GFP_KERNEL);
 330         if (work == NULL) {
 331                 dev_priv->display.enable_fbc(crtc, interval);
 332                 return;
 333         }
 334
 335         work->crtc = crtc;
 336         work->fb = crtc->fb;
 337         work->interval = interval;
 338         INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
 339
 340         dev_priv->fbc_work = work;
 341
 342         DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
 343
 344         /* Delay the actual enabling to let pageflipping cease and the
 345          * display to settle before starting the compression. Note that
 346          * this delay also serves a second purpose: it allows for a
 347          * vblank to pass after disabling the FBC before we attempt
 348          * to modify the control registers.
 349          *
 350          * A more complicated solution would involve tracking vblanks
 351          * following the termination of the page-flipping sequence
 352          * and indeed performing the enable as a co-routine and not
 353          * waiting synchronously upon the vblank.
 354          */
 355         schedule_delayed_work(&work->work, msecs_to_jiffies(50));
 356 }
 357
 358 void intel_disable_fbc(struct drm_device *dev)
 359 {
 360         struct drm_i915_private *dev_priv = dev->dev_private;
 361
 362         intel_cancel_fbc_work(dev_priv);
 363
 364         if (!dev_priv->display.disable_fbc)
 365                 return;
 366
 367         dev_priv->display.disable_fbc(dev);
 368         dev_priv->cfb_plane = -1;
 369 }
 370
 371 /**
 372  * intel_update_fbc - enable/disable FBC as needed
 373  * @dev: the drm_device
 374  *
 375  * Set up the framebuffer compression hardware at mode set time.  We
 376  * enable it if possible:
 377  *   - plane A only (on pre-965)
 378  *   - no pixel mulitply/line duplication
 379  *   - no alpha buffer discard
 380  *   - no dual wide
 381  *   - framebuffer <= 2048 in width, 1536 in height
 382  *
 383  * We can't assume that any compression will take place (worst case),
 384  * so the compressed buffer has to be the same size as the uncompressed
 385  * one.  It also must reside (along with the line length buffer) in
 386  * stolen memory.
 387  *
 388  * We need to enable/disable FBC on a global basis.
 389  */
 390 void intel_update_fbc(struct drm_device *dev)
 391 {
 392         struct drm_i915_private *dev_priv = dev->dev_private;
 393         struct drm_crtc *crtc = NULL, *tmp_crtc;
 394         struct intel_crtc *intel_crtc;
 395         struct drm_framebuffer *fb;
 396         struct intel_framebuffer *intel_fb;
 397         struct drm_i915_gem_object *obj;
 398         int enable_fbc;
 399
 400         if (!i915_powersave)
 401                 return;
 402
 403         if (!I915_HAS_FBC(dev))
 404                 return;
 405
 406         /*
 407          * If FBC is already on, we just have to verify that we can
 408          * keep it that way...
 409          * Need to disable if:
 410          *   - more than one pipe is active
 411          *   - changing FBC params (stride, fence, mode)
 412          *   - new fb is too large to fit in compressed buffer
 413          *   - going to an unsupported config (interlace, pixel multiply, etc.)
 414          */
 415         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
 416                 if (intel_crtc_active(tmp_crtc) &&
 417                     !to_intel_crtc(tmp_crtc)->primary_disabled) {
 418                         if (crtc) {
 419                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
 420                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
 421                                 goto out_disable;
 422                         }
 423                         crtc = tmp_crtc;
 424                 }
 425         }
 426
 427         if (!crtc || crtc->fb == NULL) {
 428                 DRM_DEBUG_KMS("no output, disabling\n");
 429                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
 430                 goto out_disable;
 431         }
 432
 433         intel_crtc = to_intel_crtc(crtc);
 434         fb = crtc->fb;
 435         intel_fb = to_intel_framebuffer(fb);
 436         obj = intel_fb->obj;
 437
 438         enable_fbc = i915_enable_fbc;
 439         if (enable_fbc < 0) {
 440                 DRM_DEBUG_KMS("fbc set to per-chip default\n");
 441                 enable_fbc = 1;
 442                 if (INTEL_INFO(dev)->gen <= 6)
 443                         enable_fbc = 0;
 444         }
 445         if (!enable_fbc) {
 446                 DRM_DEBUG_KMS("fbc disabled per module param\n");
 447                 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
 448                 goto out_disable;
 449         }
 450         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
 451             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
 452                 DRM_DEBUG_KMS("mode incompatible with compression, "
 453                               "disabling\n");
 454                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
 455                 goto out_disable;
 456         }
 457         if ((crtc->mode.hdisplay > 2048) ||
 458             (crtc->mode.vdisplay > 1536)) {
 459                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
 460                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
 461                 goto out_disable;
 462         }
 463         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
 464                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
 465                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
 466                 goto out_disable;
 467         }
 468
 469         /* The use of a CPU fence is mandatory in order to detect writes
 470          * by the CPU to the scanout and trigger updates to the FBC.
 471          */
 472         if (obj->tiling_mode != I915_TILING_X ||
 473             obj->fence_reg == I915_FENCE_REG_NONE) {
 474                 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
 475                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
 476                 goto out_disable;
 477         }
 478
 479         /* If the kernel debugger is active, always disable compression */
 480         if (in_dbg_master())
 481                 goto out_disable;
 482
 483         if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
 484                 DRM_INFO("not enough stolen space for compressed buffer (need %zd bytes), disabling\n", intel_fb->obj->base.size);
 485                 DRM_INFO("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
 486                 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
 487                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
 488                 goto out_disable;
 489         }
 490
 491         /* If the scanout has not changed, don't modify the FBC settings.
 492          * Note that we make the fundamental assumption that the fb->obj
 493          * cannot be unpinned (and have its GTT offset and fence revoked)
 494          * without first being decoupled from the scanout and FBC disabled.
 495          */
 496         if (dev_priv->cfb_plane == intel_crtc->plane &&
 497             dev_priv->cfb_fb == fb->base.id &&
 498             dev_priv->cfb_y == crtc->y)
 499                 return;
 500
 501         if (intel_fbc_enabled(dev)) {
 502                 /* We update FBC along two paths, after changing fb/crtc
 503                  * configuration (modeswitching) and after page-flipping
 504                  * finishes. For the latter, we know that not only did
 505                  * we disable the FBC at the start of the page-flip
 506                  * sequence, but also more than one vblank has passed.
 507                  *
 508                  * For the former case of modeswitching, it is possible
 509                  * to switch between two FBC valid configurations
 510                  * instantaneously so we do need to disable the FBC
 511                  * before we can modify its control registers. We also
 512                  * have to wait for the next vblank for that to take
 513                  * effect. However, since we delay enabling FBC we can
 514                  * assume that a vblank has passed since disabling and
 515                  * that we can safely alter the registers in the deferred
 516                  * callback.
 517                  *
 518                  * In the scenario that we go from a valid to invalid
 519                  * and then back to valid FBC configuration we have
 520                  * no strict enforcement that a vblank occurred since
 521                  * disabling the FBC. However, along all current pipe
 522                  * disabling paths we do need to wait for a vblank at
 523                  * some point. And we wait before enabling FBC anyway.
 524                  */
 525                 DRM_DEBUG_KMS("disabling active FBC for update\n");
 526                 intel_disable_fbc(dev);
 527         }
 528
 529         intel_enable_fbc(crtc, 500);
 530         return;
 531
 532 out_disable:
 533         /* Multiple disables should be harmless */
 534         if (intel_fbc_enabled(dev)) {
 535                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
 536                 intel_disable_fbc(dev);
 537         }
 538         i915_gem_stolen_cleanup_compression(dev);
 539 }
 540
 541 static void i915_pineview_get_mem_freq(struct drm_device *dev)
 542 {
 543         drm_i915_private_t *dev_priv = dev->dev_private;
 544         u32 tmp;
 545
 546         tmp = I915_READ(CLKCFG);
 547
 548         switch (tmp & CLKCFG_FSB_MASK) {
 549         case CLKCFG_FSB_533:
 550                 dev_priv->fsb_freq = 533; /* 133*4 */
 551                 break;
 552         case CLKCFG_FSB_800:
 553                 dev_priv->fsb_freq = 800; /* 200*4 */
 554                 break;
 555         case CLKCFG_FSB_667:
 556                 dev_priv->fsb_freq =  667; /* 167*4 */
 557                 break;
 558         case CLKCFG_FSB_400:
 559                 dev_priv->fsb_freq = 400; /* 100*4 */
 560                 break;
 561         }
 562
 563         switch (tmp & CLKCFG_MEM_MASK) {
 564         case CLKCFG_MEM_533:
 565                 dev_priv->mem_freq = 533;
 566                 break;
 567         case CLKCFG_MEM_667:
 568                 dev_priv->mem_freq = 667;
 569                 break;
 570         case CLKCFG_MEM_800:
 571                 dev_priv->mem_freq = 800;
 572                 break;
 573         }
 574
 575         /* detect pineview DDR3 setting */
 576         tmp = I915_READ(CSHRDDR3CTL);
 577         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 578 }
 579
 580 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 581 {
 582         drm_i915_private_t *dev_priv = dev->dev_private;
 583         u16 ddrpll, csipll;
 584
 585         ddrpll = I915_READ16(DDRMPLL1);
 586         csipll = I915_READ16(CSIPLL0);
 587
 588         switch (ddrpll & 0xff) {
 589         case 0xc:
 590                 dev_priv->mem_freq = 800;
 591                 break;
 592         case 0x10:
 593                 dev_priv->mem_freq = 1066;
 594                 break;
 595         case 0x14:
 596                 dev_priv->mem_freq = 1333;
 597                 break;
 598         case 0x18:
 599                 dev_priv->mem_freq = 1600;
 600                 break;
 601         default:
 602                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 603                                  ddrpll & 0xff);
 604                 dev_priv->mem_freq = 0;
 605                 break;
 606         }
 607
 608         dev_priv->ips.r_t = dev_priv->mem_freq;
 609
 610         switch (csipll & 0x3ff) {
 611         case 0x00c:
 612                 dev_priv->fsb_freq = 3200;
 613                 break;
 614         case 0x00e:
 615                 dev_priv->fsb_freq = 3733;
 616                 break;
 617         case 0x010:
 618                 dev_priv->fsb_freq = 4266;
 619                 break;
 620         case 0x012:
 621                 dev_priv->fsb_freq = 4800;
 622                 break;
 623         case 0x014:
 624                 dev_priv->fsb_freq = 5333;
 625                 break;
 626         case 0x016:
 627                 dev_priv->fsb_freq = 5866;
 628                 break;
 629         case 0x018:
 630                 dev_priv->fsb_freq = 6400;
 631                 break;
 632         default:
 633                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 634                                  csipll & 0x3ff);
 635                 dev_priv->fsb_freq = 0;
 636                 break;
 637         }
 638
 639         if (dev_priv->fsb_freq == 3200) {
 640                 dev_priv->ips.c_m = 0;
 641         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 642                 dev_priv->ips.c_m = 1;
 643         } else {
 644                 dev_priv->ips.c_m = 2;
 645         }
 646 }
 647
 648 static const struct cxsr_latency cxsr_latency_table[] = {
 649         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 650         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 651         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 652         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 653         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 654
 655         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 656         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 657         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 658         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 659         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 660
 661         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 662         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 663         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 664         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 665         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 666
 667         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 668         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 669         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 670         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 671         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 672
 673         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 674         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 675         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 676         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 677         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 678
 679         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 680         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 681         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 682         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 683         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 684 };
 685
 686 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 687                                                          int is_ddr3,
 688                                                          int fsb,
 689                                                          int mem)
 690 {
 691         const struct cxsr_latency *latency;
 692         int i;
 693
 694         if (fsb == 0 || mem == 0)
 695                 return NULL;
 696
 697         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 698                 latency = &cxsr_latency_table[i];
 699                 if (is_desktop == latency->is_desktop &&
 700                     is_ddr3 == latency->is_ddr3 &&
 701                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 702                         return latency;
 703         }
 704
 705         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 706
 707         return NULL;
 708 }
 709
 710 static void pineview_disable_cxsr(struct drm_device *dev)
 711 {
 712         struct drm_i915_private *dev_priv = dev->dev_private;
 713
 714         /* deactivate cxsr */
 715         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
 716 }
 717
 718 /*
 719  * Latency for FIFO fetches is dependent on several factors:
 720  *   - memory configuration (speed, channels)
 721  *   - chipset
 722  *   - current MCH state
 723  * It can be fairly high in some situations, so here we assume a fairly
 724  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 725  * set this value too high, the FIFO will fetch frequently to stay full)
 726  * and power consumption (set it too low to save power and we might see
 727  * FIFO underruns and display "flicker").
 728  *
 729  * A value of 5us seems to be a good balance; safe for very low end
 730  * platforms but not overly aggressive on lower latency configs.
 731  */
 732 static const int latency_ns = 5000;
 733
 734 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 735 {
 736         struct drm_i915_private *dev_priv = dev->dev_private;
 737         uint32_t dsparb = I915_READ(DSPARB);
 738         int size;
 739
 740         size = dsparb & 0x7f;
 741         if (plane)
 742                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 743
 744         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 745                       plane ? "B" : "A", size);
 746
 747         return size;
 748 }
 749
 750 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
 751 {
 752         struct drm_i915_private *dev_priv = dev->dev_private;
 753         uint32_t dsparb = I915_READ(DSPARB);
 754         int size;
 755
 756         size = dsparb & 0x1ff;
 757         if (plane)
 758                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 759         size >>= 1; /* Convert to cachelines */
 760
 761         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 762                       plane ? "B" : "A", size);
 763
 764         return size;
 765 }
 766
 767 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 768 {
 769         struct drm_i915_private *dev_priv = dev->dev_private;
 770         uint32_t dsparb = I915_READ(DSPARB);
 771         int size;
 772
 773         size = dsparb & 0x7f;
 774         size >>= 2; /* Convert to cachelines */
 775
 776         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 777                       plane ? "B" : "A",
 778                       size);
 779
 780         return size;
 781 }
 782
 783 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 784 {
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         uint32_t dsparb = I915_READ(DSPARB);
 787         int size;
 788
 789         size = dsparb & 0x7f;
 790         size >>= 1; /* Convert to cachelines */
 791
 792         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 793                       plane ? "B" : "A", size);
 794
 795         return size;
 796 }
 797
 798 /* Pineview has different values for various configs */
 799 static const struct intel_watermark_params pineview_display_wm = {
 800         PINEVIEW_DISPLAY_FIFO,
 801         PINEVIEW_MAX_WM,
 802         PINEVIEW_DFT_WM,
 803         PINEVIEW_GUARD_WM,
 804         PINEVIEW_FIFO_LINE_SIZE
 805 };
 806 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 807         PINEVIEW_DISPLAY_FIFO,
 808         PINEVIEW_MAX_WM,
 809         PINEVIEW_DFT_HPLLOFF_WM,
 810         PINEVIEW_GUARD_WM,
 811         PINEVIEW_FIFO_LINE_SIZE
 812 };
 813 static const struct intel_watermark_params pineview_cursor_wm = {
 814         PINEVIEW_CURSOR_FIFO,
 815         PINEVIEW_CURSOR_MAX_WM,
 816         PINEVIEW_CURSOR_DFT_WM,
 817         PINEVIEW_CURSOR_GUARD_WM,
 818         PINEVIEW_FIFO_LINE_SIZE,
 819 };
 820 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 821         PINEVIEW_CURSOR_FIFO,
 822         PINEVIEW_CURSOR_MAX_WM,
 823         PINEVIEW_CURSOR_DFT_WM,
 824         PINEVIEW_CURSOR_GUARD_WM,
 825         PINEVIEW_FIFO_LINE_SIZE
 826 };
 827 static const struct intel_watermark_params g4x_wm_info = {
 828         G4X_FIFO_SIZE,
 829         G4X_MAX_WM,
 830         G4X_MAX_WM,
 831         2,
 832         G4X_FIFO_LINE_SIZE,
 833 };
 834 static const struct intel_watermark_params g4x_cursor_wm_info = {
 835         I965_CURSOR_FIFO,
 836         I965_CURSOR_MAX_WM,
 837         I965_CURSOR_DFT_WM,
 838         2,
 839         G4X_FIFO_LINE_SIZE,
 840 };
 841 static const struct intel_watermark_params valleyview_wm_info = {
 842         VALLEYVIEW_FIFO_SIZE,
 843         VALLEYVIEW_MAX_WM,
 844         VALLEYVIEW_MAX_WM,
 845         2,
 846         G4X_FIFO_LINE_SIZE,
 847 };
 848 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 849         I965_CURSOR_FIFO,
 850         VALLEYVIEW_CURSOR_MAX_WM,
 851         I965_CURSOR_DFT_WM,
 852         2,
 853         G4X_FIFO_LINE_SIZE,
 854 };
 855 static const struct intel_watermark_params i965_cursor_wm_info = {
 856         I965_CURSOR_FIFO,
 857         I965_CURSOR_MAX_WM,
 858         I965_CURSOR_DFT_WM,
 859         2,
 860         I915_FIFO_LINE_SIZE,
 861 };
 862 static const struct intel_watermark_params i945_wm_info = {
 863         I945_FIFO_SIZE,
 864         I915_MAX_WM,
 865         1,
 866         2,
 867         I915_FIFO_LINE_SIZE
 868 };
 869 static const struct intel_watermark_params i915_wm_info = {
 870         I915_FIFO_SIZE,
 871         I915_MAX_WM,
 872         1,
 873         2,
 874         I915_FIFO_LINE_SIZE
 875 };
 876 static const struct intel_watermark_params i855_wm_info = {
 877         I855GM_FIFO_SIZE,
 878         I915_MAX_WM,
 879         1,
 880         2,
 881         I830_FIFO_LINE_SIZE
 882 };
 883 static const struct intel_watermark_params i830_wm_info = {
 884         I830_FIFO_SIZE,
 885         I915_MAX_WM,
 886         1,
 887         2,
 888         I830_FIFO_LINE_SIZE
 889 };
 890
 891 static const struct intel_watermark_params ironlake_display_wm_info = {
 892         ILK_DISPLAY_FIFO,
 893         ILK_DISPLAY_MAXWM,
 894         ILK_DISPLAY_DFTWM,
 895         2,
 896         ILK_FIFO_LINE_SIZE
 897 };
 898 static const struct intel_watermark_params ironlake_cursor_wm_info = {
 899         ILK_CURSOR_FIFO,
 900         ILK_CURSOR_MAXWM,
 901         ILK_CURSOR_DFTWM,
 902         2,
 903         ILK_FIFO_LINE_SIZE
 904 };
 905 static const struct intel_watermark_params ironlake_display_srwm_info = {
 906         ILK_DISPLAY_SR_FIFO,
 907         ILK_DISPLAY_MAX_SRWM,
 908         ILK_DISPLAY_DFT_SRWM,
 909         2,
 910         ILK_FIFO_LINE_SIZE
 911 };
 912 static const struct intel_watermark_params ironlake_cursor_srwm_info = {
 913         ILK_CURSOR_SR_FIFO,
 914         ILK_CURSOR_MAX_SRWM,
 915         ILK_CURSOR_DFT_SRWM,
 916         2,
 917         ILK_FIFO_LINE_SIZE
 918 };
 919
 920 static const struct intel_watermark_params sandybridge_display_wm_info = {
 921         SNB_DISPLAY_FIFO,
 922         SNB_DISPLAY_MAXWM,
 923         SNB_DISPLAY_DFTWM,
 924         2,
 925         SNB_FIFO_LINE_SIZE
 926 };
 927 static const struct intel_watermark_params sandybridge_cursor_wm_info = {
 928         SNB_CURSOR_FIFO,
 929         SNB_CURSOR_MAXWM,
 930         SNB_CURSOR_DFTWM,
 931         2,
 932         SNB_FIFO_LINE_SIZE
 933 };
 934 static const struct intel_watermark_params sandybridge_display_srwm_info = {
 935         SNB_DISPLAY_SR_FIFO,
 936         SNB_DISPLAY_MAX_SRWM,
 937         SNB_DISPLAY_DFT_SRWM,
 938         2,
 939         SNB_FIFO_LINE_SIZE
 940 };
 941 static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
 942         SNB_CURSOR_SR_FIFO,
 943         SNB_CURSOR_MAX_SRWM,
 944         SNB_CURSOR_DFT_SRWM,
 945         2,
 946         SNB_FIFO_LINE_SIZE
 947 };
 948
 949
 950 /**
 951  * intel_calculate_wm - calculate watermark level
 952  * @clock_in_khz: pixel clock
 953  * @wm: chip FIFO params
 954  * @pixel_size: display pixel size
 955  * @latency_ns: memory latency for the platform
 956  *
 957  * Calculate the watermark level (the level at which the display plane will
 958  * start fetching from memory again).  Each chip has a different display
 959  * FIFO size and allocation, so the caller needs to figure that out and pass
 960  * in the correct intel_watermark_params structure.
 961  *
 962  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 963  * on the pixel size.  When it reaches the watermark level, it'll start
 964  * fetching FIFO line sized based chunks from memory until the FIFO fills
 965  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 966  * will occur, and a display engine hang could result.
 967  */
 968 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 969                                         const struct intel_watermark_params *wm,
 970                                         int fifo_size,
 971                                         int pixel_size,
 972                                         unsigned long latency_ns)
 973 {
 974         long entries_required, wm_size;
 975
 976         /*
 977          * Note: we need to make sure we don't overflow for various clock &
 978          * latency values.
 979          * clocks go from a few thousand to several hundred thousand.
 980          * latency is usually a few thousand
 981          */
 982         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 983                 1000;
 984         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 985
 986         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 987
 988         wm_size = fifo_size - (entries_required + wm->guard_size);
 989
 990         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 991
 992         /* Don't promote wm_size to unsigned... */
 993         if (wm_size > (long)wm->max_wm)
 994                 wm_size = wm->max_wm;
 995         if (wm_size <= 0)
 996                 wm_size = wm->default_wm;
 997         return wm_size;
 998 }
 999
1000 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1001 {
1002         struct drm_crtc *crtc, *enabled = NULL;
1003
1004         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1005                 if (intel_crtc_active(crtc)) {
1006                         if (enabled)
1007                                 return NULL;
1008                         enabled = crtc;
1009                 }
1010         }
1011
1012         return enabled;
1013 }
1014
1015 static void pineview_update_wm(struct drm_device *dev)
1016 {
1017         struct drm_i915_private *dev_priv = dev->dev_private;
1018         struct drm_crtc *crtc;
1019         const struct cxsr_latency *latency;
1020         u32 reg;
1021         unsigned long wm;
1022
1023         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1024                                          dev_priv->fsb_freq, dev_priv->mem_freq);
1025         if (!latency) {
1026                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1027                 pineview_disable_cxsr(dev);
1028                 return;
1029         }
1030
1031         crtc = single_enabled_crtc(dev);
1032         if (crtc) {
1033                 int clock = crtc->mode.clock;
1034                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1035
1036                 /* Display SR */
1037                 wm = intel_calculate_wm(clock, &pineview_display_wm,
1038                                         pineview_display_wm.fifo_size,
1039                                         pixel_size, latency->display_sr);
1040                 reg = I915_READ(DSPFW1);
1041                 reg &= ~DSPFW_SR_MASK;
1042                 reg |= wm << DSPFW_SR_SHIFT;
1043                 I915_WRITE(DSPFW1, reg);
1044                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1045
1046                 /* cursor SR */
1047                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1048                                         pineview_display_wm.fifo_size,
1049                                         pixel_size, latency->cursor_sr);
1050                 reg = I915_READ(DSPFW3);
1051                 reg &= ~DSPFW_CURSOR_SR_MASK;
1052                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1053                 I915_WRITE(DSPFW3, reg);
1054
1055                 /* Display HPLL off SR */
1056                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1057                                         pineview_display_hplloff_wm.fifo_size,
1058                                         pixel_size, latency->display_hpll_disable);
1059                 reg = I915_READ(DSPFW3);
1060                 reg &= ~DSPFW_HPLL_SR_MASK;
1061                 reg |= wm & DSPFW_HPLL_SR_MASK;
1062                 I915_WRITE(DSPFW3, reg);
1063
1064                 /* cursor HPLL off SR */
1065                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1066                                         pineview_display_hplloff_wm.fifo_size,
1067                                         pixel_size, latency->cursor_hpll_disable);
1068                 reg = I915_READ(DSPFW3);
1069                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1070                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1071                 I915_WRITE(DSPFW3, reg);
1072                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1073
1074                 /* activate cxsr */
1075                 I915_WRITE(DSPFW3,
1076                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1077                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1078         } else {
1079                 pineview_disable_cxsr(dev);
1080                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1081         }
1082 }
1083
1084 static bool g4x_compute_wm0(struct drm_device *dev,
1085                             int plane,
1086                             const struct intel_watermark_params *display,
1087                             int display_latency_ns,
1088                             const struct intel_watermark_params *cursor,
1089                             int cursor_latency_ns,
1090                             int *plane_wm,
1091                             int *cursor_wm)
1092 {
1093         struct drm_crtc *crtc;
1094         int htotal, hdisplay, clock, pixel_size;
1095         int line_time_us, line_count;
1096         int entries, tlb_miss;
1097
1098         crtc = intel_get_crtc_for_plane(dev, plane);
1099         if (!intel_crtc_active(crtc)) {
1100                 *cursor_wm = cursor->guard_size;
1101                 *plane_wm = display->guard_size;
1102                 return false;
1103         }
1104
1105         htotal = crtc->mode.htotal;
1106         hdisplay = crtc->mode.hdisplay;
1107         clock = crtc->mode.clock;
1108         pixel_size = crtc->fb->bits_per_pixel / 8;
1109
1110         /* Use the small buffer method to calculate plane watermark */
1111         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1112         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1113         if (tlb_miss > 0)
1114                 entries += tlb_miss;
1115         entries = DIV_ROUND_UP(entries, display->cacheline_size);
1116         *plane_wm = entries + display->guard_size;
1117         if (*plane_wm > (int)display->max_wm)
1118                 *plane_wm = display->max_wm;
1119
1120         /* Use the large buffer method to calculate cursor watermark */
1121         line_time_us = ((htotal * 1000) / clock);
1122         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1123         entries = line_count * 64 * pixel_size;
1124         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1125         if (tlb_miss > 0)
1126                 entries += tlb_miss;
1127         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1128         *cursor_wm = entries + cursor->guard_size;
1129         if (*cursor_wm > (int)cursor->max_wm)
1130                 *cursor_wm = (int)cursor->max_wm;
1131
1132         return true;
1133 }
1134
1135 /*
1136  * Check the wm result.
1137  *
1138  * If any calculated watermark values is larger than the maximum value that
1139  * can be programmed into the associated watermark register, that watermark
1140  * must be disabled.
1141  */
1142 static bool g4x_check_srwm(struct drm_device *dev,
1143                            int display_wm, int cursor_wm,
1144                            const struct intel_watermark_params *display,
1145                            const struct intel_watermark_params *cursor)
1146 {
1147         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1148                       display_wm, cursor_wm);
1149
1150         if (display_wm > display->max_wm) {
1151                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1152                               display_wm, display->max_wm);
1153                 return false;
1154         }
1155
1156         if (cursor_wm > cursor->max_wm) {
1157                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1158                               cursor_wm, cursor->max_wm);
1159                 return false;
1160         }
1161
1162         if (!(display_wm || cursor_wm)) {
1163                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1164                 return false;
1165         }
1166
1167         return true;
1168 }
1169
1170 static bool g4x_compute_srwm(struct drm_device *dev,
1171                              int plane,
1172                              int latency_ns,
1173                              const struct intel_watermark_params *display,
1174                              const struct intel_watermark_params *cursor,
1175                              int *display_wm, int *cursor_wm)
1176 {
1177         struct drm_crtc *crtc;
1178         int hdisplay, htotal, pixel_size, clock;
1179         unsigned long line_time_us;
1180         int line_count, line_size;
1181         int small, large;
1182         int entries;
1183
1184         if (!latency_ns) {
1185                 *display_wm = *cursor_wm = 0;
1186                 return false;
1187         }
1188
1189         crtc = intel_get_crtc_for_plane(dev, plane);
1190         hdisplay = crtc->mode.hdisplay;
1191         htotal = crtc->mode.htotal;
1192         clock = crtc->mode.clock;
1193         pixel_size = crtc->fb->bits_per_pixel / 8;
1194
1195         line_time_us = (htotal * 1000) / clock;
1196         line_count = (latency_ns / line_time_us + 1000) / 1000;
1197         line_size = hdisplay * pixel_size;
1198
1199         /* Use the minimum of the small and large buffer method for primary */
1200         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1201         large = line_count * line_size;
1202
1203         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1204         *display_wm = entries + display->guard_size;
1205
1206         /* calculate the self-refresh watermark for display cursor */
1207         entries = line_count * pixel_size * 64;
1208         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1209         *cursor_wm = entries + cursor->guard_size;
1210
1211         return g4x_check_srwm(dev,
1212                               *display_wm, *cursor_wm,
1213                               display, cursor);
1214 }
1215
1216 static bool vlv_compute_drain_latency(struct drm_device *dev,
1217                                      int plane,
1218                                      int *plane_prec_mult,
1219                                      int *plane_dl,
1220                                      int *cursor_prec_mult,
1221                                      int *cursor_dl)
1222 {
1223         struct drm_crtc *crtc;
1224         int clock, pixel_size;
1225         int entries;
1226
1227         crtc = intel_get_crtc_for_plane(dev, plane);
1228         if (!intel_crtc_active(crtc))
1229                 return false;
1230
1231         clock = crtc->mode.clock;       /* VESA DOT Clock */
1232         pixel_size = crtc->fb->bits_per_pixel / 8;      /* BPP */
1233
1234         entries = (clock / 1000) * pixel_size;
1235         *plane_prec_mult = (entries > 256) ?
1236                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1237         *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1238                                                      pixel_size);
1239
1240         entries = (clock / 1000) * 4;   /* BPP is always 4 for cursor */
1241         *cursor_prec_mult = (entries > 256) ?
1242                 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1243         *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1244
1245         return true;
1246 }
1247
1248 /*
1249  * Update drain latency registers of memory arbiter
1250  *
1251  * Valleyview SoC has a new memory arbiter and needs drain latency registers
1252  * to be programmed. Each plane has a drain latency multiplier and a drain
1253  * latency value.
1254  */
1255
1256 static void vlv_update_drain_latency(struct drm_device *dev)
1257 {
1258         struct drm_i915_private *dev_priv = dev->dev_private;
1259         int planea_prec, planea_dl, planeb_prec, planeb_dl;
1260         int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1261         int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1262                                                         either 16 or 32 */
1263
1264         /* For plane A, Cursor A */
1265         if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1266                                       &cursor_prec_mult, &cursora_dl)) {
1267                 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1268                         DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1269                 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1270                         DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1271
1272                 I915_WRITE(VLV_DDL1, cursora_prec |
1273                                 (cursora_dl << DDL_CURSORA_SHIFT) |
1274                                 planea_prec | planea_dl);
1275         }
1276
1277         /* For plane B, Cursor B */
1278         if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1279                                       &cursor_prec_mult, &cursorb_dl)) {
1280                 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1281                         DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1282                 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1283                         DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1284
1285                 I915_WRITE(VLV_DDL2, cursorb_prec |
1286                                 (cursorb_dl << DDL_CURSORB_SHIFT) |
1287                                 planeb_prec | planeb_dl);
1288         }
1289 }
1290
1291 #define single_plane_enabled(mask) is_power_of_2(mask)
1292
1293 static void valleyview_update_wm(struct drm_device *dev)
1294 {
1295         static const int sr_latency_ns = 12000;
1296         struct drm_i915_private *dev_priv = dev->dev_private;
1297         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1298         int plane_sr, cursor_sr;
1299         int ignore_plane_sr, ignore_cursor_sr;
1300         unsigned int enabled = 0;
1301
1302         vlv_update_drain_latency(dev);
1303
1304         if (g4x_compute_wm0(dev, 0,
1305                             &valleyview_wm_info, latency_ns,
1306                             &valleyview_cursor_wm_info, latency_ns,
1307                             &planea_wm, &cursora_wm))
1308                 enabled |= 1;
1309
1310         if (g4x_compute_wm0(dev, 1,
1311                             &valleyview_wm_info, latency_ns,
1312                             &valleyview_cursor_wm_info, latency_ns,
1313                             &planeb_wm, &cursorb_wm))
1314                 enabled |= 2;
1315
1316         if (single_plane_enabled(enabled) &&
1317             g4x_compute_srwm(dev, ffs(enabled) - 1,
1318                              sr_latency_ns,
1319                              &valleyview_wm_info,
1320                              &valleyview_cursor_wm_info,
1321                              &plane_sr, &ignore_cursor_sr) &&
1322             g4x_compute_srwm(dev, ffs(enabled) - 1,
1323                              2*sr_latency_ns,
1324                              &valleyview_wm_info,
1325                              &valleyview_cursor_wm_info,
1326                              &ignore_plane_sr, &cursor_sr)) {
1327                 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
1328         } else {
1329                 I915_WRITE(FW_BLC_SELF_VLV,
1330                            I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
1331                 plane_sr = cursor_sr = 0;
1332         }
1333
1334         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1335                       planea_wm, cursora_wm,
1336                       planeb_wm, cursorb_wm,
1337                       plane_sr, cursor_sr);
1338
1339         I915_WRITE(DSPFW1,
1340                    (plane_sr << DSPFW_SR_SHIFT) |
1341                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1342                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1343                    planea_wm);
1344         I915_WRITE(DSPFW2,
1345                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1346                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1347         I915_WRITE(DSPFW3,
1348                    (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1349                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1350 }
1351
1352 static void g4x_update_wm(struct drm_device *dev)
1353 {
1354         static const int sr_latency_ns = 12000;
1355         struct drm_i915_private *dev_priv = dev->dev_private;
1356         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1357         int plane_sr, cursor_sr;
1358         unsigned int enabled = 0;
1359
1360         if (g4x_compute_wm0(dev, 0,
1361                             &g4x_wm_info, latency_ns,
1362                             &g4x_cursor_wm_info, latency_ns,
1363                             &planea_wm, &cursora_wm))
1364                 enabled |= 1;
1365
1366         if (g4x_compute_wm0(dev, 1,
1367                             &g4x_wm_info, latency_ns,
1368                             &g4x_cursor_wm_info, latency_ns,
1369                             &planeb_wm, &cursorb_wm))
1370                 enabled |= 2;
1371
1372         if (single_plane_enabled(enabled) &&
1373             g4x_compute_srwm(dev, ffs(enabled) - 1,
1374                              sr_latency_ns,
1375                              &g4x_wm_info,
1376                              &g4x_cursor_wm_info,
1377                              &plane_sr, &cursor_sr)) {
1378                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1379         } else {
1380                 I915_WRITE(FW_BLC_SELF,
1381                            I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
1382                 plane_sr = cursor_sr = 0;
1383         }
1384
1385         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1386                       planea_wm, cursora_wm,
1387                       planeb_wm, cursorb_wm,
1388                       plane_sr, cursor_sr);
1389
1390         I915_WRITE(DSPFW1,
1391                    (plane_sr << DSPFW_SR_SHIFT) |
1392                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1393                    (planeb_wm << DSPFW_PLANEB_SHIFT) |
1394                    planea_wm);
1395         I915_WRITE(DSPFW2,
1396                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1397                    (cursora_wm << DSPFW_CURSORA_SHIFT));
1398         /* HPLL off in SR has some issues on G4x... disable it */
1399         I915_WRITE(DSPFW3,
1400                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1401                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1402 }
1403
1404 static void i965_update_wm(struct drm_device *dev)
1405 {
1406         struct drm_i915_private *dev_priv = dev->dev_private;
1407         struct drm_crtc *crtc;
1408         int srwm = 1;
1409         int cursor_sr = 16;
1410
1411         /* Calc sr entries for one plane configs */
1412         crtc = single_enabled_crtc(dev);
1413         if (crtc) {
1414                 /* self-refresh has much higher latency */
1415                 static const int sr_latency_ns = 12000;
1416                 int clock = crtc->mode.clock;
1417                 int htotal = crtc->mode.htotal;
1418                 int hdisplay = crtc->mode.hdisplay;
1419                 int pixel_size = crtc->fb->bits_per_pixel / 8;
1420                 unsigned long line_time_us;
1421                 int entries;
1422
1423                 line_time_us = ((htotal * 1000) / clock);
1424
1425                 /* Use ns/us then divide to preserve precision */
1426                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1427                         pixel_size * hdisplay;
1428                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1429                 srwm = I965_FIFO_SIZE - entries;
1430                 if (srwm < 0)
1431                         srwm = 1;
1432                 srwm &= 0x1ff;
1433                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1434                               entries, srwm);
1435
1436                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1437                         pixel_size * 64;
1438                 entries = DIV_ROUND_UP(entries,
1439                                           i965_cursor_wm_info.cacheline_size);
1440                 cursor_sr = i965_cursor_wm_info.fifo_size -
1441                         (entries + i965_cursor_wm_info.guard_size);
1442
1443                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1444                         cursor_sr = i965_cursor_wm_info.max_wm;
1445
1446                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1447                               "cursor %d\n", srwm, cursor_sr);
1448
1449                 if (IS_CRESTLINE(dev))
1450                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1451         } else {
1452                 /* Turn off self refresh if both pipes are enabled */
1453                 if (IS_CRESTLINE(dev))
1454                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1455                                    & ~FW_BLC_SELF_EN);
1456         }
1457
1458         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1459                       srwm);
1460
1461         /* 965 has limitations... */
1462         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1463                    (8 << 16) | (8 << 8) | (8 << 0));
1464         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1465         /* update cursor SR watermark */
1466         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1467 }
1468
1469 static void i9xx_update_wm(struct drm_device *dev)
1470 {
1471         struct drm_i915_private *dev_priv = dev->dev_private;
1472         const struct intel_watermark_params *wm_info;
1473         uint32_t fwater_lo;
1474         uint32_t fwater_hi;
1475         int cwm, srwm = 1;
1476         int fifo_size;
1477         int planea_wm, planeb_wm;
1478         struct drm_crtc *crtc, *enabled = NULL;
1479
1480         if (IS_I945GM(dev))
1481                 wm_info = &i945_wm_info;
1482         else if (!IS_GEN2(dev))
1483                 wm_info = &i915_wm_info;
1484         else
1485                 wm_info = &i855_wm_info;
1486
1487         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1488         crtc = intel_get_crtc_for_plane(dev, 0);
1489         if (intel_crtc_active(crtc)) {
1490                 int cpp = crtc->fb->bits_per_pixel / 8;
1491                 if (IS_GEN2(dev))
1492                         cpp = 4;
1493
1494                 planea_wm = intel_calculate_wm(crtc->mode.clock,
1495                                                wm_info, fifo_size, cpp,
1496                                                latency_ns);
1497                 enabled = crtc;
1498         } else
1499                 planea_wm = fifo_size - wm_info->guard_size;
1500
1501         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1502         crtc = intel_get_crtc_for_plane(dev, 1);
1503         if (intel_crtc_active(crtc)) {
1504                 int cpp = crtc->fb->bits_per_pixel / 8;
1505                 if (IS_GEN2(dev))
1506                         cpp = 4;
1507
1508                 planeb_wm = intel_calculate_wm(crtc->mode.clock,
1509                                                wm_info, fifo_size, cpp,
1510                                                latency_ns);
1511                 if (enabled == NULL)
1512                         enabled = crtc;
1513                 else
1514                         enabled = NULL;
1515         } else
1516                 planeb_wm = fifo_size - wm_info->guard_size;
1517
1518         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1519
1520         /*
1521          * Overlay gets an aggressive default since video jitter is bad.
1522          */
1523         cwm = 2;
1524
1525         /* Play safe and disable self-refresh before adjusting watermarks. */
1526         if (IS_I945G(dev) || IS_I945GM(dev))
1527                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1528         else if (IS_I915GM(dev))
1529                 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1530
1531         /* Calc sr entries for one plane configs */
1532         if (HAS_FW_BLC(dev) && enabled) {
1533                 /* self-refresh has much higher latency */
1534                 static const int sr_latency_ns = 6000;
1535                 int clock = enabled->mode.clock;
1536                 int htotal = enabled->mode.htotal;
1537                 int hdisplay = enabled->mode.hdisplay;
1538                 int pixel_size = enabled->fb->bits_per_pixel / 8;
1539                 unsigned long line_time_us;
1540                 int entries;
1541
1542                 line_time_us = (htotal * 1000) / clock;
1543
1544                 /* Use ns/us then divide to preserve precision */
1545                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1546                         pixel_size * hdisplay;
1547                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1548                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1549                 srwm = wm_info->fifo_size - entries;
1550                 if (srwm < 0)
1551                         srwm = 1;
1552
1553                 if (IS_I945G(dev) || IS_I945GM(dev))
1554                         I915_WRITE(FW_BLC_SELF,
1555                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1556                 else if (IS_I915GM(dev))
1557                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1558         }
1559
1560         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1561                       planea_wm, planeb_wm, cwm, srwm);
1562
1563         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1564         fwater_hi = (cwm & 0x1f);
1565
1566         /* Set request length to 8 cachelines per fetch */
1567         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1568         fwater_hi = fwater_hi | (1 << 8);
1569
1570         I915_WRITE(FW_BLC, fwater_lo);
1571         I915_WRITE(FW_BLC2, fwater_hi);
1572
1573         if (HAS_FW_BLC(dev)) {
1574                 if (enabled) {
1575                         if (IS_I945G(dev) || IS_I945GM(dev))
1576                                 I915_WRITE(FW_BLC_SELF,
1577                                            FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1578                         else if (IS_I915GM(dev))
1579                                 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1580                         DRM_DEBUG_KMS("memory self refresh enabled\n");
1581                 } else
1582                         DRM_DEBUG_KMS("memory self refresh disabled\n");
1583         }
1584 }
1585
1586 static void i830_update_wm(struct drm_device *dev)
1587 {
1588         struct drm_i915_private *dev_priv = dev->dev_private;
1589         struct drm_crtc *crtc;
1590         uint32_t fwater_lo;
1591         int planea_wm;
1592
1593         crtc = single_enabled_crtc(dev);
1594         if (crtc == NULL)
1595                 return;
1596
1597         planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1598                                        dev_priv->display.get_fifo_size(dev, 0),
1599                                        4, latency_ns);
1600         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1601         fwater_lo |= (3<<8) | planea_wm;
1602
1603         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1604
1605         I915_WRITE(FW_BLC, fwater_lo);
1606 }
1607
1608 #define ILK_LP0_PLANE_LATENCY           700
1609 #define ILK_LP0_CURSOR_LATENCY          1300
1610
1611 /*
1612  * Check the wm result.
1613  *
1614  * If any calculated watermark values is larger than the maximum value that
1615  * can be programmed into the associated watermark register, that watermark
1616  * must be disabled.
1617  */
1618 static bool ironlake_check_srwm(struct drm_device *dev, int level,
1619                                 int fbc_wm, int display_wm, int cursor_wm,
1620                                 const struct intel_watermark_params *display,
1621                                 const struct intel_watermark_params *cursor)
1622 {
1623         struct drm_i915_private *dev_priv = dev->dev_private;
1624
1625         DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1626                       " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1627
1628         if (fbc_wm > SNB_FBC_MAX_SRWM) {
1629                 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1630                               fbc_wm, SNB_FBC_MAX_SRWM, level);
1631
1632                 /* fbc has it's own way to disable FBC WM */
1633                 I915_WRITE(DISP_ARB_CTL,
1634                            I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1635                 return false;
1636         }
1637
1638         if (display_wm > display->max_wm) {
1639                 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1640                               display_wm, SNB_DISPLAY_MAX_SRWM, level);
1641                 return false;
1642         }
1643
1644         if (cursor_wm > cursor->max_wm) {
1645                 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1646                               cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1647                 return false;
1648         }
1649
1650         if (!(fbc_wm || display_wm || cursor_wm)) {
1651                 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1652                 return false;
1653         }
1654
1655         return true;
1656 }
1657
1658 /*
1659  * Compute watermark values of WM[1-3],
1660  */
1661 static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1662                                   int latency_ns,
1663                                   const struct intel_watermark_params *display,
1664                                   const struct intel_watermark_params *cursor,
1665                                   int *fbc_wm, int *display_wm, int *cursor_wm)
1666 {
1667         struct drm_crtc *crtc;
1668         unsigned long line_time_us;
1669         int hdisplay, htotal, pixel_size, clock;
1670         int line_count, line_size;
1671         int small, large;
1672         int entries;
1673
1674         if (!latency_ns) {
1675                 *fbc_wm = *display_wm = *cursor_wm = 0;
1676                 return false;
1677         }
1678
1679         crtc = intel_get_crtc_for_plane(dev, plane);
1680         hdisplay = crtc->mode.hdisplay;
1681         htotal = crtc->mode.htotal;
1682         clock = crtc->mode.clock;
1683         pixel_size = crtc->fb->bits_per_pixel / 8;
1684
1685         line_time_us = (htotal * 1000) / clock;
1686         line_count = (latency_ns / line_time_us + 1000) / 1000;
1687         line_size = hdisplay * pixel_size;
1688
1689         /* Use the minimum of the small and large buffer method for primary */
1690         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1691         large = line_count * line_size;
1692
1693         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1694         *display_wm = entries + display->guard_size;
1695
1696         /*
1697          * Spec says:
1698          * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1699          */
1700         *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1701
1702         /* calculate the self-refresh watermark for display cursor */
1703         entries = line_count * pixel_size * 64;
1704         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1705         *cursor_wm = entries + cursor->guard_size;
1706
1707         return ironlake_check_srwm(dev, level,
1708                                    *fbc_wm, *display_wm, *cursor_wm,
1709                                    display, cursor);
1710 }
1711
1712 static void ironlake_update_wm(struct drm_device *dev)
1713 {
1714         struct drm_i915_private *dev_priv = dev->dev_private;
1715         int fbc_wm, plane_wm, cursor_wm;
1716         unsigned int enabled;
1717
1718         enabled = 0;
1719         if (g4x_compute_wm0(dev, 0,
1720                             &ironlake_display_wm_info,
1721                             ILK_LP0_PLANE_LATENCY,
1722                             &ironlake_cursor_wm_info,
1723                             ILK_LP0_CURSOR_LATENCY,
1724                             &plane_wm, &cursor_wm)) {
1725                 I915_WRITE(WM0_PIPEA_ILK,
1726                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1727                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1728                               " plane %d, " "cursor: %d\n",
1729                               plane_wm, cursor_wm);
1730                 enabled |= 1;
1731         }
1732
1733         if (g4x_compute_wm0(dev, 1,
1734                             &ironlake_display_wm_info,
1735                             ILK_LP0_PLANE_LATENCY,
1736                             &ironlake_cursor_wm_info,
1737                             ILK_LP0_CURSOR_LATENCY,
1738                             &plane_wm, &cursor_wm)) {
1739                 I915_WRITE(WM0_PIPEB_ILK,
1740                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1741                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1742                               " plane %d, cursor: %d\n",
1743                               plane_wm, cursor_wm);
1744                 enabled |= 2;
1745         }
1746
1747         /*
1748          * Calculate and update the self-refresh watermark only when one
1749          * display plane is used.
1750          */
1751         I915_WRITE(WM3_LP_ILK, 0);
1752         I915_WRITE(WM2_LP_ILK, 0);
1753         I915_WRITE(WM1_LP_ILK, 0);
1754
1755         if (!single_plane_enabled(enabled))
1756                 return;
1757         enabled = ffs(enabled) - 1;
1758
1759         /* WM1 */
1760         if (!ironlake_compute_srwm(dev, 1, enabled,
1761                                    ILK_READ_WM1_LATENCY() * 500,
1762                                    &ironlake_display_srwm_info,
1763                                    &ironlake_cursor_srwm_info,
1764                                    &fbc_wm, &plane_wm, &cursor_wm))
1765                 return;
1766
1767         I915_WRITE(WM1_LP_ILK,
1768                    WM1_LP_SR_EN |
1769                    (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1770                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1771                    (plane_wm << WM1_LP_SR_SHIFT) |
1772                    cursor_wm);
1773
1774         /* WM2 */
1775         if (!ironlake_compute_srwm(dev, 2, enabled,
1776                                    ILK_READ_WM2_LATENCY() * 500,
1777                                    &ironlake_display_srwm_info,
1778                                    &ironlake_cursor_srwm_info,
1779                                    &fbc_wm, &plane_wm, &cursor_wm))
1780                 return;
1781
1782         I915_WRITE(WM2_LP_ILK,
1783                    WM2_LP_EN |
1784                    (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1785                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1786                    (plane_wm << WM1_LP_SR_SHIFT) |
1787                    cursor_wm);
1788
1789         /*
1790          * WM3 is unsupported on ILK, probably because we don't have latency
1791          * data for that power state
1792          */
1793 }
1794
1795 static void sandybridge_update_wm(struct drm_device *dev)
1796 {
1797         struct drm_i915_private *dev_priv = dev->dev_private;
1798         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1799         u32 val;
1800         int fbc_wm, plane_wm, cursor_wm;
1801         unsigned int enabled;
1802
1803         enabled = 0;
1804         if (g4x_compute_wm0(dev, 0,
1805                             &sandybridge_display_wm_info, latency,
1806                             &sandybridge_cursor_wm_info, latency,
1807                             &plane_wm, &cursor_wm)) {
1808                 val = I915_READ(WM0_PIPEA_ILK);
1809                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1810                 I915_WRITE(WM0_PIPEA_ILK, val |
1811                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1812                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1813                               " plane %d, " "cursor: %d\n",
1814                               plane_wm, cursor_wm);
1815                 enabled |= 1;
1816         }
1817
1818         if (g4x_compute_wm0(dev, 1,
1819                             &sandybridge_display_wm_info, latency,
1820                             &sandybridge_cursor_wm_info, latency,
1821                             &plane_wm, &cursor_wm)) {
1822                 val = I915_READ(WM0_PIPEB_ILK);
1823                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1824                 I915_WRITE(WM0_PIPEB_ILK, val |
1825                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1826                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1827                               " plane %d, cursor: %d\n",
1828                               plane_wm, cursor_wm);
1829                 enabled |= 2;
1830         }
1831
1832         /*
1833          * Calculate and update the self-refresh watermark only when one
1834          * display plane is used.
1835          *
1836          * SNB support 3 levels of watermark.
1837          *
1838          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1839          * and disabled in the descending order
1840          *
1841          */
1842         I915_WRITE(WM3_LP_ILK, 0);
1843         I915_WRITE(WM2_LP_ILK, 0);
1844         I915_WRITE(WM1_LP_ILK, 0);
1845
1846         if (!single_plane_enabled(enabled) ||
1847             dev_priv->sprite_scaling_enabled)
1848                 return;
1849         enabled = ffs(enabled) - 1;
1850
1851         /* WM1 */
1852         if (!ironlake_compute_srwm(dev, 1, enabled,
1853                                    SNB_READ_WM1_LATENCY() * 500,
1854                                    &sandybridge_display_srwm_info,
1855                                    &sandybridge_cursor_srwm_info,
1856                                    &fbc_wm, &plane_wm, &cursor_wm))
1857                 return;
1858
1859         I915_WRITE(WM1_LP_ILK,
1860                    WM1_LP_SR_EN |
1861                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1862                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1863                    (plane_wm << WM1_LP_SR_SHIFT) |
1864                    cursor_wm);
1865
1866         /* WM2 */
1867         if (!ironlake_compute_srwm(dev, 2, enabled,
1868                                    SNB_READ_WM2_LATENCY() * 500,
1869                                    &sandybridge_display_srwm_info,
1870                                    &sandybridge_cursor_srwm_info,
1871                                    &fbc_wm, &plane_wm, &cursor_wm))
1872                 return;
1873
1874         I915_WRITE(WM2_LP_ILK,
1875                    WM2_LP_EN |
1876                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1877                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1878                    (plane_wm << WM1_LP_SR_SHIFT) |
1879                    cursor_wm);
1880
1881         /* WM3 */
1882         if (!ironlake_compute_srwm(dev, 3, enabled,
1883                                    SNB_READ_WM3_LATENCY() * 500,
1884                                    &sandybridge_display_srwm_info,
1885                                    &sandybridge_cursor_srwm_info,
1886                                    &fbc_wm, &plane_wm, &cursor_wm))
1887                 return;
1888
1889         I915_WRITE(WM3_LP_ILK,
1890                    WM3_LP_EN |
1891                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1892                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1893                    (plane_wm << WM1_LP_SR_SHIFT) |
1894                    cursor_wm);
1895 }
1896
1897 static void ivybridge_update_wm(struct drm_device *dev)
1898 {
1899         struct drm_i915_private *dev_priv = dev->dev_private;
1900         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
1901         u32 val;
1902         int fbc_wm, plane_wm, cursor_wm;
1903         int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1904         unsigned int enabled;
1905
1906         enabled = 0;
1907         if (g4x_compute_wm0(dev, 0,
1908                             &sandybridge_display_wm_info, latency,
1909                             &sandybridge_cursor_wm_info, latency,
1910                             &plane_wm, &cursor_wm)) {
1911                 val = I915_READ(WM0_PIPEA_ILK);
1912                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1913                 I915_WRITE(WM0_PIPEA_ILK, val |
1914                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1915                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1916                               " plane %d, " "cursor: %d\n",
1917                               plane_wm, cursor_wm);
1918                 enabled |= 1;
1919         }
1920
1921         if (g4x_compute_wm0(dev, 1,
1922                             &sandybridge_display_wm_info, latency,
1923                             &sandybridge_cursor_wm_info, latency,
1924                             &plane_wm, &cursor_wm)) {
1925                 val = I915_READ(WM0_PIPEB_ILK);
1926                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1927                 I915_WRITE(WM0_PIPEB_ILK, val |
1928                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1929                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1930                               " plane %d, cursor: %d\n",
1931                               plane_wm, cursor_wm);
1932                 enabled |= 2;
1933         }
1934
1935         if (g4x_compute_wm0(dev, 2,
1936                             &sandybridge_display_wm_info, latency,
1937                             &sandybridge_cursor_wm_info, latency,
1938                             &plane_wm, &cursor_wm)) {
1939                 val = I915_READ(WM0_PIPEC_IVB);
1940                 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1941                 I915_WRITE(WM0_PIPEC_IVB, val |
1942                            ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1943                 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1944                               " plane %d, cursor: %d\n",
1945                               plane_wm, cursor_wm);
1946                 enabled |= 3;
1947         }
1948
1949         /*
1950          * Calculate and update the self-refresh watermark only when one
1951          * display plane is used.
1952          *
1953          * SNB support 3 levels of watermark.
1954          *
1955          * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1956          * and disabled in the descending order
1957          *
1958          */
1959         I915_WRITE(WM3_LP_ILK, 0);
1960         I915_WRITE(WM2_LP_ILK, 0);
1961         I915_WRITE(WM1_LP_ILK, 0);
1962
1963         if (!single_plane_enabled(enabled) ||
1964             dev_priv->sprite_scaling_enabled)
1965                 return;
1966         enabled = ffs(enabled) - 1;
1967
1968         /* WM1 */
1969         if (!ironlake_compute_srwm(dev, 1, enabled,
1970                                    SNB_READ_WM1_LATENCY() * 500,
1971                                    &sandybridge_display_srwm_info,
1972                                    &sandybridge_cursor_srwm_info,
1973                                    &fbc_wm, &plane_wm, &cursor_wm))
1974                 return;
1975
1976         I915_WRITE(WM1_LP_ILK,
1977                    WM1_LP_SR_EN |
1978                    (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1979                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1980                    (plane_wm << WM1_LP_SR_SHIFT) |
1981                    cursor_wm);
1982
1983         /* WM2 */
1984         if (!ironlake_compute_srwm(dev, 2, enabled,
1985                                    SNB_READ_WM2_LATENCY() * 500,
1986                                    &sandybridge_display_srwm_info,
1987                                    &sandybridge_cursor_srwm_info,
1988                                    &fbc_wm, &plane_wm, &cursor_wm))
1989                 return;
1990
1991         I915_WRITE(WM2_LP_ILK,
1992                    WM2_LP_EN |
1993                    (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1994                    (fbc_wm << WM1_LP_FBC_SHIFT) |
1995                    (plane_wm << WM1_LP_SR_SHIFT) |
1996                    cursor_wm);
1997
1998         /* WM3, note we have to correct the cursor latency */
1999         if (!ironlake_compute_srwm(dev, 3, enabled,
2000                                    SNB_READ_WM3_LATENCY() * 500,
2001                                    &sandybridge_display_srwm_info,
2002                                    &sandybridge_cursor_srwm_info,
2003                                    &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2004             !ironlake_compute_srwm(dev, 3, enabled,
2005                                    2 * SNB_READ_WM3_LATENCY() * 500,
2006                                    &sandybridge_display_srwm_info,
2007                                    &sandybridge_cursor_srwm_info,
2008                                    &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
2009                 return;
2010
2011         I915_WRITE(WM3_LP_ILK,
2012                    WM3_LP_EN |
2013                    (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2014                    (fbc_wm << WM1_LP_FBC_SHIFT) |
2015                    (plane_wm << WM1_LP_SR_SHIFT) |
2016                    cursor_wm);
2017 }
2018
2019 static void
2020 haswell_update_linetime_wm(struct drm_device *dev, int pipe,
2021                                  struct drm_display_mode *mode)
2022 {
2023         struct drm_i915_private *dev_priv = dev->dev_private;
2024         u32 temp;
2025
2026         temp = I915_READ(PIPE_WM_LINETIME(pipe));
2027         temp &= ~PIPE_WM_LINETIME_MASK;
2028
2029         /* The WM are computed with base on how long it takes to fill a single
2030          * row at the given clock rate, multiplied by 8.
2031          * */
2032         temp |= PIPE_WM_LINETIME_TIME(
2033                 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
2034
2035         /* IPS watermarks are only used by pipe A, and are ignored by
2036          * pipes B and C.  They are calculated similarly to the common
2037          * linetime values, except that we are using CD clock frequency
2038          * in MHz instead of pixel rate for the division.
2039          *
2040          * This is a placeholder for the IPS watermark calculation code.
2041          */
2042
2043         I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
2044 }
2045
2046 static bool
2047 sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2048                               uint32_t sprite_width, int pixel_size,
2049                               const struct intel_watermark_params *display,
2050                               int display_latency_ns, int *sprite_wm)
2051 {
2052         struct drm_crtc *crtc;
2053         int clock;
2054         int entries, tlb_miss;
2055
2056         crtc = intel_get_crtc_for_plane(dev, plane);
2057         if (!intel_crtc_active(crtc)) {
2058                 *sprite_wm = display->guard_size;
2059                 return false;
2060         }
2061
2062         clock = crtc->mode.clock;
2063
2064         /* Use the small buffer method to calculate the sprite watermark */
2065         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2066         tlb_miss = display->fifo_size*display->cacheline_size -
2067                 sprite_width * 8;
2068         if (tlb_miss > 0)
2069                 entries += tlb_miss;
2070         entries = DIV_ROUND_UP(entries, display->cacheline_size);
2071         *sprite_wm = entries + display->guard_size;
2072         if (*sprite_wm > (int)display->max_wm)
2073                 *sprite_wm = display->max_wm;
2074
2075         return true;
2076 }
2077
2078 static bool
2079 sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2080                                 uint32_t sprite_width, int pixel_size,
2081                                 const struct intel_watermark_params *display,
2082                                 int latency_ns, int *sprite_wm)
2083 {
2084         struct drm_crtc *crtc;
2085         unsigned long line_time_us;
2086         int clock;
2087         int line_count, line_size;
2088         int small, large;
2089         int entries;
2090
2091         if (!latency_ns) {
2092                 *sprite_wm = 0;
2093                 return false;
2094         }
2095
2096         crtc = intel_get_crtc_for_plane(dev, plane);
2097         clock = crtc->mode.clock;
2098         if (!clock) {
2099                 *sprite_wm = 0;
2100                 return false;
2101         }
2102
2103         line_time_us = (sprite_width * 1000) / clock;
2104         if (!line_time_us) {
2105                 *sprite_wm = 0;
2106                 return false;
2107         }
2108
2109         line_count = (latency_ns / line_time_us + 1000) / 1000;
2110         line_size = sprite_width * pixel_size;
2111
2112         /* Use the minimum of the small and large buffer method for primary */
2113         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2114         large = line_count * line_size;
2115
2116         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2117         *sprite_wm = entries + display->guard_size;
2118
2119         return *sprite_wm > 0x3ff ? false : true;
2120 }
2121
2122 static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
2123                                          uint32_t sprite_width, int pixel_size)
2124 {
2125         struct drm_i915_private *dev_priv = dev->dev_private;
2126         int latency = SNB_READ_WM0_LATENCY() * 100;     /* In unit 0.1us */
2127         u32 val;
2128         int sprite_wm, reg;
2129         int ret;
2130
2131         switch (pipe) {
2132         case 0:
2133                 reg = WM0_PIPEA_ILK;
2134                 break;
2135         case 1:
2136                 reg = WM0_PIPEB_ILK;
2137                 break;
2138         case 2:
2139                 reg = WM0_PIPEC_IVB;
2140                 break;
2141         default:
2142                 return; /* bad pipe */
2143         }
2144
2145         ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2146                                             &sandybridge_display_wm_info,
2147                                             latency, &sprite_wm);
2148         if (!ret) {
2149                 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2150                               pipe_name(pipe));
2151                 return;
2152         }
2153
2154         val = I915_READ(reg);
2155         val &= ~WM0_PIPE_SPRITE_MASK;
2156         I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2157         DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
2158
2159
2160         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2161                                               pixel_size,
2162                                               &sandybridge_display_srwm_info,
2163                                               SNB_READ_WM1_LATENCY() * 500,
2164                                               &sprite_wm);
2165         if (!ret) {
2166                 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2167                               pipe_name(pipe));
2168                 return;
2169         }
2170         I915_WRITE(WM1S_LP_ILK, sprite_wm);
2171
2172         /* Only IVB has two more LP watermarks for sprite */
2173         if (!IS_IVYBRIDGE(dev))
2174                 return;
2175
2176         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2177                                               pixel_size,
2178                                               &sandybridge_display_srwm_info,
2179                                               SNB_READ_WM2_LATENCY() * 500,
2180                                               &sprite_wm);
2181         if (!ret) {
2182                 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2183                               pipe_name(pipe));
2184                 return;
2185         }
2186         I915_WRITE(WM2S_LP_IVB, sprite_wm);
2187
2188         ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2189                                               pixel_size,
2190                                               &sandybridge_display_srwm_info,
2191                                               SNB_READ_WM3_LATENCY() * 500,
2192                                               &sprite_wm);
2193         if (!ret) {
2194                 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2195                               pipe_name(pipe));
2196                 return;
2197         }
2198         I915_WRITE(WM3S_LP_IVB, sprite_wm);
2199 }
2200
2201 /**
2202  * intel_update_watermarks - update FIFO watermark values based on current modes
2203  *
2204  * Calculate watermark values for the various WM regs based on current mode
2205  * and plane configuration.
2206  *
2207  * There are several cases to deal with here:
2208  *   - normal (i.e. non-self-refresh)
2209  *   - self-refresh (SR) mode
2210  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2211  *   - lines are small relative to FIFO size (buffer can hold more than 2
2212  *     lines), so need to account for TLB latency
2213  *
2214  *   The normal calculation is:
2215  *     watermark = dotclock * bytes per pixel * latency
2216  *   where latency is platform & configuration dependent (we assume pessimal
2217  *   values here).
2218  *
2219  *   The SR calculation is:
2220  *     watermark = (trunc(latency/line time)+1) * surface width *
2221  *       bytes per pixel
2222  *   where
2223  *     line time = htotal / dotclock
2224  *     surface width = hdisplay for normal plane and 64 for cursor
2225  *   and latency is assumed to be high, as above.
2226  *
2227  * The final value programmed to the register should always be rounded up,
2228  * and include an extra 2 entries to account for clock crossings.
2229  *
2230  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2231  * to set the non-SR watermarks to 8.
2232  */
2233 void intel_update_watermarks(struct drm_device *dev)
2234 {
2235         struct drm_i915_private *dev_priv = dev->dev_private;
2236
2237         if (dev_priv->display.update_wm)
2238                 dev_priv->display.update_wm(dev);
2239 }
2240
2241 void intel_update_linetime_watermarks(struct drm_device *dev,
2242                 int pipe, struct drm_display_mode *mode)
2243 {
2244         struct drm_i915_private *dev_priv = dev->dev_private;
2245
2246         if (dev_priv->display.update_linetime_wm)
2247                 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2248 }
2249
2250 void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2251                                     uint32_t sprite_width, int pixel_size)
2252 {
2253         struct drm_i915_private *dev_priv = dev->dev_private;
2254
2255         if (dev_priv->display.update_sprite_wm)
2256                 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2257                                                    pixel_size);
2258 }
2259
2260 static struct drm_i915_gem_object *
2261 intel_alloc_context_page(struct drm_device *dev)
2262 {
2263         struct drm_i915_gem_object *ctx;
2264         int ret;
2265
2266         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2267
2268         ctx = i915_gem_alloc_object(dev, 4096);
2269         if (!ctx) {
2270                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2271                 return NULL;
2272         }
2273
2274         ret = i915_gem_object_pin(ctx, 4096, true, false);
2275         if (ret) {
2276                 DRM_ERROR("failed to pin power context: %d\n", ret);
2277                 goto err_unref;
2278         }
2279
2280         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2281         if (ret) {
2282                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2283                 goto err_unpin;
2284         }
2285
2286         return ctx;
2287
2288 err_unpin:
2289         i915_gem_object_unpin(ctx);
2290 err_unref:
2291         drm_gem_object_unreference(&ctx->base);
2292         return NULL;
2293 }
2294
2295 /**
2296  * Lock protecting IPS related data structures
2297  */
2298 DEFINE_SPINLOCK(mchdev_lock);
2299
2300 /* Global for IPS driver to get at the current i915 device. Protected by
2301  * mchdev_lock. */
2302 static struct drm_i915_private *i915_mch_dev;
2303
2304 bool ironlake_set_drps(struct drm_device *dev, u8 val)
2305 {
2306         struct drm_i915_private *dev_priv = dev->dev_private;
2307         u16 rgvswctl;
2308
2309         assert_spin_locked(&mchdev_lock);
2310
2311         rgvswctl = I915_READ16(MEMSWCTL);
2312         if (rgvswctl & MEMCTL_CMD_STS) {
2313                 DRM_DEBUG("gpu busy, RCS change rejected\n");
2314                 return false; /* still busy with another command */
2315         }
2316
2317         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2318                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2319         I915_WRITE16(MEMSWCTL, rgvswctl);
2320         POSTING_READ16(MEMSWCTL);
2321
2322         rgvswctl |= MEMCTL_CMD_STS;
2323         I915_WRITE16(MEMSWCTL, rgvswctl);
2324
2325         return true;
2326 }
2327
2328 static void ironlake_enable_drps(struct drm_device *dev)
2329 {
2330         struct drm_i915_private *dev_priv = dev->dev_private;
2331         u32 rgvmodectl = I915_READ(MEMMODECTL);
2332         u8 fmax, fmin, fstart, vstart;
2333
2334         spin_lock_irq(&mchdev_lock);
2335
2336         /* Enable temp reporting */
2337         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2338         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2339
2340         /* 100ms RC evaluation intervals */
2341         I915_WRITE(RCUPEI, 100000);
2342         I915_WRITE(RCDNEI, 100000);
2343
2344         /* Set max/min thresholds to 90ms and 80ms respectively */
2345         I915_WRITE(RCBMAXAVG, 90000);
2346         I915_WRITE(RCBMINAVG, 80000);
2347
2348         I915_WRITE(MEMIHYST, 1);
2349
2350         /* Set up min, max, and cur for interrupt handling */
2351         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2352         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2353         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2354                 MEMMODE_FSTART_SHIFT;
2355
2356         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2357                 PXVFREQ_PX_SHIFT;
2358
2359         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2360         dev_priv->ips.fstart = fstart;
2361
2362         dev_priv->ips.max_delay = fstart;
2363         dev_priv->ips.min_delay = fmin;
2364         dev_priv->ips.cur_delay = fstart;
2365
2366         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2367                          fmax, fmin, fstart);
2368
2369         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2370
2371         /*
2372          * Interrupts will be enabled in ironlake_irq_postinstall
2373          */
2374
2375         I915_WRITE(VIDSTART, vstart);
2376         POSTING_READ(VIDSTART);
2377
2378         rgvmodectl |= MEMMODE_SWMODE_EN;
2379         I915_WRITE(MEMMODECTL, rgvmodectl);
2380
2381         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2382                 DRM_ERROR("stuck trying to change perf mode\n");
2383         mdelay(1);
2384
2385         ironlake_set_drps(dev, fstart);
2386
2387         dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2388                 I915_READ(0x112e0);
2389         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2390         dev_priv->ips.last_count2 = I915_READ(0x112f4);
2391         getrawmonotonic(&dev_priv->ips.last_time2);
2392
2393         spin_unlock_irq(&mchdev_lock);
2394 }
2395
2396 static void ironlake_disable_drps(struct drm_device *dev)
2397 {
2398         struct drm_i915_private *dev_priv = dev->dev_private;
2399         u16 rgvswctl;
2400
2401         spin_lock_irq(&mchdev_lock);
2402
2403         rgvswctl = I915_READ16(MEMSWCTL);
2404
2405         /* Ack interrupts, disable EFC interrupt */
2406         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2407         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2408         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2409         I915_WRITE(DEIIR, DE_PCU_EVENT);
2410         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2411
2412         /* Go back to the starting frequency */
2413         ironlake_set_drps(dev, dev_priv->ips.fstart);
2414         mdelay(1);
2415         rgvswctl |= MEMCTL_CMD_STS;
2416         I915_WRITE(MEMSWCTL, rgvswctl);
2417         mdelay(1);
2418
2419         spin_unlock_irq(&mchdev_lock);
2420 }
2421
2422 /* There's a funny hw issue where the hw returns all 0 when reading from
2423  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2424  * ourselves, instead of doing a rmw cycle (which might result in us clearing
2425  * all limits and the gpu stuck at whatever frequency it is at atm).
2426  */
2427 static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2428 {
2429         u32 limits;
2430
2431         limits = 0;
2432
2433         if (*val >= dev_priv->rps.max_delay)
2434                 *val = dev_priv->rps.max_delay;
2435         limits |= dev_priv->rps.max_delay << 24;
2436
2437         /* Only set the down limit when we've reached the lowest level to avoid
2438          * getting more interrupts, otherwise leave this clear. This prevents a
2439          * race in the hw when coming out of rc6: There's a tiny window where
2440          * the hw runs at the minimal clock before selecting the desired
2441          * frequency, if the down threshold expires in that window we will not
2442          * receive a down interrupt. */
2443         if (*val <= dev_priv->rps.min_delay) {
2444                 *val = dev_priv->rps.min_delay;
2445                 limits |= dev_priv->rps.min_delay << 16;
2446         }
2447
2448         return limits;
2449 }
2450
2451 void gen6_set_rps(struct drm_device *dev, u8 val)
2452 {
2453         struct drm_i915_private *dev_priv = dev->dev_private;
2454         u32 limits = gen6_rps_limits(dev_priv, &val);
2455
2456         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2457         WARN_ON(val > dev_priv->rps.max_delay);
2458         WARN_ON(val < dev_priv->rps.min_delay);
2459
2460         if (val == dev_priv->rps.cur_delay)
2461                 return;
2462
2463         if (IS_HASWELL(dev))
2464                 I915_WRITE(GEN6_RPNSWREQ,
2465                            HSW_FREQUENCY(val));
2466         else
2467                 I915_WRITE(GEN6_RPNSWREQ,
2468                            GEN6_FREQUENCY(val) |
2469                            GEN6_OFFSET(0) |
2470                            GEN6_AGGRESSIVE_TURBO);
2471
2472         /* Make sure we continue to get interrupts
2473          * until we hit the minimum or maximum frequencies.
2474          */
2475         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2476
2477         POSTING_READ(GEN6_RPNSWREQ);
2478
2479         dev_priv->rps.cur_delay = val;
2480
2481         trace_intel_gpu_freq_change(val * 50);
2482 }
2483
2484 void valleyview_set_rps(struct drm_device *dev, u8 val)
2485 {
2486         struct drm_i915_private *dev_priv = dev->dev_private;
2487         unsigned long timeout = jiffies + msecs_to_jiffies(10);
2488         u32 limits = gen6_rps_limits(dev_priv, &val);
2489         u32 pval;
2490
2491         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2492         WARN_ON(val > dev_priv->rps.max_delay);
2493         WARN_ON(val < dev_priv->rps.min_delay);
2494
2495         DRM_DEBUG_DRIVER("gpu freq request from %d to %d\n",
2496                          vlv_gpu_freq(dev_priv->mem_freq,
2497                                       dev_priv->rps.cur_delay),
2498                          vlv_gpu_freq(dev_priv->mem_freq, val));
2499
2500         if (val == dev_priv->rps.cur_delay)
2501                 return;
2502
2503         valleyview_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
2504
2505         do {
2506                 valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
2507                 if (time_after(jiffies, timeout)) {
2508                         DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
2509                         break;
2510                 }
2511                 udelay(10);
2512         } while (pval & 1);
2513
2514         valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &pval);
2515         if ((pval >> 8) != val)
2516                 DRM_DEBUG_DRIVER("punit overrode freq: %d requested, but got %d\n",
2517                           val, pval >> 8);
2518
2519         /* Make sure we continue to get interrupts
2520          * until we hit the minimum or maximum frequencies.
2521          */
2522         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2523
2524         dev_priv->rps.cur_delay = pval >> 8;
2525
2526         trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
2527 }
2528
2529
2530 static void gen6_disable_rps(struct drm_device *dev)
2531 {
2532         struct drm_i915_private *dev_priv = dev->dev_private;
2533
2534         I915_WRITE(GEN6_RC_CONTROL, 0);
2535         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2536         I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2537         I915_WRITE(GEN6_PMIER, 0);
2538         /* Complete PM interrupt masking here doesn't race with the rps work
2539          * item again unmasking PM interrupts because that is using a different
2540          * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2541          * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2542
2543         spin_lock_irq(&dev_priv->rps.lock);
2544         dev_priv->rps.pm_iir = 0;
2545         spin_unlock_irq(&dev_priv->rps.lock);
2546
2547         I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2548 }
2549
2550 int intel_enable_rc6(const struct drm_device *dev)
2551 {
2552         /* Respect the kernel parameter if it is set */
2553         if (i915_enable_rc6 >= 0)
2554                 return i915_enable_rc6;
2555
2556         /* Disable RC6 on Ironlake */
2557         if (INTEL_INFO(dev)->gen == 5)
2558                 return 0;
2559
2560         if (IS_HASWELL(dev)) {
2561                 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
2562                 return INTEL_RC6_ENABLE;
2563         }
2564
2565         /* snb/ivb have more than one rc6 state. */
2566         if (INTEL_INFO(dev)->gen == 6) {
2567                 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2568                 return INTEL_RC6_ENABLE;
2569         }
2570
2571         DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2572         return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2573 }
2574
2575 static void gen6_enable_rps(struct drm_device *dev)
2576 {
2577         struct drm_i915_private *dev_priv = dev->dev_private;
2578         struct intel_ring_buffer *ring;
2579         u32 rp_state_cap;
2580         u32 gt_perf_status;
2581         u32 rc6vids, pcu_mbox, rc6_mask = 0;
2582         u32 gtfifodbg;
2583         int rc6_mode;
2584         int i, ret;
2585
2586         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2587
2588         /* Here begins a magic sequence of register writes to enable
2589          * auto-downclocking.
2590          *
2591          * Perhaps there might be some value in exposing these to
2592          * userspace...
2593          */
2594         I915_WRITE(GEN6_RC_STATE, 0);
2595
2596         /* Clear the DBG now so we don't confuse earlier errors */
2597         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2598                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2599                 I915_WRITE(GTFIFODBG, gtfifodbg);
2600         }
2601
2602         gen6_gt_force_wake_get(dev_priv);
2603
2604         rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2605         gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2606
2607         /* In units of 50MHz */
2608         dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
2609         dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2610         dev_priv->rps.cur_delay = 0;
2611
2612         /* disable the counters and set deterministic thresholds */
2613         I915_WRITE(GEN6_RC_CONTROL, 0);
2614
2615         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2616         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2617         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2618         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2619         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2620
2621         for_each_ring(ring, dev_priv, i)
2622                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2623
2624         I915_WRITE(GEN6_RC_SLEEP, 0);
2625         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2626         I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
2627         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2628         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2629
2630         /* Check if we are enabling RC6 */
2631         rc6_mode = intel_enable_rc6(dev_priv->dev);
2632         if (rc6_mode & INTEL_RC6_ENABLE)
2633                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2634
2635         /* We don't use those on Haswell */
2636         if (!IS_HASWELL(dev)) {
2637                 if (rc6_mode & INTEL_RC6p_ENABLE)
2638                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2639
2640                 if (rc6_mode & INTEL_RC6pp_ENABLE)
2641                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2642         }
2643
2644         DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
2645                         (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2646                         (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2647                         (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2648
2649         I915_WRITE(GEN6_RC_CONTROL,
2650                    rc6_mask |
2651                    GEN6_RC_CTL_EI_MODE(1) |
2652                    GEN6_RC_CTL_HW_ENABLE);
2653
2654         if (IS_HASWELL(dev)) {
2655                 I915_WRITE(GEN6_RPNSWREQ,
2656                            HSW_FREQUENCY(10));
2657                 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2658                            HSW_FREQUENCY(12));
2659         } else {
2660                 I915_WRITE(GEN6_RPNSWREQ,
2661                            GEN6_FREQUENCY(10) |
2662                            GEN6_OFFSET(0) |
2663                            GEN6_AGGRESSIVE_TURBO);
2664                 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2665                            GEN6_FREQUENCY(12));
2666         }
2667
2668         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2669         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
2670                    dev_priv->rps.max_delay << 24 |
2671                    dev_priv->rps.min_delay << 16);
2672
2673         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2674         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2675         I915_WRITE(GEN6_RP_UP_EI, 66000);
2676         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2677
2678         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2679         I915_WRITE(GEN6_RP_CONTROL,
2680                    GEN6_RP_MEDIA_TURBO |
2681                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
2682                    GEN6_RP_MEDIA_IS_GFX |
2683                    GEN6_RP_ENABLE |
2684                    GEN6_RP_UP_BUSY_AVG |
2685                    (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2686
2687         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
2688         if (!ret && (IS_GEN6(dev) || IS_IVYBRIDGE(dev))) {
2689                 pcu_mbox = 0;
2690                 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
2691                 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
2692                         DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
2693                                          (dev_priv->rps.max_delay & 0xff) * 50,
2694                                          (pcu_mbox & 0xff) * 50);
2695                         dev_priv->rps.hw_max = pcu_mbox & 0xff;
2696                 }
2697         } else {
2698                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2699         }
2700
2701         gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2702
2703         /* requires MSI enabled */
2704         I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
2705         spin_lock_irq(&dev_priv->rps.lock);
2706         WARN_ON(dev_priv->rps.pm_iir != 0);
2707         I915_WRITE(GEN6_PMIMR, 0);
2708         spin_unlock_irq(&dev_priv->rps.lock);
2709         /* enable all PM interrupts */
2710         I915_WRITE(GEN6_PMINTRMSK, 0);
2711
2712         rc6vids = 0;
2713         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2714         if (IS_GEN6(dev) && ret) {
2715                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2716         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2717                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2718                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2719                 rc6vids &= 0xffff00;
2720                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2721                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2722                 if (ret)
2723                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2724         }
2725
2726         gen6_gt_force_wake_put(dev_priv);
2727 }
2728
2729 static void gen6_update_ring_freq(struct drm_device *dev)
2730 {
2731         struct drm_i915_private *dev_priv = dev->dev_private;
2732         int min_freq = 15;
2733         unsigned int gpu_freq;
2734         unsigned int max_ia_freq, min_ring_freq;
2735         int scaling_factor = 180;
2736
2737         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2738
2739         max_ia_freq = cpufreq_quick_get_max(0);
2740         /*
2741          * Default to measured freq if none found, PCU will ensure we don't go
2742          * over
2743          */
2744         if (!max_ia_freq)
2745                 max_ia_freq = tsc_khz;
2746
2747         /* Convert from kHz to MHz */
2748         max_ia_freq /= 1000;
2749
2750         min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
2751         /* convert DDR frequency from units of 133.3MHz to bandwidth */
2752         min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
2753
2754         /*
2755          * For each potential GPU frequency, load a ring frequency we'd like
2756          * to use for memory access.  We do this by specifying the IA frequency
2757          * the PCU should use as a reference to determine the ring frequency.
2758          */
2759         for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2760              gpu_freq--) {
2761                 int diff = dev_priv->rps.max_delay - gpu_freq;
2762                 unsigned int ia_freq = 0, ring_freq = 0;
2763
2764                 if (IS_HASWELL(dev)) {
2765                         ring_freq = (gpu_freq * 5 + 3) / 4;
2766                         ring_freq = max(min_ring_freq, ring_freq);
2767                         /* leave ia_freq as the default, chosen by cpufreq */
2768                 } else {
2769                         /* On older processors, there is no separate ring
2770                          * clock domain, so in order to boost the bandwidth
2771                          * of the ring, we need to upclock the CPU (ia_freq).
2772                          *
2773                          * For GPU frequencies less than 750MHz,
2774                          * just use the lowest ring freq.
2775                          */
2776                         if (gpu_freq < min_freq)
2777                                 ia_freq = 800;
2778                         else
2779                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2780                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
2781                 }
2782
2783                 sandybridge_pcode_write(dev_priv,
2784                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2785                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
2786                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
2787                                         gpu_freq);
2788         }
2789 }
2790
2791 int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
2792 {
2793         u32 val, rp0;
2794
2795         valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE, &val);
2796
2797         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
2798         /* Clamp to max */
2799         rp0 = min_t(u32, rp0, 0xea);
2800
2801         return rp0;
2802 }
2803
2804 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
2805 {
2806         u32 val, rpe;
2807
2808         valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO, &val);
2809         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
2810         valleyview_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI, &val);
2811         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
2812
2813         return rpe;
2814 }
2815
2816 int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
2817 {
2818         u32 val;
2819
2820         valleyview_punit_read(dev_priv, PUNIT_REG_GPU_LFM, &val);
2821
2822         return val & 0xff;
2823 }
2824
2825 static void valleyview_enable_rps(struct drm_device *dev)
2826 {
2827         struct drm_i915_private *dev_priv = dev->dev_private;
2828         struct intel_ring_buffer *ring;
2829         u32 gtfifodbg, val, rpe;
2830         int i;
2831
2832         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
2833
2834         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2835                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2836                 I915_WRITE(GTFIFODBG, gtfifodbg);
2837         }
2838
2839         gen6_gt_force_wake_get(dev_priv);
2840
2841         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2842         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2843         I915_WRITE(GEN6_RP_UP_EI, 66000);
2844         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
2845
2846         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2847
2848         I915_WRITE(GEN6_RP_CONTROL,
2849                    GEN6_RP_MEDIA_TURBO |
2850                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
2851                    GEN6_RP_MEDIA_IS_GFX |
2852                    GEN6_RP_ENABLE |
2853                    GEN6_RP_UP_BUSY_AVG |
2854                    GEN6_RP_DOWN_IDLE_CONT);
2855
2856         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
2857         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2858         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2859
2860         for_each_ring(ring, dev_priv, i)
2861                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2862
2863         I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
2864
2865         /* allows RC6 residency counter to work */
2866         I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
2867         I915_WRITE(GEN6_RC_CONTROL,
2868                    GEN7_RC_CTL_TO_MODE);
2869
2870         valleyview_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS, &val);
2871         dev_priv->mem_freq = 800 + (266 * (val >> 6) & 3);
2872         DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
2873
2874         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
2875         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
2876
2877         DRM_DEBUG_DRIVER("current GPU freq: %d\n",
2878                          vlv_gpu_freq(dev_priv->mem_freq, (val >> 8) & 0xff));
2879         dev_priv->rps.cur_delay = (val >> 8) & 0xff;
2880
2881         dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
2882         dev_priv->rps.hw_max = dev_priv->rps.max_delay;
2883         DRM_DEBUG_DRIVER("max GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
2884                                                      dev_priv->rps.max_delay));
2885
2886         rpe = valleyview_rps_rpe_freq(dev_priv);
2887         DRM_DEBUG_DRIVER("RPe GPU freq: %d\n",
2888                          vlv_gpu_freq(dev_priv->mem_freq, rpe));
2889
2890         val = valleyview_rps_min_freq(dev_priv);
2891         DRM_DEBUG_DRIVER("min GPU freq: %d\n", vlv_gpu_freq(dev_priv->mem_freq,
2892                                                             val));
2893         dev_priv->rps.min_delay = val;
2894
2895         DRM_DEBUG_DRIVER("setting GPU freq to %d\n",
2896                          vlv_gpu_freq(dev_priv->mem_freq, rpe));
2897
2898         valleyview_set_rps(dev_priv->dev, rpe);
2899
2900         /* requires MSI enabled */
2901         I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
2902         spin_lock_irq(&dev_priv->rps.lock);
2903         WARN_ON(dev_priv->rps.pm_iir != 0);
2904         I915_WRITE(GEN6_PMIMR, 0);
2905         spin_unlock_irq(&dev_priv->rps.lock);
2906         /* enable all PM interrupts */
2907         I915_WRITE(GEN6_PMINTRMSK, 0);
2908
2909         gen6_gt_force_wake_put(dev_priv);
2910 }
2911
2912 void ironlake_teardown_rc6(struct drm_device *dev)
2913 {
2914         struct drm_i915_private *dev_priv = dev->dev_private;
2915
2916         if (dev_priv->ips.renderctx) {
2917                 i915_gem_object_unpin(dev_priv->ips.renderctx);
2918                 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
2919                 dev_priv->ips.renderctx = NULL;
2920         }
2921
2922         if (dev_priv->ips.pwrctx) {
2923                 i915_gem_object_unpin(dev_priv->ips.pwrctx);
2924                 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
2925                 dev_priv->ips.pwrctx = NULL;
2926         }
2927 }
2928
2929 static void ironlake_disable_rc6(struct drm_device *dev)
2930 {
2931         struct drm_i915_private *dev_priv = dev->dev_private;
2932
2933         if (I915_READ(PWRCTXA)) {
2934                 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2935                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2936                 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2937                          50);
2938
2939                 I915_WRITE(PWRCTXA, 0);
2940                 POSTING_READ(PWRCTXA);
2941
2942                 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2943                 POSTING_READ(RSTDBYCTL);
2944         }
2945 }
2946
2947 static int ironlake_setup_rc6(struct drm_device *dev)
2948 {
2949         struct drm_i915_private *dev_priv = dev->dev_private;
2950
2951         if (dev_priv->ips.renderctx == NULL)
2952                 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
2953         if (!dev_priv->ips.renderctx)
2954                 return -ENOMEM;
2955
2956         if (dev_priv->ips.pwrctx == NULL)
2957                 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
2958         if (!dev_priv->ips.pwrctx) {
2959                 ironlake_teardown_rc6(dev);
2960                 return -ENOMEM;
2961         }
2962
2963         return 0;
2964 }
2965
2966 static void ironlake_enable_rc6(struct drm_device *dev)
2967 {
2968         struct drm_i915_private *dev_priv = dev->dev_private;
2969         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
2970         bool was_interruptible;
2971         int ret;
2972
2973         /* rc6 disabled by default due to repeated reports of hanging during
2974          * boot and resume.
2975          */
2976         if (!intel_enable_rc6(dev))
2977                 return;
2978
2979         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2980
2981         ret = ironlake_setup_rc6(dev);
2982         if (ret)
2983                 return;
2984
2985         was_interruptible = dev_priv->mm.interruptible;
2986         dev_priv->mm.interruptible = false;
2987
2988         /*
2989          * GPU can automatically power down the render unit if given a page
2990          * to save state.
2991          */
2992         ret = intel_ring_begin(ring, 6);
2993         if (ret) {
2994                 ironlake_teardown_rc6(dev);
2995                 dev_priv->mm.interruptible = was_interruptible;
2996                 return;
2997         }
2998
2999         intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3000         intel_ring_emit(ring, MI_SET_CONTEXT);
3001         intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
3002                         MI_MM_SPACE_GTT |
3003                         MI_SAVE_EXT_STATE_EN |
3004                         MI_RESTORE_EXT_STATE_EN |
3005                         MI_RESTORE_INHIBIT);
3006         intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3007         intel_ring_emit(ring, MI_NOOP);
3008         intel_ring_emit(ring, MI_FLUSH);
3009         intel_ring_advance(ring);
3010
3011         /*
3012          * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3013          * does an implicit flush, combined with MI_FLUSH above, it should be
3014          * safe to assume that renderctx is valid
3015          */
3016         ret = intel_ring_idle(ring);
3017         dev_priv->mm.interruptible = was_interruptible;
3018         if (ret) {
3019                 DRM_ERROR("failed to enable ironlake power savings\n");
3020                 ironlake_teardown_rc6(dev);
3021                 return;
3022         }
3023
3024         I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
3025         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3026 }
3027
3028 static unsigned long intel_pxfreq(u32 vidfreq)
3029 {
3030         unsigned long freq;
3031         int div = (vidfreq & 0x3f0000) >> 16;
3032         int post = (vidfreq & 0x3000) >> 12;
3033         int pre = (vidfreq & 0x7);
3034
3035         if (!pre)
3036                 return 0;
3037
3038         freq = ((div * 133333) / ((1<<post) * pre));
3039
3040         return freq;
3041 }
3042
3043 static const struct cparams {
3044         u16 i;
3045         u16 t;
3046         u16 m;
3047         u16 c;
3048 } cparams[] = {
3049         { 1, 1333, 301, 28664 },
3050         { 1, 1066, 294, 24460 },
3051         { 1, 800, 294, 25192 },
3052         { 0, 1333, 276, 27605 },
3053         { 0, 1066, 276, 27605 },
3054         { 0, 800, 231, 23784 },
3055 };
3056
3057 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
3058 {
3059         u64 total_count, diff, ret;
3060         u32 count1, count2, count3, m = 0, c = 0;
3061         unsigned long now = jiffies_to_msecs(jiffies), diff1;
3062         int i;
3063
3064         assert_spin_locked(&mchdev_lock);
3065
3066         diff1 = now - dev_priv->ips.last_time1;
3067
3068         /* Prevent division-by-zero if we are asking too fast.
3069          * Also, we don't get interesting results if we are polling
3070          * faster than once in 10ms, so just return the saved value
3071          * in such cases.
3072          */
3073         if (diff1 <= 10)
3074                 return dev_priv->ips.chipset_power;
3075
3076         count1 = I915_READ(DMIEC);
3077         count2 = I915_READ(DDREC);
3078         count3 = I915_READ(CSIEC);
3079
3080         total_count = count1 + count2 + count3;
3081
3082         /* FIXME: handle per-counter overflow */
3083         if (total_count < dev_priv->ips.last_count1) {
3084                 diff = ~0UL - dev_priv->ips.last_count1;
3085                 diff += total_count;
3086         } else {
3087                 diff = total_count - dev_priv->ips.last_count1;
3088         }
3089
3090         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
3091                 if (cparams[i].i == dev_priv->ips.c_m &&
3092                     cparams[i].t == dev_priv->ips.r_t) {
3093                         m = cparams[i].m;
3094                         c = cparams[i].c;
3095                         break;
3096                 }
3097         }
3098
3099         diff = div_u64(diff, diff1);
3100         ret = ((m * diff) + c);
3101         ret = div_u64(ret, 10);
3102
3103         dev_priv->ips.last_count1 = total_count;
3104         dev_priv->ips.last_time1 = now;
3105
3106         dev_priv->ips.chipset_power = ret;
3107
3108         return ret;
3109 }
3110
3111 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3112 {
3113         unsigned long val;
3114
3115         if (dev_priv->info->gen != 5)
3116                 return 0;
3117
3118         spin_lock_irq(&mchdev_lock);
3119
3120         val = __i915_chipset_val(dev_priv);
3121
3122         spin_unlock_irq(&mchdev_lock);
3123
3124         return val;
3125 }
3126
3127 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3128 {
3129         unsigned long m, x, b;
3130         u32 tsfs;
3131
3132         tsfs = I915_READ(TSFS);
3133
3134         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3135         x = I915_READ8(TR1);
3136
3137         b = tsfs & TSFS_INTR_MASK;
3138
3139         return ((m * x) / 127) - b;
3140 }
3141
3142 static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3143 {
3144         static const struct v_table {
3145                 u16 vd; /* in .1 mil */
3146                 u16 vm; /* in .1 mil */
3147         } v_table[] = {
3148                 { 0, 0, },
3149                 { 375, 0, },
3150                 { 500, 0, },
3151                 { 625, 0, },
3152                 { 750, 0, },
3153                 { 875, 0, },
3154                 { 1000, 0, },
3155                 { 1125, 0, },
3156                 { 4125, 3000, },
3157                 { 4125, 3000, },
3158                 { 4125, 3000, },
3159                 { 4125, 3000, },
3160                 { 4125, 3000, },
3161                 { 4125, 3000, },
3162                 { 4125, 3000, },
3163                 { 4125, 3000, },
3164                 { 4125, 3000, },
3165                 { 4125, 3000, },
3166                 { 4125, 3000, },
3167                 { 4125, 3000, },
3168                 { 4125, 3000, },
3169                 { 4125, 3000, },
3170                 { 4125, 3000, },
3171                 { 4125, 3000, },
3172                 { 4125, 3000, },
3173                 { 4125, 3000, },
3174                 { 4125, 3000, },
3175                 { 4125, 3000, },
3176                 { 4125, 3000, },
3177                 { 4125, 3000, },
3178                 { 4125, 3000, },
3179                 { 4125, 3000, },
3180                 { 4250, 3125, },
3181                 { 4375, 3250, },
3182                 { 4500, 3375, },
3183                 { 4625, 3500, },
3184                 { 4750, 3625, },
3185                 { 4875, 3750, },
3186                 { 5000, 3875, },
3187                 { 5125, 4000, },
3188                 { 5250, 4125, },
3189                 { 5375, 4250, },
3190                 { 5500, 4375, },
3191                 { 5625, 4500, },
3192                 { 5750, 4625, },
3193                 { 5875, 4750, },
3194                 { 6000, 4875, },
3195                 { 6125, 5000, },
3196                 { 6250, 5125, },
3197                 { 6375, 5250, },
3198                 { 6500, 5375, },
3199                 { 6625, 5500, },
3200                 { 6750, 5625, },
3201                 { 6875, 5750, },
3202                 { 7000, 5875, },
3203                 { 7125, 6000, },
3204                 { 7250, 6125, },
3205                 { 7375, 6250, },
3206                 { 7500, 6375, },
3207                 { 7625, 6500, },
3208                 { 7750, 6625, },
3209                 { 7875, 6750, },
3210                 { 8000, 6875, },
3211                 { 8125, 7000, },
3212                 { 8250, 7125, },
3213                 { 8375, 7250, },
3214                 { 8500, 7375, },
3215                 { 8625, 7500, },
3216                 { 8750, 7625, },
3217                 { 8875, 7750, },
3218                 { 9000, 7875, },
3219                 { 9125, 8000, },
3220                 { 9250, 8125, },
3221                 { 9375, 8250, },
3222                 { 9500, 8375, },
3223                 { 9625, 8500, },
3224                 { 9750, 8625, },
3225                 { 9875, 8750, },
3226                 { 10000, 8875, },
3227                 { 10125, 9000, },
3228                 { 10250, 9125, },
3229                 { 10375, 9250, },
3230                 { 10500, 9375, },
3231                 { 10625, 9500, },
3232                 { 10750, 9625, },
3233                 { 10875, 9750, },
3234                 { 11000, 9875, },
3235                 { 11125, 10000, },
3236                 { 11250, 10125, },
3237                 { 11375, 10250, },
3238                 { 11500, 10375, },
3239                 { 11625, 10500, },
3240                 { 11750, 10625, },
3241                 { 11875, 10750, },
3242                 { 12000, 10875, },
3243                 { 12125, 11000, },
3244                 { 12250, 11125, },
3245                 { 12375, 11250, },
3246                 { 12500, 11375, },
3247                 { 12625, 11500, },
3248                 { 12750, 11625, },
3249                 { 12875, 11750, },
3250                 { 13000, 11875, },
3251                 { 13125, 12000, },
3252                 { 13250, 12125, },
3253                 { 13375, 12250, },
3254                 { 13500, 12375, },
3255                 { 13625, 12500, },
3256                 { 13750, 12625, },
3257                 { 13875, 12750, },
3258                 { 14000, 12875, },
3259                 { 14125, 13000, },
3260                 { 14250, 13125, },
3261                 { 14375, 13250, },
3262                 { 14500, 13375, },
3263                 { 14625, 13500, },
3264                 { 14750, 13625, },
3265                 { 14875, 13750, },
3266                 { 15000, 13875, },
3267                 { 15125, 14000, },
3268                 { 15250, 14125, },
3269                 { 15375, 14250, },
3270                 { 15500, 14375, },
3271                 { 15625, 14500, },
3272                 { 15750, 14625, },
3273                 { 15875, 14750, },
3274                 { 16000, 14875, },
3275                 { 16125, 15000, },
3276         };
3277         if (dev_priv->info->is_mobile)
3278                 return v_table[pxvid].vm;
3279         else
3280                 return v_table[pxvid].vd;
3281 }
3282
3283 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
3284 {
3285         struct timespec now, diff1;
3286         u64 diff;
3287         unsigned long diffms;
3288         u32 count;
3289
3290         assert_spin_locked(&mchdev_lock);
3291
3292         getrawmonotonic(&now);
3293         diff1 = timespec_sub(now, dev_priv->ips.last_time2);
3294
3295         /* Don't divide by 0 */
3296         diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3297         if (!diffms)
3298                 return;
3299
3300         count = I915_READ(GFXEC);
3301
3302         if (count < dev_priv->ips.last_count2) {
3303                 diff = ~0UL - dev_priv->ips.last_count2;
3304                 diff += count;
3305         } else {
3306                 diff = count - dev_priv->ips.last_count2;
3307         }
3308
3309         dev_priv->ips.last_count2 = count;
3310         dev_priv->ips.last_time2 = now;
3311
3312         /* More magic constants... */
3313         diff = diff * 1181;
3314         diff = div_u64(diff, diffms * 10);
3315         dev_priv->ips.gfx_power = diff;
3316 }
3317
3318 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3319 {
3320         if (dev_priv->info->gen != 5)
3321                 return;
3322
3323         spin_lock_irq(&mchdev_lock);
3324
3325         __i915_update_gfx_val(dev_priv);
3326
3327         spin_unlock_irq(&mchdev_lock);
3328 }
3329
3330 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
3331 {
3332         unsigned long t, corr, state1, corr2, state2;
3333         u32 pxvid, ext_v;
3334
3335         assert_spin_locked(&mchdev_lock);
3336
3337         pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
3338         pxvid = (pxvid >> 24) & 0x7f;
3339         ext_v = pvid_to_extvid(dev_priv, pxvid);
3340
3341         state1 = ext_v;
3342
3343         t = i915_mch_val(dev_priv);
3344
3345         /* Revel in the empirically derived constants */
3346
3347         /* Correction factor in 1/100000 units */
3348         if (t > 80)
3349                 corr = ((t * 2349) + 135940);
3350         else if (t >= 50)
3351                 corr = ((t * 964) + 29317);
3352         else /* < 50 */
3353                 corr = ((t * 301) + 1004);
3354
3355         corr = corr * ((150142 * state1) / 10000 - 78642);
3356         corr /= 100000;
3357         corr2 = (corr * dev_priv->ips.corr);
3358
3359         state2 = (corr2 * state1) / 10000;
3360         state2 /= 100; /* convert to mW */
3361
3362         __i915_update_gfx_val(dev_priv);
3363
3364         return dev_priv->ips.gfx_power + state2;
3365 }
3366
3367 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3368 {
3369         unsigned long val;
3370
3371         if (dev_priv->info->gen != 5)
3372                 return 0;
3373
3374         spin_lock_irq(&mchdev_lock);
3375
3376         val = __i915_gfx_val(dev_priv);
3377
3378         spin_unlock_irq(&mchdev_lock);
3379
3380         return val;
3381 }
3382
3383 /**
3384  * i915_read_mch_val - return value for IPS use
3385  *
3386  * Calculate and return a value for the IPS driver to use when deciding whether
3387  * we have thermal and power headroom to increase CPU or GPU power budget.
3388  */
3389 unsigned long i915_read_mch_val(void)
3390 {
3391         struct drm_i915_private *dev_priv;
3392         unsigned long chipset_val, graphics_val, ret = 0;
3393
3394         spin_lock_irq(&mchdev_lock);
3395         if (!i915_mch_dev)
3396                 goto out_unlock;
3397         dev_priv = i915_mch_dev;
3398
3399         chipset_val = __i915_chipset_val(dev_priv);
3400         graphics_val = __i915_gfx_val(dev_priv);
3401
3402         ret = chipset_val + graphics_val;
3403
3404 out_unlock:
3405         spin_unlock_irq(&mchdev_lock);
3406
3407         return ret;
3408 }
3409 EXPORT_SYMBOL_GPL(i915_read_mch_val);
3410
3411 /**
3412  * i915_gpu_raise - raise GPU frequency limit
3413  *
3414  * Raise the limit; IPS indicates we have thermal headroom.
3415  */
3416 bool i915_gpu_raise(void)
3417 {
3418         struct drm_i915_private *dev_priv;
3419         bool ret = true;
3420
3421         spin_lock_irq(&mchdev_lock);
3422         if (!i915_mch_dev) {
3423                 ret = false;
3424                 goto out_unlock;
3425         }
3426         dev_priv = i915_mch_dev;
3427
3428         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3429                 dev_priv->ips.max_delay--;
3430
3431 out_unlock:
3432         spin_unlock_irq(&mchdev_lock);
3433
3434         return ret;
3435 }
3436 EXPORT_SYMBOL_GPL(i915_gpu_raise);
3437
3438 /**
3439  * i915_gpu_lower - lower GPU frequency limit
3440  *
3441  * IPS indicates we're close to a thermal limit, so throttle back the GPU
3442  * frequency maximum.
3443  */
3444 bool i915_gpu_lower(void)
3445 {
3446         struct drm_i915_private *dev_priv;
3447         bool ret = true;
3448
3449         spin_lock_irq(&mchdev_lock);
3450         if (!i915_mch_dev) {
3451                 ret = false;
3452                 goto out_unlock;
3453         }
3454         dev_priv = i915_mch_dev;
3455
3456         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3457                 dev_priv->ips.max_delay++;
3458
3459 out_unlock:
3460         spin_unlock_irq(&mchdev_lock);
3461
3462         return ret;
3463 }
3464 EXPORT_SYMBOL_GPL(i915_gpu_lower);
3465
3466 /**
3467  * i915_gpu_busy - indicate GPU business to IPS
3468  *
3469  * Tell the IPS driver whether or not the GPU is busy.
3470  */
3471 bool i915_gpu_busy(void)
3472 {
3473         struct drm_i915_private *dev_priv;
3474         struct intel_ring_buffer *ring;
3475         bool ret = false;
3476         int i;
3477
3478         spin_lock_irq(&mchdev_lock);
3479         if (!i915_mch_dev)
3480                 goto out_unlock;
3481         dev_priv = i915_mch_dev;
3482
3483         for_each_ring(ring, dev_priv, i)
3484                 ret |= !list_empty(&ring->request_list);
3485
3486 out_unlock:
3487         spin_unlock_irq(&mchdev_lock);
3488
3489         return ret;
3490 }
3491 EXPORT_SYMBOL_GPL(i915_gpu_busy);
3492
3493 /**
3494  * i915_gpu_turbo_disable - disable graphics turbo
3495  *
3496  * Disable graphics turbo by resetting the max frequency and setting the
3497  * current frequency to the default.
3498  */
3499 bool i915_gpu_turbo_disable(void)
3500 {
3501         struct drm_i915_private *dev_priv;
3502         bool ret = true;
3503
3504         spin_lock_irq(&mchdev_lock);
3505         if (!i915_mch_dev) {
3506                 ret = false;
3507                 goto out_unlock;
3508         }
3509         dev_priv = i915_mch_dev;
3510
3511         dev_priv->ips.max_delay = dev_priv->ips.fstart;
3512
3513         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
3514                 ret = false;
3515
3516 out_unlock:
3517         spin_unlock_irq(&mchdev_lock);
3518
3519         return ret;
3520 }
3521 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3522
3523 /**
3524  * Tells the intel_ips driver that the i915 driver is now loaded, if
3525  * IPS got loaded first.
3526  *
3527  * This awkward dance is so that neither module has to depend on the
3528  * other in order for IPS to do the appropriate communication of
3529  * GPU turbo limits to i915.
3530  */
3531 static void
3532 ips_ping_for_i915_load(void)
3533 {
3534         void (*link)(void);
3535
3536         link = symbol_get(ips_link_to_i915_driver);
3537         if (link) {
3538                 link();
3539                 symbol_put(ips_link_to_i915_driver);
3540         }
3541 }
3542
3543 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3544 {
3545         /* We only register the i915 ips part with intel-ips once everything is
3546          * set up, to avoid intel-ips sneaking in and reading bogus values. */
3547         spin_lock_irq(&mchdev_lock);
3548         i915_mch_dev = dev_priv;
3549         spin_unlock_irq(&mchdev_lock);
3550
3551         ips_ping_for_i915_load();
3552 }
3553
3554 void intel_gpu_ips_teardown(void)
3555 {
3556         spin_lock_irq(&mchdev_lock);
3557         i915_mch_dev = NULL;
3558         spin_unlock_irq(&mchdev_lock);
3559 }
3560 static void intel_init_emon(struct drm_device *dev)
3561 {
3562         struct drm_i915_private *dev_priv = dev->dev_private;
3563         u32 lcfuse;
3564         u8 pxw[16];
3565         int i;
3566
3567         /* Disable to program */
3568         I915_WRITE(ECR, 0);
3569         POSTING_READ(ECR);
3570
3571         /* Program energy weights for various events */
3572         I915_WRITE(SDEW, 0x15040d00);
3573         I915_WRITE(CSIEW0, 0x007f0000);
3574         I915_WRITE(CSIEW1, 0x1e220004);
3575         I915_WRITE(CSIEW2, 0x04000004);
3576
3577         for (i = 0; i < 5; i++)
3578                 I915_WRITE(PEW + (i * 4), 0);
3579         for (i = 0; i < 3; i++)
3580                 I915_WRITE(DEW + (i * 4), 0);
3581
3582         /* Program P-state weights to account for frequency power adjustment */
3583         for (i = 0; i < 16; i++) {
3584                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3585                 unsigned long freq = intel_pxfreq(pxvidfreq);
3586                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3587                         PXVFREQ_PX_SHIFT;
3588                 unsigned long val;
3589
3590                 val = vid * vid;
3591                 val *= (freq / 1000);
3592                 val *= 255;
3593                 val /= (127*127*900);
3594                 if (val > 0xff)
3595                         DRM_ERROR("bad pxval: %ld\n", val);
3596                 pxw[i] = val;
3597         }
3598         /* Render standby states get 0 weight */
3599         pxw[14] = 0;
3600         pxw[15] = 0;
3601
3602         for (i = 0; i < 4; i++) {
3603                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3604                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3605                 I915_WRITE(PXW + (i * 4), val);
3606         }
3607
3608         /* Adjust magic regs to magic values (more experimental results) */
3609         I915_WRITE(OGW0, 0);
3610         I915_WRITE(OGW1, 0);
3611         I915_WRITE(EG0, 0x00007f00);
3612         I915_WRITE(EG1, 0x0000000e);
3613         I915_WRITE(EG2, 0x000e0000);
3614         I915_WRITE(EG3, 0x68000300);
3615         I915_WRITE(EG4, 0x42000000);
3616         I915_WRITE(EG5, 0x00140031);
3617         I915_WRITE(EG6, 0);
3618         I915_WRITE(EG7, 0);
3619
3620         for (i = 0; i < 8; i++)
3621                 I915_WRITE(PXWL + (i * 4), 0);
3622
3623         /* Enable PMON + select events */
3624         I915_WRITE(ECR, 0x80000019);
3625
3626         lcfuse = I915_READ(LCFUSE02);
3627
3628         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
3629 }
3630
3631 void intel_disable_gt_powersave(struct drm_device *dev)
3632 {
3633         struct drm_i915_private *dev_priv = dev->dev_private;
3634
3635         if (IS_IRONLAKE_M(dev)) {
3636                 ironlake_disable_drps(dev);
3637                 ironlake_disable_rc6(dev);
3638         } else if (INTEL_INFO(dev)->gen >= 6) {
3639                 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
3640                 mutex_lock(&dev_priv->rps.hw_lock);
3641                 gen6_disable_rps(dev);
3642                 mutex_unlock(&dev_priv->rps.hw_lock);
3643         }
3644 }
3645
3646 static void intel_gen6_powersave_work(struct work_struct *work)
3647 {
3648         struct drm_i915_private *dev_priv =
3649                 container_of(work, struct drm_i915_private,
3650                              rps.delayed_resume_work.work);
3651         struct drm_device *dev = dev_priv->dev;
3652
3653         mutex_lock(&dev_priv->rps.hw_lock);
3654
3655         if (IS_VALLEYVIEW(dev)) {
3656                 valleyview_enable_rps(dev);
3657         } else {
3658                 gen6_enable_rps(dev);
3659                 gen6_update_ring_freq(dev);
3660         }
3661         mutex_unlock(&dev_priv->rps.hw_lock);
3662 }
3663
3664 void intel_enable_gt_powersave(struct drm_device *dev)
3665 {
3666         struct drm_i915_private *dev_priv = dev->dev_private;
3667
3668         if (IS_IRONLAKE_M(dev)) {
3669                 ironlake_enable_drps(dev);
3670                 ironlake_enable_rc6(dev);
3671                 intel_init_emon(dev);
3672         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
3673                 /*
3674                  * PCU communication is slow and this doesn't need to be
3675                  * done at any specific time, so do this out of our fast path
3676                  * to make resume and init faster.
3677                  */
3678                 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3679                                       round_jiffies_up_relative(HZ));
3680         }
3681 }
3682
3683 static void ibx_init_clock_gating(struct drm_device *dev)
3684 {
3685         struct drm_i915_private *dev_priv = dev->dev_private;
3686
3687         /*
3688          * On Ibex Peak and Cougar Point, we need to disable clock
3689          * gating for the panel power sequencer or it will fail to
3690          * start up when no ports are active.
3691          */
3692         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3693 }
3694
3695 static void ironlake_init_clock_gating(struct drm_device *dev)
3696 {
3697         struct drm_i915_private *dev_priv = dev->dev_private;
3698         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3699
3700         /* Required for FBC */
3701         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3702                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3703                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
3704
3705         I915_WRITE(PCH_3DCGDIS0,
3706                    MARIUNIT_CLOCK_GATE_DISABLE |
3707                    SVSMUNIT_CLOCK_GATE_DISABLE);
3708         I915_WRITE(PCH_3DCGDIS1,
3709                    VFMUNIT_CLOCK_GATE_DISABLE);
3710
3711         /*
3712          * According to the spec the following bits should be set in
3713          * order to enable memory self-refresh
3714          * The bit 22/21 of 0x42004
3715          * The bit 5 of 0x42020
3716          * The bit 15 of 0x45000
3717          */
3718         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3719                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
3720                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
3721         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
3722         I915_WRITE(DISP_ARB_CTL,
3723                    (I915_READ(DISP_ARB_CTL) |
3724                     DISP_FBC_WM_DIS));
3725         I915_WRITE(WM3_LP_ILK, 0);
3726         I915_WRITE(WM2_LP_ILK, 0);
3727         I915_WRITE(WM1_LP_ILK, 0);
3728
3729         /*
3730          * Based on the document from hardware guys the following bits
3731          * should be set unconditionally in order to enable FBC.
3732          * The bit 22 of 0x42000
3733          * The bit 22 of 0x42004
3734          * The bit 7,8,9 of 0x42020.
3735          */
3736         if (IS_IRONLAKE_M(dev)) {
3737                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3738                            I915_READ(ILK_DISPLAY_CHICKEN1) |
3739                            ILK_FBCQ_DIS);
3740                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3741                            I915_READ(ILK_DISPLAY_CHICKEN2) |
3742                            ILK_DPARB_GATE);
3743         }
3744
3745         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3746
3747         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3748                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3749                    ILK_ELPIN_409_SELECT);
3750         I915_WRITE(_3D_CHICKEN2,
3751                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3752                    _3D_CHICKEN2_WM_READ_PIPELINED);
3753
3754         /* WaDisableRenderCachePipelinedFlush */
3755         I915_WRITE(CACHE_MODE_0,
3756                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3757
3758         ibx_init_clock_gating(dev);
3759 }
3760
3761 static void cpt_init_clock_gating(struct drm_device *dev)
3762 {
3763         struct drm_i915_private *dev_priv = dev->dev_private;
3764         int pipe;
3765         uint32_t val;
3766
3767         /*
3768          * On Ibex Peak and Cougar Point, we need to disable clock
3769          * gating for the panel power sequencer or it will fail to
3770          * start up when no ports are active.
3771          */
3772         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3773         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3774                    DPLS_EDP_PPS_FIX_DIS);
3775         /* The below fixes the weird display corruption, a few pixels shifted
3776          * downward, on (only) LVDS of some HP laptops with IVY.
3777          */
3778         for_each_pipe(pipe) {
3779                 val = I915_READ(TRANS_CHICKEN2(pipe));
3780                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
3781                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3782                 if (dev_priv->fdi_rx_polarity_inverted)
3783                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
3784                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
3785                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
3786                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3787                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
3788         }
3789         /* WADP0ClockGatingDisable */
3790         for_each_pipe(pipe) {
3791                 I915_WRITE(TRANS_CHICKEN1(pipe),
3792                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3793         }
3794 }
3795
3796 static void gen6_check_mch_setup(struct drm_device *dev)
3797 {
3798         struct drm_i915_private *dev_priv = dev->dev_private;
3799         uint32_t tmp;
3800
3801         tmp = I915_READ(MCH_SSKPD);
3802         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
3803                 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
3804                 DRM_INFO("This can cause pipe underruns and display issues.\n");
3805                 DRM_INFO("Please upgrade your BIOS to fix this.\n");
3806         }
3807 }
3808
3809 static void gen6_init_clock_gating(struct drm_device *dev)
3810 {
3811         struct drm_i915_private *dev_priv = dev->dev_private;
3812         int pipe;
3813         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
3814
3815         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3816
3817         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3818                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3819                    ILK_ELPIN_409_SELECT);
3820
3821         /* WaDisableHiZPlanesWhenMSAAEnabled */
3822         I915_WRITE(_3D_CHICKEN,
3823                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
3824
3825         /* WaSetupGtModeTdRowDispatch */
3826         if (IS_SNB_GT1(dev))
3827                 I915_WRITE(GEN6_GT_MODE,
3828                            _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
3829
3830         I915_WRITE(WM3_LP_ILK, 0);
3831         I915_WRITE(WM2_LP_ILK, 0);
3832         I915_WRITE(WM1_LP_ILK, 0);
3833
3834         I915_WRITE(CACHE_MODE_0,
3835                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
3836
3837         I915_WRITE(GEN6_UCGCTL1,
3838                    I915_READ(GEN6_UCGCTL1) |
3839                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3840                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3841
3842         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3843          * gating disable must be set.  Failure to set it results in
3844          * flickering pixels due to Z write ordering failures after
3845          * some amount of runtime in the Mesa "fire" demo, and Unigine
3846          * Sanctuary and Tropics, and apparently anything else with
3847          * alpha test or pixel discard.
3848          *
3849          * According to the spec, bit 11 (RCCUNIT) must also be set,
3850          * but we didn't debug actual testcases to find it out.
3851          *
3852          * Also apply WaDisableVDSUnitClockGating and
3853          * WaDisableRCPBUnitClockGating.
3854          */
3855         I915_WRITE(GEN6_UCGCTL2,
3856                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
3857                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3858                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3859
3860         /* Bspec says we need to always set all mask bits. */
3861         I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3862                    _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
3863
3864         /*
3865          * According to the spec the following bits should be
3866          * set in order to enable memory self-refresh and fbc:
3867          * The bit21 and bit22 of 0x42000
3868          * The bit21 and bit22 of 0x42004
3869          * The bit5 and bit7 of 0x42020
3870          * The bit14 of 0x70180
3871          * The bit14 of 0x71180
3872          */
3873         I915_WRITE(ILK_DISPLAY_CHICKEN1,
3874                    I915_READ(ILK_DISPLAY_CHICKEN1) |
3875                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3876         I915_WRITE(ILK_DISPLAY_CHICKEN2,
3877                    I915_READ(ILK_DISPLAY_CHICKEN2) |
3878                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
3879         I915_WRITE(ILK_DSPCLK_GATE_D,
3880                    I915_READ(ILK_DSPCLK_GATE_D) |
3881                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
3882                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
3883
3884         /* WaMbcDriverBootEnable */
3885         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3886                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3887
3888         for_each_pipe(pipe) {
3889                 I915_WRITE(DSPCNTR(pipe),
3890                            I915_READ(DSPCNTR(pipe)) |
3891                            DISPPLANE_TRICKLE_FEED_DISABLE);
3892                 intel_flush_display_plane(dev_priv, pipe);
3893         }
3894
3895         /* The default value should be 0x200 according to docs, but the two
3896          * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3897         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
3898         I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3899
3900         cpt_init_clock_gating(dev);
3901
3902         gen6_check_mch_setup(dev);
3903 }
3904
3905 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3906 {
3907         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3908
3909         reg &= ~GEN7_FF_SCHED_MASK;
3910         reg |= GEN7_FF_TS_SCHED_HW;
3911         reg |= GEN7_FF_VS_SCHED_HW;
3912         reg |= GEN7_FF_DS_SCHED_HW;
3913
3914         /* WaVSRefCountFullforceMissDisable */
3915         if (IS_HASWELL(dev_priv->dev))
3916                 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
3917
3918         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3919 }
3920
3921 static void lpt_init_clock_gating(struct drm_device *dev)
3922 {
3923         struct drm_i915_private *dev_priv = dev->dev_private;
3924
3925         /*
3926          * TODO: this bit should only be enabled when really needed, then
3927          * disabled when not needed anymore in order to save power.
3928          */
3929         if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
3930                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
3931                            I915_READ(SOUTH_DSPCLK_GATE_D) |
3932                            PCH_LP_PARTITION_LEVEL_DISABLE);
3933 }
3934
3935 static void haswell_init_clock_gating(struct drm_device *dev)
3936 {
3937         struct drm_i915_private *dev_priv = dev->dev_private;
3938         int pipe;
3939
3940         I915_WRITE(WM3_LP_ILK, 0);
3941         I915_WRITE(WM2_LP_ILK, 0);
3942         I915_WRITE(WM1_LP_ILK, 0);
3943
3944         /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3945          * This implements the WaDisableRCZUnitClockGating workaround.
3946          */
3947         I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3948
3949         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3950         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3951                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3952
3953         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3954         I915_WRITE(GEN7_L3CNTLREG1,
3955                         GEN7_WA_FOR_GEN7_L3_CONTROL);
3956         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3957                         GEN7_WA_L3_CHICKEN_MODE);
3958
3959         /* This is required by WaCatErrorRejectionIssue */
3960         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3961                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3962                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3963
3964         for_each_pipe(pipe) {
3965                 I915_WRITE(DSPCNTR(pipe),
3966                            I915_READ(DSPCNTR(pipe)) |
3967                            DISPPLANE_TRICKLE_FEED_DISABLE);
3968                 intel_flush_display_plane(dev_priv, pipe);
3969         }
3970
3971         gen7_setup_fixed_func_scheduler(dev_priv);
3972
3973         /* WaDisable4x2SubspanOptimization */
3974         I915_WRITE(CACHE_MODE_1,
3975                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
3976
3977         /* WaMbcDriverBootEnable */
3978         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3979                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
3980
3981         /* WaSwitchSolVfFArbitrationPriority */
3982         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
3983
3984         /* XXX: This is a workaround for early silicon revisions and should be
3985          * removed later.
3986          */
3987         I915_WRITE(WM_DBG,
3988                         I915_READ(WM_DBG) |
3989                         WM_DBG_DISALLOW_MULTIPLE_LP |
3990                         WM_DBG_DISALLOW_SPRITE |
3991                         WM_DBG_DISALLOW_MAXFIFO);
3992
3993         lpt_init_clock_gating(dev);
3994 }
3995
3996 static void ivybridge_init_clock_gating(struct drm_device *dev)
3997 {
3998         struct drm_i915_private *dev_priv = dev->dev_private;
3999         int pipe;
4000         uint32_t snpcr;
4001
4002         I915_WRITE(WM3_LP_ILK, 0);
4003         I915_WRITE(WM2_LP_ILK, 0);
4004         I915_WRITE(WM1_LP_ILK, 0);
4005
4006         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4007
4008         /* WaDisableEarlyCull */
4009         I915_WRITE(_3D_CHICKEN3,
4010                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4011
4012         /* WaDisableBackToBackFlipFix */
4013         I915_WRITE(IVB_CHICKEN3,
4014                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4015                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
4016
4017         /* WaDisablePSDDualDispatchEnable */
4018         if (IS_IVB_GT1(dev))
4019                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4020                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4021         else
4022                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4023                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4024
4025         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
4026         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4027                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4028
4029         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
4030         I915_WRITE(GEN7_L3CNTLREG1,
4031                         GEN7_WA_FOR_GEN7_L3_CONTROL);
4032         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4033                    GEN7_WA_L3_CHICKEN_MODE);
4034         if (IS_IVB_GT1(dev))
4035                 I915_WRITE(GEN7_ROW_CHICKEN2,
4036                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4037         else
4038                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4039                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4040
4041
4042         /* WaForceL3Serialization */
4043         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4044                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4045
4046         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4047          * gating disable must be set.  Failure to set it results in
4048          * flickering pixels due to Z write ordering failures after
4049          * some amount of runtime in the Mesa "fire" demo, and Unigine
4050          * Sanctuary and Tropics, and apparently anything else with
4051          * alpha test or pixel discard.
4052          *
4053          * According to the spec, bit 11 (RCCUNIT) must also be set,
4054          * but we didn't debug actual testcases to find it out.
4055          *
4056          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4057          * This implements the WaDisableRCZUnitClockGating workaround.
4058          */
4059         I915_WRITE(GEN6_UCGCTL2,
4060                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4061                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4062
4063         /* This is required by WaCatErrorRejectionIssue */
4064         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4065                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4066                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4067
4068         for_each_pipe(pipe) {
4069                 I915_WRITE(DSPCNTR(pipe),
4070                            I915_READ(DSPCNTR(pipe)) |
4071                            DISPPLANE_TRICKLE_FEED_DISABLE);
4072                 intel_flush_display_plane(dev_priv, pipe);
4073         }
4074
4075         /* WaMbcDriverBootEnable */
4076         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4077                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4078
4079         gen7_setup_fixed_func_scheduler(dev_priv);
4080
4081         /* WaDisable4x2SubspanOptimization */
4082         I915_WRITE(CACHE_MODE_1,
4083                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4084
4085         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4086         snpcr &= ~GEN6_MBC_SNPCR_MASK;
4087         snpcr |= GEN6_MBC_SNPCR_MED;
4088         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
4089
4090         if (!HAS_PCH_NOP(dev))
4091                 cpt_init_clock_gating(dev);
4092
4093         gen6_check_mch_setup(dev);
4094 }
4095
4096 static void valleyview_init_clock_gating(struct drm_device *dev)
4097 {
4098         struct drm_i915_private *dev_priv = dev->dev_private;
4099         int pipe;
4100
4101         I915_WRITE(WM3_LP_ILK, 0);
4102         I915_WRITE(WM2_LP_ILK, 0);
4103         I915_WRITE(WM1_LP_ILK, 0);
4104
4105         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
4106
4107         /* WaDisableEarlyCull */
4108         I915_WRITE(_3D_CHICKEN3,
4109                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4110
4111         /* WaDisableBackToBackFlipFix */
4112         I915_WRITE(IVB_CHICKEN3,
4113                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4114                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
4115
4116         /* WaDisablePSDDualDispatchEnable */
4117         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4118                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4119                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4120
4121         /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
4122         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4123                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4124
4125         /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
4126         I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
4127         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4128
4129         /* WaForceL3Serialization */
4130         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4131                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4132
4133         /* WaDisableDopClockGating */
4134         I915_WRITE(GEN7_ROW_CHICKEN2,
4135                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4136
4137         /* WaForceL3Serialization */
4138         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4139                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4140
4141         /* This is required by WaCatErrorRejectionIssue */
4142         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4143                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4144                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4145
4146         /* WaMbcDriverBootEnable */
4147         I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4148                    GEN6_MBCTL_ENABLE_BOOT_FETCH);
4149
4150
4151         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4152          * gating disable must be set.  Failure to set it results in
4153          * flickering pixels due to Z write ordering failures after
4154          * some amount of runtime in the Mesa "fire" demo, and Unigine
4155          * Sanctuary and Tropics, and apparently anything else with
4156          * alpha test or pixel discard.
4157          *
4158          * According to the spec, bit 11 (RCCUNIT) must also be set,
4159          * but we didn't debug actual testcases to find it out.
4160          *
4161          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
4162          * This implements the WaDisableRCZUnitClockGating workaround.
4163          *
4164          * Also apply WaDisableVDSUnitClockGating and
4165          * WaDisableRCPBUnitClockGating.
4166          */
4167         I915_WRITE(GEN6_UCGCTL2,
4168                    GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
4169                    GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
4170                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4171                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4172                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4173
4174         I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4175
4176         for_each_pipe(pipe) {
4177                 I915_WRITE(DSPCNTR(pipe),
4178                            I915_READ(DSPCNTR(pipe)) |
4179                            DISPPLANE_TRICKLE_FEED_DISABLE);
4180                 intel_flush_display_plane(dev_priv, pipe);
4181         }
4182
4183         I915_WRITE(CACHE_MODE_1,
4184                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
4185
4186         /*
4187          * WaDisableVLVClockGating_VBIIssue
4188          * Disable clock gating on th GCFG unit to prevent a delay
4189          * in the reporting of vblank events.
4190          */
4191         I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4192
4193         /* Conservative clock gating settings for now */
4194         I915_WRITE(0x9400, 0xffffffff);
4195         I915_WRITE(0x9404, 0xffffffff);
4196         I915_WRITE(0x9408, 0xffffffff);
4197         I915_WRITE(0x940c, 0xffffffff);
4198         I915_WRITE(0x9410, 0xffffffff);
4199         I915_WRITE(0x9414, 0xffffffff);
4200         I915_WRITE(0x9418, 0xffffffff);
4201 }
4202
4203 static void g4x_init_clock_gating(struct drm_device *dev)
4204 {
4205         struct drm_i915_private *dev_priv = dev->dev_private;
4206         uint32_t dspclk_gate;
4207
4208         I915_WRITE(RENCLK_GATE_D1, 0);
4209         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4210                    GS_UNIT_CLOCK_GATE_DISABLE |
4211                    CL_UNIT_CLOCK_GATE_DISABLE);
4212         I915_WRITE(RAMCLK_GATE_D, 0);
4213         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4214                 OVRUNIT_CLOCK_GATE_DISABLE |
4215                 OVCUNIT_CLOCK_GATE_DISABLE;
4216         if (IS_GM45(dev))
4217                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4218         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4219
4220         /* WaDisableRenderCachePipelinedFlush */
4221         I915_WRITE(CACHE_MODE_0,
4222                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
4223 }
4224
4225 static void crestline_init_clock_gating(struct drm_device *dev)
4226 {
4227         struct drm_i915_private *dev_priv = dev->dev_private;
4228
4229         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4230         I915_WRITE(RENCLK_GATE_D2, 0);
4231         I915_WRITE(DSPCLK_GATE_D, 0);
4232         I915_WRITE(RAMCLK_GATE_D, 0);
4233         I915_WRITE16(DEUC, 0);
4234 }
4235
4236 static void broadwater_init_clock_gating(struct drm_device *dev)
4237 {
4238         struct drm_i915_private *dev_priv = dev->dev_private;
4239
4240         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4241                    I965_RCC_CLOCK_GATE_DISABLE |
4242                    I965_RCPB_CLOCK_GATE_DISABLE |
4243                    I965_ISC_CLOCK_GATE_DISABLE |
4244                    I965_FBC_CLOCK_GATE_DISABLE);
4245         I915_WRITE(RENCLK_GATE_D2, 0);
4246 }
4247
4248 static void gen3_init_clock_gating(struct drm_device *dev)
4249 {
4250         struct drm_i915_private *dev_priv = dev->dev_private;
4251         u32 dstate = I915_READ(D_STATE);
4252
4253         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4254                 DSTATE_DOT_CLOCK_GATING;
4255         I915_WRITE(D_STATE, dstate);
4256
4257         if (IS_PINEVIEW(dev))
4258                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
4259
4260         /* IIR "flip pending" means done if this bit is set */
4261         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
4262 }
4263
4264 static void i85x_init_clock_gating(struct drm_device *dev)
4265 {
4266         struct drm_i915_private *dev_priv = dev->dev_private;
4267
4268         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4269 }
4270
4271 static void i830_init_clock_gating(struct drm_device *dev)
4272 {
4273         struct drm_i915_private *dev_priv = dev->dev_private;
4274
4275         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4276 }
4277
4278 void intel_init_clock_gating(struct drm_device *dev)
4279 {
4280         struct drm_i915_private *dev_priv = dev->dev_private;
4281
4282         dev_priv->display.init_clock_gating(dev);
4283 }
4284
4285 /**
4286  * We should only use the power well if we explicitly asked the hardware to
4287  * enable it, so check if it's enabled and also check if we've requested it to
4288  * be enabled.
4289  */
4290 bool intel_using_power_well(struct drm_device *dev)
4291 {
4292         struct drm_i915_private *dev_priv = dev->dev_private;
4293
4294         if (IS_HASWELL(dev))
4295                 return I915_READ(HSW_PWR_WELL_DRIVER) ==
4296                        (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
4297         else
4298                 return true;
4299 }
4300
4301 void intel_set_power_well(struct drm_device *dev, bool enable)
4302 {
4303         struct drm_i915_private *dev_priv = dev->dev_private;
4304         bool is_enabled, enable_requested;
4305         uint32_t tmp;
4306
4307         if (!HAS_POWER_WELL(dev))
4308                 return;
4309
4310         if (!i915_disable_power_well && !enable)
4311                 return;
4312
4313         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
4314         is_enabled = tmp & HSW_PWR_WELL_STATE;
4315         enable_requested = tmp & HSW_PWR_WELL_ENABLE;
4316
4317         if (enable) {
4318                 if (!enable_requested)
4319                         I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
4320
4321                 if (!is_enabled) {
4322                         DRM_DEBUG_KMS("Enabling power well\n");
4323                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
4324                                       HSW_PWR_WELL_STATE), 20))
4325                                 DRM_ERROR("Timeout enabling power well\n");
4326                 }
4327         } else {
4328                 if (enable_requested) {
4329                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
4330                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
4331                 }
4332         }
4333 }
4334
4335 /*
4336  * Starting with Haswell, we have a "Power Down Well" that can be turned off
4337  * when not needed anymore. We have 4 registers that can request the power well
4338  * to be enabled, and it will only be disabled if none of the registers is
4339  * requesting it to be enabled.
4340  */
4341 void intel_init_power_well(struct drm_device *dev)
4342 {
4343         struct drm_i915_private *dev_priv = dev->dev_private;
4344
4345         if (!HAS_POWER_WELL(dev))
4346                 return;
4347
4348         /* For now, we need the power well to be always enabled. */
4349         intel_set_power_well(dev, true);
4350
4351         /* We're taking over the BIOS, so clear any requests made by it since
4352          * the driver is in charge now. */
4353         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
4354                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
4355 }
4356
4357 /* Set up chip specific power management-related functions */
4358 void intel_init_pm(struct drm_device *dev)
4359 {
4360         struct drm_i915_private *dev_priv = dev->dev_private;
4361
4362         if (I915_HAS_FBC(dev)) {
4363                 if (HAS_PCH_SPLIT(dev)) {
4364                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4365                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
4366                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
4367                 } else if (IS_GM45(dev)) {
4368                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4369                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4370                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4371                 } else if (IS_CRESTLINE(dev)) {
4372                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4373                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4374                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4375                 }
4376                 /* 855GM needs testing */
4377         }
4378
4379         /* For cxsr */
4380         if (IS_PINEVIEW(dev))
4381                 i915_pineview_get_mem_freq(dev);
4382         else if (IS_GEN5(dev))
4383                 i915_ironlake_get_mem_freq(dev);
4384
4385         /* For FIFO watermark updates */
4386         if (HAS_PCH_SPLIT(dev)) {
4387                 if (IS_GEN5(dev)) {
4388                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4389                                 dev_priv->display.update_wm = ironlake_update_wm;
4390                         else {
4391                                 DRM_DEBUG_KMS("Failed to get proper latency. "
4392                                               "Disable CxSR\n");
4393                                 dev_priv->display.update_wm = NULL;
4394                         }
4395                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4396                 } else if (IS_GEN6(dev)) {
4397                         if (SNB_READ_WM0_LATENCY()) {
4398                                 dev_priv->display.update_wm = sandybridge_update_wm;
4399                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4400                         } else {
4401                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4402                                               "Disable CxSR\n");
4403                                 dev_priv->display.update_wm = NULL;
4404                         }
4405                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4406                 } else if (IS_IVYBRIDGE(dev)) {
4407                         if (SNB_READ_WM0_LATENCY()) {
4408                                 dev_priv->display.update_wm = ivybridge_update_wm;
4409                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4410                         } else {
4411                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4412                                               "Disable CxSR\n");
4413                                 dev_priv->display.update_wm = NULL;
4414                         }
4415                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
4416                 } else if (IS_HASWELL(dev)) {
4417                         if (SNB_READ_WM0_LATENCY()) {
4418                                 dev_priv->display.update_wm = sandybridge_update_wm;
4419                                 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4420                                 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
4421                         } else {
4422                                 DRM_DEBUG_KMS("Failed to read display plane latency. "
4423                                               "Disable CxSR\n");
4424                                 dev_priv->display.update_wm = NULL;
4425                         }
4426                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
4427                 } else
4428                         dev_priv->display.update_wm = NULL;
4429         } else if (IS_VALLEYVIEW(dev)) {
4430                 dev_priv->display.update_wm = valleyview_update_wm;
4431                 dev_priv->display.init_clock_gating =
4432                         valleyview_init_clock_gating;
4433         } else if (IS_PINEVIEW(dev)) {
4434                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4435                                             dev_priv->is_ddr3,
4436                                             dev_priv->fsb_freq,
4437                                             dev_priv->mem_freq)) {
4438                         DRM_INFO("failed to find known CxSR latency "
4439                                  "(found ddr%s fsb freq %d, mem freq %d), "
4440                                  "disabling CxSR\n",
4441                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
4442                                  dev_priv->fsb_freq, dev_priv->mem_freq);
4443                         /* Disable CxSR and never update its watermark again */
4444                         pineview_disable_cxsr(dev);
4445                         dev_priv->display.update_wm = NULL;
4446                 } else
4447                         dev_priv->display.update_wm = pineview_update_wm;
4448                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4449         } else if (IS_G4X(dev)) {
4450                 dev_priv->display.update_wm = g4x_update_wm;
4451                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4452         } else if (IS_GEN4(dev)) {
4453                 dev_priv->display.update_wm = i965_update_wm;
4454                 if (IS_CRESTLINE(dev))
4455                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4456                 else if (IS_BROADWATER(dev))
4457                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4458         } else if (IS_GEN3(dev)) {
4459                 dev_priv->display.update_wm = i9xx_update_wm;
4460                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4461                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4462         } else if (IS_I865G(dev)) {
4463                 dev_priv->display.update_wm = i830_update_wm;
4464                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4465                 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4466         } else if (IS_I85X(dev)) {
4467                 dev_priv->display.update_wm = i9xx_update_wm;
4468                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4469                 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4470         } else {
4471                 dev_priv->display.update_wm = i830_update_wm;
4472                 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4473                 if (IS_845G(dev))
4474                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4475                 else
4476                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4477         }
4478 }
4479
4480 static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4481 {
4482         u32 gt_thread_status_mask;
4483
4484         if (IS_HASWELL(dev_priv->dev))
4485                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4486         else
4487                 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4488
4489         /* w/a for a sporadic read returning 0 by waiting for the GT
4490          * thread to wake up.
4491          */
4492         if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4493                 DRM_ERROR("GT thread status wait timed out\n");
4494 }
4495
4496 static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4497 {
4498         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4499         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4500 }
4501
4502 static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4503 {
4504         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
4505                             FORCEWAKE_ACK_TIMEOUT_MS))
4506                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4507
4508         I915_WRITE_NOTRACE(FORCEWAKE, 1);
4509         POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4510
4511         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
4512                             FORCEWAKE_ACK_TIMEOUT_MS))
4513                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4514
4515         __gen6_gt_wait_for_thread_c0(dev_priv);
4516 }
4517
4518 static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4519 {
4520         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
4521         /* something from same cacheline, but !FORCEWAKE_MT */
4522         POSTING_READ(ECOBUS);
4523 }
4524
4525 static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4526 {
4527         u32 forcewake_ack;
4528
4529         if (IS_HASWELL(dev_priv->dev))
4530                 forcewake_ack = FORCEWAKE_ACK_HSW;
4531         else
4532                 forcewake_ack = FORCEWAKE_MT_ACK;
4533
4534         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0,
4535                             FORCEWAKE_ACK_TIMEOUT_MS))
4536                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4537
4538         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4539         /* something from same cacheline, but !FORCEWAKE_MT */
4540         POSTING_READ(ECOBUS);
4541
4542         if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL),
4543                             FORCEWAKE_ACK_TIMEOUT_MS))
4544                 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
4545
4546         __gen6_gt_wait_for_thread_c0(dev_priv);
4547 }
4548
4549 /*
4550  * Generally this is called implicitly by the register read function. However,
4551  * if some sequence requires the GT to not power down then this function should
4552  * be called at the beginning of the sequence followed by a call to
4553  * gen6_gt_force_wake_put() at the end of the sequence.
4554  */
4555 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4556 {
4557         unsigned long irqflags;
4558
4559         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4560         if (dev_priv->forcewake_count++ == 0)
4561                 dev_priv->gt.force_wake_get(dev_priv);
4562         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4563 }
4564
4565 void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4566 {
4567         u32 gtfifodbg;
4568         gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4569         if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4570              "MMIO read or write has been dropped %x\n", gtfifodbg))
4571                 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4572 }
4573
4574 static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4575 {
4576         I915_WRITE_NOTRACE(FORCEWAKE, 0);
4577         /* something from same cacheline, but !FORCEWAKE */
4578         POSTING_READ(ECOBUS);
4579         gen6_gt_check_fifodbg(dev_priv);
4580 }
4581
4582 static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4583 {
4584         I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4585         /* something from same cacheline, but !FORCEWAKE_MT */
4586         POSTING_READ(ECOBUS);
4587         gen6_gt_check_fifodbg(dev_priv);
4588 }
4589
4590 /*
4591  * see gen6_gt_force_wake_get()
4592  */
4593 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4594 {
4595         unsigned long irqflags;
4596
4597         spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4598         if (--dev_priv->forcewake_count == 0)
4599                 dev_priv->gt.force_wake_put(dev_priv);
4600         spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4601 }
4602
4603 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4604 {
4605         int ret = 0;
4606
4607         if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4608                 int loop = 500;
4609                 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4610                 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4611                         udelay(10);
4612                         fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4613                 }
4614                 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4615                         ++ret;
4616                 dev_priv->gt_fifo_count = fifo;
4617         }
4618         dev_priv->gt_fifo_count--;
4619
4620         return ret;
4621 }
4622
4623 static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4624 {
4625         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
4626         /* something from same cacheline, but !FORCEWAKE_VLV */
4627         POSTING_READ(FORCEWAKE_ACK_VLV);
4628 }
4629
4630 static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4631 {
4632         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
4633                             FORCEWAKE_ACK_TIMEOUT_MS))
4634                 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
4635
4636         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4637         I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4638                            _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
4639
4640         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
4641                             FORCEWAKE_ACK_TIMEOUT_MS))
4642                 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
4643
4644         if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
4645                              FORCEWAKE_KERNEL),
4646                             FORCEWAKE_ACK_TIMEOUT_MS))
4647                 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
4648
4649         __gen6_gt_wait_for_thread_c0(dev_priv);
4650 }
4651
4652 static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4653 {
4654         I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4655         I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4656                            _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4657         /* The below doubles as a POSTING_READ */
4658         gen6_gt_check_fifodbg(dev_priv);
4659 }
4660
4661 void intel_gt_reset(struct drm_device *dev)
4662 {
4663         struct drm_i915_private *dev_priv = dev->dev_private;
4664
4665         if (IS_VALLEYVIEW(dev)) {
4666                 vlv_force_wake_reset(dev_priv);
4667         } else if (INTEL_INFO(dev)->gen >= 6) {
4668                 __gen6_gt_force_wake_reset(dev_priv);
4669                 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4670                         __gen6_gt_force_wake_mt_reset(dev_priv);
4671         }
4672 }
4673
4674 void intel_gt_init(struct drm_device *dev)
4675 {
4676         struct drm_i915_private *dev_priv = dev->dev_private;
4677
4678         spin_lock_init(&dev_priv->gt_lock);
4679
4680         intel_gt_reset(dev);
4681
4682         if (IS_VALLEYVIEW(dev)) {
4683                 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4684                 dev_priv->gt.force_wake_put = vlv_force_wake_put;
4685         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4686                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4687                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4688         } else if (IS_GEN6(dev)) {
4689                 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4690                 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
4691         }
4692         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4693                           intel_gen6_powersave_work);
4694 }
4695
4696 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4697 {
4698         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4699
4700         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4701                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4702                 return -EAGAIN;
4703         }
4704
4705         I915_WRITE(GEN6_PCODE_DATA, *val);
4706         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4707
4708         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4709                      500)) {
4710                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4711                 return -ETIMEDOUT;
4712         }
4713
4714         *val = I915_READ(GEN6_PCODE_DATA);
4715         I915_WRITE(GEN6_PCODE_DATA, 0);
4716
4717         return 0;
4718 }
4719
4720 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4721 {
4722         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4723
4724         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4725                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4726                 return -EAGAIN;
4727         }
4728
4729         I915_WRITE(GEN6_PCODE_DATA, val);
4730         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4731
4732         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4733                      500)) {
4734                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4735                 return -ETIMEDOUT;
4736         }
4737
4738         I915_WRITE(GEN6_PCODE_DATA, 0);
4739
4740         return 0;
4741 }
4742
4743 static int vlv_punit_rw(struct drm_i915_private *dev_priv, u32 port, u8 opcode,
4744                         u8 addr, u32 *val)
4745 {
4746         u32 cmd, devfn, be, bar;
4747
4748         bar = 0;
4749         be = 0xf;
4750         devfn = PCI_DEVFN(2, 0);
4751
4752         cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
4753                 (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
4754                 (bar << IOSF_BAR_SHIFT);
4755
4756         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4757
4758         if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
4759                 DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n",
4760                                  opcode == PUNIT_OPCODE_REG_READ ?
4761                                  "read" : "write");
4762                 return -EAGAIN;
4763         }
4764
4765         I915_WRITE(VLV_IOSF_ADDR, addr);
4766         if (opcode == PUNIT_OPCODE_REG_WRITE)
4767                 I915_WRITE(VLV_IOSF_DATA, *val);
4768         I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
4769
4770         if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
4771                      5)) {
4772                 DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n",
4773                           opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
4774                           addr);
4775                 return -ETIMEDOUT;
4776         }
4777
4778         if (opcode == PUNIT_OPCODE_REG_READ)
4779                 *val = I915_READ(VLV_IOSF_DATA);
4780         I915_WRITE(VLV_IOSF_DATA, 0);
4781
4782         return 0;
4783 }
4784
4785 int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
4786 {
4787         return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_READ,
4788                             addr, val);
4789 }
4790
4791 int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
4792 {
4793         return vlv_punit_rw(dev_priv, IOSF_PORT_PUNIT, PUNIT_OPCODE_REG_WRITE,
4794                             addr, &val);
4795 }
4796
4797 int valleyview_nc_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
4798 {
4799         return vlv_punit_rw(dev_priv, IOSF_PORT_NC, PUNIT_OPCODE_REG_READ,
4800                             addr, val);
4801 }
4802
4803 int vlv_gpu_freq(int ddr_freq, int val)
4804 {
4805         int mult, base;
4806
4807         switch (ddr_freq) {
4808         case 800:
4809                 mult = 20;
4810                 base = 120;
4811                 break;
4812         case 1066:
4813                 mult = 22;
4814                 base = 133;
4815                 break;
4816         case 1333:
4817                 mult = 21;
4818                 base = 125;
4819                 break;
4820         default:
4821                 return -1;
4822         }
4823
4824         return ((val - 0xbd) * mult) + base;
4825 }
4826
4827 int vlv_freq_opcode(int ddr_freq, int val)
4828 {
4829         int mult, base;
4830
4831         switch (ddr_freq) {
4832         case 800:
4833                 mult = 20;
4834                 base = 120;
4835                 break;
4836         case 1066:
4837                 mult = 22;
4838                 base = 133;
4839                 break;
4840         case 1333:
4841                 mult = 21;
4842                 base = 125;
4843                 break;
4844         default:
4845                 return -1;
4846         }
4847
4848         val /= mult;
4849         val -= base / mult;
4850         val += 0xbd;
4851
4852         if (val > 0xea)
4853                 val = 0xea;
4854
4855         return val;
4856 }
4857