2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include <linux/export.h>
32 #include <drm/drm_crtc.h>
33 #include <drm/drm_crtc_helper.h>
34 #include <drm/drm_edid.h>
35 #include "intel_drv.h"
36 #include <drm/i915_drm.h>
39 #define DP_RECEIVER_CAP_SIZE 0xf
40 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
44 * @intel_dp: DP struct
46 * If a CPU or PCH DP output is attached to an eDP panel, this function
47 * will return true, and false otherwise.
49 static bool is_edp(struct intel_dp *intel_dp)
51 return intel_dp->base.type == INTEL_OUTPUT_EDP;
55 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
56 * @intel_dp: DP struct
58 * Returns true if the given DP struct corresponds to a PCH DP port attached
59 * to an eDP panel, false otherwise. Helpful for determining whether we
60 * may need FDI resources for a given DP output or not.
62 static bool is_pch_edp(struct intel_dp *intel_dp)
64 return intel_dp->is_pch_edp;
68 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
69 * @intel_dp: DP struct
71 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 static bool is_cpu_edp(struct intel_dp *intel_dp)
75 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
78 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
80 return container_of(intel_attached_encoder(connector),
81 struct intel_dp, base);
85 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
86 * @encoder: DRM encoder
88 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
91 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
93 struct intel_dp *intel_dp;
98 intel_dp = enc_to_intel_dp(encoder);
100 return is_pch_edp(intel_dp);
103 static void intel_dp_link_down(struct intel_dp *intel_dp);
106 intel_edp_link_config(struct intel_encoder *intel_encoder,
107 int *lane_num, int *link_bw)
109 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
111 *lane_num = intel_dp->lane_count;
112 if (intel_dp->link_bw == DP_LINK_BW_1_62)
114 else if (intel_dp->link_bw == DP_LINK_BW_2_7)
119 intel_edp_target_clock(struct intel_encoder *intel_encoder,
120 struct drm_display_mode *mode)
122 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
123 struct intel_connector *intel_connector = intel_dp->attached_connector;
125 if (intel_connector->panel.fixed_mode)
126 return intel_connector->panel.fixed_mode->clock;
132 intel_dp_max_lane_count(struct intel_dp *intel_dp)
134 int max_lane_count = intel_dp->dpcd[DP_MAX_LANE_COUNT] & 0x1f;
135 switch (max_lane_count) {
136 case 1: case 2: case 4:
141 return max_lane_count;
145 intel_dp_max_link_bw(struct intel_dp *intel_dp)
147 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
149 switch (max_link_bw) {
150 case DP_LINK_BW_1_62:
154 max_link_bw = DP_LINK_BW_1_62;
161 intel_dp_link_clock(uint8_t link_bw)
163 if (link_bw == DP_LINK_BW_2_7)
170 * The units on the numbers in the next two are... bizarre. Examples will
171 * make it clearer; this one parallels an example in the eDP spec.
173 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
175 * 270000 * 1 * 8 / 10 == 216000
177 * The actual data capacity of that configuration is 2.16Gbit/s, so the
178 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
179 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
180 * 119000. At 18bpp that's 2142000 kilobits per second.
182 * Thus the strange-looking division by 10 in intel_dp_link_required, to
183 * get the result in decakilobits instead of kilobits.
187 intel_dp_link_required(int pixel_clock, int bpp)
189 return (pixel_clock * bpp + 9) / 10;
193 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
195 return (max_link_clock * max_lanes * 8) / 10;
199 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
200 struct drm_display_mode *mode,
203 int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
204 int max_lanes = intel_dp_max_lane_count(intel_dp);
205 int max_rate, mode_rate;
207 mode_rate = intel_dp_link_required(mode->clock, 24);
208 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
210 if (mode_rate > max_rate) {
211 mode_rate = intel_dp_link_required(mode->clock, 18);
212 if (mode_rate > max_rate)
217 |= INTEL_MODE_DP_FORCE_6BPC;
226 intel_dp_mode_valid(struct drm_connector *connector,
227 struct drm_display_mode *mode)
229 struct intel_dp *intel_dp = intel_attached_dp(connector);
230 struct intel_connector *intel_connector = to_intel_connector(connector);
231 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
233 if (is_edp(intel_dp) && fixed_mode) {
234 if (mode->hdisplay > fixed_mode->hdisplay)
237 if (mode->vdisplay > fixed_mode->vdisplay)
241 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
242 return MODE_CLOCK_HIGH;
244 if (mode->clock < 10000)
245 return MODE_CLOCK_LOW;
247 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
248 return MODE_H_ILLEGAL;
254 pack_aux(uint8_t *src, int src_bytes)
261 for (i = 0; i < src_bytes; i++)
262 v |= ((uint32_t) src[i]) << ((3-i) * 8);
267 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
272 for (i = 0; i < dst_bytes; i++)
273 dst[i] = src >> ((3-i) * 8);
276 /* hrawclock is 1/4 the FSB frequency */
278 intel_hrawclk(struct drm_device *dev)
280 struct drm_i915_private *dev_priv = dev->dev_private;
283 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
284 if (IS_VALLEYVIEW(dev))
287 clkcfg = I915_READ(CLKCFG);
288 switch (clkcfg & CLKCFG_FSB_MASK) {
297 case CLKCFG_FSB_1067:
299 case CLKCFG_FSB_1333:
301 /* these two are just a guess; one of them might be right */
302 case CLKCFG_FSB_1600:
303 case CLKCFG_FSB_1600_ALT:
310 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
312 struct drm_device *dev = intel_dp->base.base.dev;
313 struct drm_i915_private *dev_priv = dev->dev_private;
315 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
318 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
320 struct drm_device *dev = intel_dp->base.base.dev;
321 struct drm_i915_private *dev_priv = dev->dev_private;
323 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
327 intel_dp_check_edp(struct intel_dp *intel_dp)
329 struct drm_device *dev = intel_dp->base.base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private;
332 if (!is_edp(intel_dp))
334 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
335 WARN(1, "eDP powered off while attempting aux channel communication.\n");
336 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
337 I915_READ(PCH_PP_STATUS),
338 I915_READ(PCH_PP_CONTROL));
343 intel_dp_aux_ch(struct intel_dp *intel_dp,
344 uint8_t *send, int send_bytes,
345 uint8_t *recv, int recv_size)
347 uint32_t output_reg = intel_dp->output_reg;
348 struct drm_device *dev = intel_dp->base.base.dev;
349 struct drm_i915_private *dev_priv = dev->dev_private;
350 uint32_t ch_ctl = output_reg + 0x10;
351 uint32_t ch_data = ch_ctl + 4;
355 uint32_t aux_clock_divider;
358 if (IS_HASWELL(dev)) {
359 switch (intel_dp->port) {
361 ch_ctl = DPA_AUX_CH_CTL;
362 ch_data = DPA_AUX_CH_DATA1;
365 ch_ctl = PCH_DPB_AUX_CH_CTL;
366 ch_data = PCH_DPB_AUX_CH_DATA1;
369 ch_ctl = PCH_DPC_AUX_CH_CTL;
370 ch_data = PCH_DPC_AUX_CH_DATA1;
373 ch_ctl = PCH_DPD_AUX_CH_CTL;
374 ch_data = PCH_DPD_AUX_CH_DATA1;
381 intel_dp_check_edp(intel_dp);
382 /* The clock divider is based off the hrawclk,
383 * and would like to run at 2MHz. So, take the
384 * hrawclk value and divide by 2 and use that
386 * Note that PCH attached eDP panels should use a 125MHz input
389 if (is_cpu_edp(intel_dp)) {
390 if (IS_VALLEYVIEW(dev))
391 aux_clock_divider = 100;
392 else if (IS_GEN6(dev) || IS_GEN7(dev))
393 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
395 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
396 } else if (HAS_PCH_SPLIT(dev))
397 aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */
399 aux_clock_divider = intel_hrawclk(dev) / 2;
406 /* Try to wait for any previous AUX channel activity */
407 for (try = 0; try < 3; try++) {
408 status = I915_READ(ch_ctl);
409 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
415 WARN(1, "dp_aux_ch not started status 0x%08x\n",
420 /* Must try at least 3 times according to DP spec */
421 for (try = 0; try < 5; try++) {
422 /* Load the send data into the aux channel data registers */
423 for (i = 0; i < send_bytes; i += 4)
424 I915_WRITE(ch_data + i,
425 pack_aux(send + i, send_bytes - i));
427 /* Send the command and wait for it to complete */
429 DP_AUX_CH_CTL_SEND_BUSY |
430 DP_AUX_CH_CTL_TIME_OUT_400us |
431 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
432 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
433 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
435 DP_AUX_CH_CTL_TIME_OUT_ERROR |
436 DP_AUX_CH_CTL_RECEIVE_ERROR);
438 status = I915_READ(ch_ctl);
439 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
444 /* Clear done status and any errors */
448 DP_AUX_CH_CTL_TIME_OUT_ERROR |
449 DP_AUX_CH_CTL_RECEIVE_ERROR);
451 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
452 DP_AUX_CH_CTL_RECEIVE_ERROR))
454 if (status & DP_AUX_CH_CTL_DONE)
458 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
459 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
463 /* Check for timeout or receive error.
464 * Timeouts occur when the sink is not connected
466 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
467 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
471 /* Timeouts occur when the device isn't connected, so they're
472 * "normal" -- don't fill the kernel log with these */
473 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
474 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
478 /* Unload any bytes sent back from the other side */
479 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
480 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
481 if (recv_bytes > recv_size)
482 recv_bytes = recv_size;
484 for (i = 0; i < recv_bytes; i += 4)
485 unpack_aux(I915_READ(ch_data + i),
486 recv + i, recv_bytes - i);
491 /* Write data to the aux channel in native mode */
493 intel_dp_aux_native_write(struct intel_dp *intel_dp,
494 uint16_t address, uint8_t *send, int send_bytes)
501 intel_dp_check_edp(intel_dp);
504 msg[0] = AUX_NATIVE_WRITE << 4;
505 msg[1] = address >> 8;
506 msg[2] = address & 0xff;
507 msg[3] = send_bytes - 1;
508 memcpy(&msg[4], send, send_bytes);
509 msg_bytes = send_bytes + 4;
511 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
514 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
516 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
524 /* Write a single byte to the aux channel in native mode */
526 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
527 uint16_t address, uint8_t byte)
529 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
532 /* read bytes from a native aux channel */
534 intel_dp_aux_native_read(struct intel_dp *intel_dp,
535 uint16_t address, uint8_t *recv, int recv_bytes)
544 intel_dp_check_edp(intel_dp);
545 msg[0] = AUX_NATIVE_READ << 4;
546 msg[1] = address >> 8;
547 msg[2] = address & 0xff;
548 msg[3] = recv_bytes - 1;
551 reply_bytes = recv_bytes + 1;
554 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
561 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
562 memcpy(recv, reply + 1, ret - 1);
565 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
573 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
574 uint8_t write_byte, uint8_t *read_byte)
576 struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
577 struct intel_dp *intel_dp = container_of(adapter,
580 uint16_t address = algo_data->address;
588 intel_dp_check_edp(intel_dp);
589 /* Set up the command byte */
590 if (mode & MODE_I2C_READ)
591 msg[0] = AUX_I2C_READ << 4;
593 msg[0] = AUX_I2C_WRITE << 4;
595 if (!(mode & MODE_I2C_STOP))
596 msg[0] |= AUX_I2C_MOT << 4;
598 msg[1] = address >> 8;
619 for (retry = 0; retry < 5; retry++) {
620 ret = intel_dp_aux_ch(intel_dp,
624 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
628 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
629 case AUX_NATIVE_REPLY_ACK:
630 /* I2C-over-AUX Reply field is only valid
631 * when paired with AUX ACK.
634 case AUX_NATIVE_REPLY_NACK:
635 DRM_DEBUG_KMS("aux_ch native nack\n");
637 case AUX_NATIVE_REPLY_DEFER:
641 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
646 switch (reply[0] & AUX_I2C_REPLY_MASK) {
647 case AUX_I2C_REPLY_ACK:
648 if (mode == MODE_I2C_READ) {
649 *read_byte = reply[1];
651 return reply_bytes - 1;
652 case AUX_I2C_REPLY_NACK:
653 DRM_DEBUG_KMS("aux_i2c nack\n");
655 case AUX_I2C_REPLY_DEFER:
656 DRM_DEBUG_KMS("aux_i2c defer\n");
660 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
665 DRM_ERROR("too many retries, giving up\n");
669 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp);
670 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
673 intel_dp_i2c_init(struct intel_dp *intel_dp,
674 struct intel_connector *intel_connector, const char *name)
678 DRM_DEBUG_KMS("i2c_init %s\n", name);
679 intel_dp->algo.running = false;
680 intel_dp->algo.address = 0;
681 intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
683 memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
684 intel_dp->adapter.owner = THIS_MODULE;
685 intel_dp->adapter.class = I2C_CLASS_DDC;
686 strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
687 intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
688 intel_dp->adapter.algo_data = &intel_dp->algo;
689 intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
691 ironlake_edp_panel_vdd_on(intel_dp);
692 ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
693 ironlake_edp_panel_vdd_off(intel_dp, false);
698 intel_dp_mode_fixup(struct drm_encoder *encoder,
699 const struct drm_display_mode *mode,
700 struct drm_display_mode *adjusted_mode)
702 struct drm_device *dev = encoder->dev;
703 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
704 struct intel_connector *intel_connector = intel_dp->attached_connector;
705 int lane_count, clock;
706 int max_lane_count = intel_dp_max_lane_count(intel_dp);
707 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
709 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
711 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
712 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
714 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
715 mode, adjusted_mode);
718 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
721 DRM_DEBUG_KMS("DP link computation with max lane count %i "
722 "max bw %02x pixel clock %iKHz\n",
723 max_lane_count, bws[max_clock], adjusted_mode->clock);
725 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
728 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
729 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
731 for (clock = 0; clock <= max_clock; clock++) {
732 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
733 int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
735 if (mode_rate <= link_avail) {
736 intel_dp->link_bw = bws[clock];
737 intel_dp->lane_count = lane_count;
738 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
739 DRM_DEBUG_KMS("DP link bw %02x lane "
740 "count %d clock %d bpp %d\n",
741 intel_dp->link_bw, intel_dp->lane_count,
742 adjusted_mode->clock, bpp);
743 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
744 mode_rate, link_avail);
753 struct intel_dp_m_n {
762 intel_reduce_ratio(uint32_t *num, uint32_t *den)
764 while (*num > 0xffffff || *den > 0xffffff) {
771 intel_dp_compute_m_n(int bpp,
775 struct intel_dp_m_n *m_n)
778 m_n->gmch_m = (pixel_clock * bpp) >> 3;
779 m_n->gmch_n = link_clock * nlanes;
780 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
781 m_n->link_m = pixel_clock;
782 m_n->link_n = link_clock;
783 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
787 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
788 struct drm_display_mode *adjusted_mode)
790 struct drm_device *dev = crtc->dev;
791 struct intel_encoder *encoder;
792 struct drm_i915_private *dev_priv = dev->dev_private;
793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
795 struct intel_dp_m_n m_n;
796 int pipe = intel_crtc->pipe;
799 * Find the lane count in the intel_encoder private
801 for_each_encoder_on_crtc(dev, crtc, encoder) {
802 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
804 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
805 intel_dp->base.type == INTEL_OUTPUT_EDP)
807 lane_count = intel_dp->lane_count;
813 * Compute the GMCH and Link ratios. The '3' here is
814 * the number of bytes_per_pixel post-LUT, which we always
815 * set up for 8-bits of R/G/B, or 3 bytes total.
817 intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
818 mode->clock, adjusted_mode->clock, &m_n);
820 if (IS_HASWELL(dev)) {
821 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
822 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
823 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
824 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
825 } else if (HAS_PCH_SPLIT(dev)) {
826 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
827 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
828 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
829 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
830 } else if (IS_VALLEYVIEW(dev)) {
831 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
832 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
833 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
834 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
836 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
837 TU_SIZE(m_n.tu) | m_n.gmch_m);
838 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
839 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
840 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
844 void intel_dp_init_link_config(struct intel_dp *intel_dp)
846 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
847 intel_dp->link_configuration[0] = intel_dp->link_bw;
848 intel_dp->link_configuration[1] = intel_dp->lane_count;
849 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
851 * Check for DPCD version > 1.1 and enhanced framing support
853 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
854 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
855 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
860 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
861 struct drm_display_mode *adjusted_mode)
863 struct drm_device *dev = encoder->dev;
864 struct drm_i915_private *dev_priv = dev->dev_private;
865 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
866 struct drm_crtc *crtc = intel_dp->base.base.crtc;
867 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
870 * There are four kinds of DP registers:
877 * IBX PCH and CPU are the same for almost everything,
878 * except that the CPU DP PLL is configured in this
881 * CPT PCH is quite different, having many bits moved
882 * to the TRANS_DP_CTL register instead. That
883 * configuration happens (oddly) in ironlake_pch_enable
886 /* Preserve the BIOS-computed detected bit. This is
887 * supposed to be read-only.
889 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
891 /* Handle DP bits in common between all three register formats */
892 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
894 switch (intel_dp->lane_count) {
896 intel_dp->DP |= DP_PORT_WIDTH_1;
899 intel_dp->DP |= DP_PORT_WIDTH_2;
902 intel_dp->DP |= DP_PORT_WIDTH_4;
905 if (intel_dp->has_audio) {
906 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
907 pipe_name(intel_crtc->pipe));
908 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
909 intel_write_eld(encoder, adjusted_mode);
912 intel_dp_init_link_config(intel_dp);
914 /* Split out the IBX/CPU vs CPT settings */
916 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
917 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
918 intel_dp->DP |= DP_SYNC_HS_HIGH;
919 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
920 intel_dp->DP |= DP_SYNC_VS_HIGH;
921 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
923 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
924 intel_dp->DP |= DP_ENHANCED_FRAMING;
926 intel_dp->DP |= intel_crtc->pipe << 29;
928 /* don't miss out required setting for eDP */
929 if (adjusted_mode->clock < 200000)
930 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
932 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
933 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
934 intel_dp->DP |= intel_dp->color_range;
936 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
937 intel_dp->DP |= DP_SYNC_HS_HIGH;
938 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
939 intel_dp->DP |= DP_SYNC_VS_HIGH;
940 intel_dp->DP |= DP_LINK_TRAIN_OFF;
942 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
943 intel_dp->DP |= DP_ENHANCED_FRAMING;
945 if (intel_crtc->pipe == 1)
946 intel_dp->DP |= DP_PIPEB_SELECT;
948 if (is_cpu_edp(intel_dp)) {
949 /* don't miss out required setting for eDP */
950 if (adjusted_mode->clock < 200000)
951 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
953 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
956 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
960 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
961 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
963 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
964 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
966 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
967 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
969 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
973 struct drm_device *dev = intel_dp->base.base.dev;
974 struct drm_i915_private *dev_priv = dev->dev_private;
976 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
978 I915_READ(PCH_PP_STATUS),
979 I915_READ(PCH_PP_CONTROL));
981 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
982 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
983 I915_READ(PCH_PP_STATUS),
984 I915_READ(PCH_PP_CONTROL));
988 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
990 DRM_DEBUG_KMS("Wait for panel power on\n");
991 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
994 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
996 DRM_DEBUG_KMS("Wait for panel power off time\n");
997 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1000 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1002 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1003 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1007 /* Read the current pp_control value, unlocking the register if it
1011 static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1013 u32 control = I915_READ(PCH_PP_CONTROL);
1015 control &= ~PANEL_UNLOCK_MASK;
1016 control |= PANEL_UNLOCK_REGS;
1020 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1022 struct drm_device *dev = intel_dp->base.base.dev;
1023 struct drm_i915_private *dev_priv = dev->dev_private;
1026 if (!is_edp(intel_dp))
1028 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1030 WARN(intel_dp->want_panel_vdd,
1031 "eDP VDD already requested on\n");
1033 intel_dp->want_panel_vdd = true;
1035 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1036 DRM_DEBUG_KMS("eDP VDD already on\n");
1040 if (!ironlake_edp_have_panel_power(intel_dp))
1041 ironlake_wait_panel_power_cycle(intel_dp);
1043 pp = ironlake_get_pp_control(dev_priv);
1044 pp |= EDP_FORCE_VDD;
1045 I915_WRITE(PCH_PP_CONTROL, pp);
1046 POSTING_READ(PCH_PP_CONTROL);
1047 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1048 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1051 * If the panel wasn't on, delay before accessing aux channel
1053 if (!ironlake_edp_have_panel_power(intel_dp)) {
1054 DRM_DEBUG_KMS("eDP was not running\n");
1055 msleep(intel_dp->panel_power_up_delay);
1059 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1061 struct drm_device *dev = intel_dp->base.base.dev;
1062 struct drm_i915_private *dev_priv = dev->dev_private;
1065 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1066 pp = ironlake_get_pp_control(dev_priv);
1067 pp &= ~EDP_FORCE_VDD;
1068 I915_WRITE(PCH_PP_CONTROL, pp);
1069 POSTING_READ(PCH_PP_CONTROL);
1071 /* Make sure sequencer is idle before allowing subsequent activity */
1072 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1073 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1075 msleep(intel_dp->panel_power_down_delay);
1079 static void ironlake_panel_vdd_work(struct work_struct *__work)
1081 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1082 struct intel_dp, panel_vdd_work);
1083 struct drm_device *dev = intel_dp->base.base.dev;
1085 mutex_lock(&dev->mode_config.mutex);
1086 ironlake_panel_vdd_off_sync(intel_dp);
1087 mutex_unlock(&dev->mode_config.mutex);
1090 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1092 if (!is_edp(intel_dp))
1095 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1096 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1098 intel_dp->want_panel_vdd = false;
1101 ironlake_panel_vdd_off_sync(intel_dp);
1104 * Queue the timer to fire a long
1105 * time from now (relative to the power down delay)
1106 * to keep the panel power up across a sequence of operations
1108 schedule_delayed_work(&intel_dp->panel_vdd_work,
1109 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1113 static void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1115 struct drm_device *dev = intel_dp->base.base.dev;
1116 struct drm_i915_private *dev_priv = dev->dev_private;
1119 if (!is_edp(intel_dp))
1122 DRM_DEBUG_KMS("Turn eDP power on\n");
1124 if (ironlake_edp_have_panel_power(intel_dp)) {
1125 DRM_DEBUG_KMS("eDP power already on\n");
1129 ironlake_wait_panel_power_cycle(intel_dp);
1131 pp = ironlake_get_pp_control(dev_priv);
1133 /* ILK workaround: disable reset around power sequence */
1134 pp &= ~PANEL_POWER_RESET;
1135 I915_WRITE(PCH_PP_CONTROL, pp);
1136 POSTING_READ(PCH_PP_CONTROL);
1139 pp |= POWER_TARGET_ON;
1141 pp |= PANEL_POWER_RESET;
1143 I915_WRITE(PCH_PP_CONTROL, pp);
1144 POSTING_READ(PCH_PP_CONTROL);
1146 ironlake_wait_panel_on(intel_dp);
1149 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1150 I915_WRITE(PCH_PP_CONTROL, pp);
1151 POSTING_READ(PCH_PP_CONTROL);
1155 static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1157 struct drm_device *dev = intel_dp->base.base.dev;
1158 struct drm_i915_private *dev_priv = dev->dev_private;
1161 if (!is_edp(intel_dp))
1164 DRM_DEBUG_KMS("Turn eDP power off\n");
1166 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1168 pp = ironlake_get_pp_control(dev_priv);
1169 /* We need to switch off panel power _and_ force vdd, for otherwise some
1170 * panels get very unhappy and cease to work. */
1171 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1172 I915_WRITE(PCH_PP_CONTROL, pp);
1173 POSTING_READ(PCH_PP_CONTROL);
1175 intel_dp->want_panel_vdd = false;
1177 ironlake_wait_panel_off(intel_dp);
1180 static void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1182 struct drm_device *dev = intel_dp->base.base.dev;
1183 struct drm_i915_private *dev_priv = dev->dev_private;
1186 if (!is_edp(intel_dp))
1189 DRM_DEBUG_KMS("\n");
1191 * If we enable the backlight right away following a panel power
1192 * on, we may see slight flicker as the panel syncs with the eDP
1193 * link. So delay a bit to make sure the image is solid before
1194 * allowing it to appear.
1196 msleep(intel_dp->backlight_on_delay);
1197 pp = ironlake_get_pp_control(dev_priv);
1198 pp |= EDP_BLC_ENABLE;
1199 I915_WRITE(PCH_PP_CONTROL, pp);
1200 POSTING_READ(PCH_PP_CONTROL);
1203 static void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1205 struct drm_device *dev = intel_dp->base.base.dev;
1206 struct drm_i915_private *dev_priv = dev->dev_private;
1209 if (!is_edp(intel_dp))
1212 DRM_DEBUG_KMS("\n");
1213 pp = ironlake_get_pp_control(dev_priv);
1214 pp &= ~EDP_BLC_ENABLE;
1215 I915_WRITE(PCH_PP_CONTROL, pp);
1216 POSTING_READ(PCH_PP_CONTROL);
1217 msleep(intel_dp->backlight_off_delay);
1220 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1222 struct drm_device *dev = intel_dp->base.base.dev;
1223 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1224 struct drm_i915_private *dev_priv = dev->dev_private;
1227 assert_pipe_disabled(dev_priv,
1228 to_intel_crtc(crtc)->pipe);
1230 DRM_DEBUG_KMS("\n");
1231 dpa_ctl = I915_READ(DP_A);
1232 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1233 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1235 /* We don't adjust intel_dp->DP while tearing down the link, to
1236 * facilitate link retraining (e.g. after hotplug). Hence clear all
1237 * enable bits here to ensure that we don't enable too much. */
1238 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1239 intel_dp->DP |= DP_PLL_ENABLE;
1240 I915_WRITE(DP_A, intel_dp->DP);
1245 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1247 struct drm_device *dev = intel_dp->base.base.dev;
1248 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1249 struct drm_i915_private *dev_priv = dev->dev_private;
1252 assert_pipe_disabled(dev_priv,
1253 to_intel_crtc(crtc)->pipe);
1255 dpa_ctl = I915_READ(DP_A);
1256 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1257 "dp pll off, should be on\n");
1258 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1260 /* We can't rely on the value tracked for the DP register in
1261 * intel_dp->DP because link_down must not change that (otherwise link
1262 * re-training will fail. */
1263 dpa_ctl &= ~DP_PLL_ENABLE;
1264 I915_WRITE(DP_A, dpa_ctl);
1269 /* If the sink supports it, try to set the power state appropriately */
1270 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1274 /* Should have a valid DPCD by this point */
1275 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1278 if (mode != DRM_MODE_DPMS_ON) {
1279 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1282 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1285 * When turning on, we need to retry for 1ms to give the sink
1288 for (i = 0; i < 3; i++) {
1289 ret = intel_dp_aux_native_write_1(intel_dp,
1299 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1302 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1303 struct drm_device *dev = encoder->base.dev;
1304 struct drm_i915_private *dev_priv = dev->dev_private;
1305 u32 tmp = I915_READ(intel_dp->output_reg);
1307 if (!(tmp & DP_PORT_EN))
1310 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1311 *pipe = PORT_TO_PIPE_CPT(tmp);
1312 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1313 *pipe = PORT_TO_PIPE(tmp);
1319 switch (intel_dp->output_reg) {
1321 trans_sel = TRANS_DP_PORT_SEL_B;
1324 trans_sel = TRANS_DP_PORT_SEL_C;
1327 trans_sel = TRANS_DP_PORT_SEL_D;
1334 trans_dp = I915_READ(TRANS_DP_CTL(i));
1335 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1342 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg);
1347 static void intel_disable_dp(struct intel_encoder *encoder)
1349 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1351 /* Make sure the panel is off before trying to change the mode. But also
1352 * ensure that we have vdd while we switch off the panel. */
1353 ironlake_edp_panel_vdd_on(intel_dp);
1354 ironlake_edp_backlight_off(intel_dp);
1355 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1356 ironlake_edp_panel_off(intel_dp);
1358 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1359 if (!is_cpu_edp(intel_dp))
1360 intel_dp_link_down(intel_dp);
1363 static void intel_post_disable_dp(struct intel_encoder *encoder)
1365 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1367 if (is_cpu_edp(intel_dp)) {
1368 intel_dp_link_down(intel_dp);
1369 ironlake_edp_pll_off(intel_dp);
1373 static void intel_enable_dp(struct intel_encoder *encoder)
1375 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1376 struct drm_device *dev = encoder->base.dev;
1377 struct drm_i915_private *dev_priv = dev->dev_private;
1378 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1380 if (WARN_ON(dp_reg & DP_PORT_EN))
1383 ironlake_edp_panel_vdd_on(intel_dp);
1384 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1385 intel_dp_start_link_train(intel_dp);
1386 ironlake_edp_panel_on(intel_dp);
1387 ironlake_edp_panel_vdd_off(intel_dp, true);
1388 intel_dp_complete_link_train(intel_dp);
1389 ironlake_edp_backlight_on(intel_dp);
1392 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1394 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1396 if (is_cpu_edp(intel_dp))
1397 ironlake_edp_pll_on(intel_dp);
1401 * Native read with retry for link status and receiver capability reads for
1402 * cases where the sink may still be asleep.
1405 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1406 uint8_t *recv, int recv_bytes)
1411 * Sinks are *supposed* to come up within 1ms from an off state,
1412 * but we're also supposed to retry 3 times per the spec.
1414 for (i = 0; i < 3; i++) {
1415 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1417 if (ret == recv_bytes)
1426 * Fetch AUX CH registers 0x202 - 0x207 which contain
1427 * link status information
1430 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1432 return intel_dp_aux_native_read_retry(intel_dp,
1435 DP_LINK_STATUS_SIZE);
1439 intel_get_adjust_request_voltage(uint8_t adjust_request[2],
1442 int s = ((lane & 1) ?
1443 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1444 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1445 uint8_t l = adjust_request[lane>>1];
1447 return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1451 intel_get_adjust_request_pre_emphasis(uint8_t adjust_request[2],
1454 int s = ((lane & 1) ?
1455 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1456 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1457 uint8_t l = adjust_request[lane>>1];
1459 return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1464 static char *voltage_names[] = {
1465 "0.4V", "0.6V", "0.8V", "1.2V"
1467 static char *pre_emph_names[] = {
1468 "0dB", "3.5dB", "6dB", "9.5dB"
1470 static char *link_train_names[] = {
1471 "pattern 1", "pattern 2", "idle", "off"
1476 * These are source-specific values; current Intel hardware supports
1477 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1481 intel_dp_voltage_max(struct intel_dp *intel_dp)
1483 struct drm_device *dev = intel_dp->base.base.dev;
1485 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1486 return DP_TRAIN_VOLTAGE_SWING_800;
1487 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1488 return DP_TRAIN_VOLTAGE_SWING_1200;
1490 return DP_TRAIN_VOLTAGE_SWING_800;
1494 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1496 struct drm_device *dev = intel_dp->base.base.dev;
1498 if (IS_HASWELL(dev)) {
1499 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1500 case DP_TRAIN_VOLTAGE_SWING_400:
1501 return DP_TRAIN_PRE_EMPHASIS_9_5;
1502 case DP_TRAIN_VOLTAGE_SWING_600:
1503 return DP_TRAIN_PRE_EMPHASIS_6;
1504 case DP_TRAIN_VOLTAGE_SWING_800:
1505 return DP_TRAIN_PRE_EMPHASIS_3_5;
1506 case DP_TRAIN_VOLTAGE_SWING_1200:
1508 return DP_TRAIN_PRE_EMPHASIS_0;
1510 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1511 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1512 case DP_TRAIN_VOLTAGE_SWING_400:
1513 return DP_TRAIN_PRE_EMPHASIS_6;
1514 case DP_TRAIN_VOLTAGE_SWING_600:
1515 case DP_TRAIN_VOLTAGE_SWING_800:
1516 return DP_TRAIN_PRE_EMPHASIS_3_5;
1518 return DP_TRAIN_PRE_EMPHASIS_0;
1521 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1522 case DP_TRAIN_VOLTAGE_SWING_400:
1523 return DP_TRAIN_PRE_EMPHASIS_6;
1524 case DP_TRAIN_VOLTAGE_SWING_600:
1525 return DP_TRAIN_PRE_EMPHASIS_6;
1526 case DP_TRAIN_VOLTAGE_SWING_800:
1527 return DP_TRAIN_PRE_EMPHASIS_3_5;
1528 case DP_TRAIN_VOLTAGE_SWING_1200:
1530 return DP_TRAIN_PRE_EMPHASIS_0;
1536 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1541 uint8_t *adjust_request = link_status + (DP_ADJUST_REQUEST_LANE0_1 - DP_LANE0_1_STATUS);
1542 uint8_t voltage_max;
1543 uint8_t preemph_max;
1545 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1546 uint8_t this_v = intel_get_adjust_request_voltage(adjust_request, lane);
1547 uint8_t this_p = intel_get_adjust_request_pre_emphasis(adjust_request, lane);
1555 voltage_max = intel_dp_voltage_max(intel_dp);
1556 if (v >= voltage_max)
1557 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1559 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1560 if (p >= preemph_max)
1561 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1563 for (lane = 0; lane < 4; lane++)
1564 intel_dp->train_set[lane] = v | p;
1568 intel_dp_signal_levels(uint8_t train_set)
1570 uint32_t signal_levels = 0;
1572 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1573 case DP_TRAIN_VOLTAGE_SWING_400:
1575 signal_levels |= DP_VOLTAGE_0_4;
1577 case DP_TRAIN_VOLTAGE_SWING_600:
1578 signal_levels |= DP_VOLTAGE_0_6;
1580 case DP_TRAIN_VOLTAGE_SWING_800:
1581 signal_levels |= DP_VOLTAGE_0_8;
1583 case DP_TRAIN_VOLTAGE_SWING_1200:
1584 signal_levels |= DP_VOLTAGE_1_2;
1587 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1588 case DP_TRAIN_PRE_EMPHASIS_0:
1590 signal_levels |= DP_PRE_EMPHASIS_0;
1592 case DP_TRAIN_PRE_EMPHASIS_3_5:
1593 signal_levels |= DP_PRE_EMPHASIS_3_5;
1595 case DP_TRAIN_PRE_EMPHASIS_6:
1596 signal_levels |= DP_PRE_EMPHASIS_6;
1598 case DP_TRAIN_PRE_EMPHASIS_9_5:
1599 signal_levels |= DP_PRE_EMPHASIS_9_5;
1602 return signal_levels;
1605 /* Gen6's DP voltage swing and pre-emphasis control */
1607 intel_gen6_edp_signal_levels(uint8_t train_set)
1609 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1610 DP_TRAIN_PRE_EMPHASIS_MASK);
1611 switch (signal_levels) {
1612 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1613 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1614 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1615 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1616 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1617 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1618 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1619 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1620 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1621 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1622 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1623 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1624 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1625 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1627 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1628 "0x%x\n", signal_levels);
1629 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1633 /* Gen7's DP voltage swing and pre-emphasis control */
1635 intel_gen7_edp_signal_levels(uint8_t train_set)
1637 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1638 DP_TRAIN_PRE_EMPHASIS_MASK);
1639 switch (signal_levels) {
1640 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1641 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1642 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1643 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1644 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1645 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1647 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1648 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1649 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1650 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1652 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1653 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1654 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1655 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1658 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1659 "0x%x\n", signal_levels);
1660 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1664 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1666 intel_dp_signal_levels_hsw(uint8_t train_set)
1668 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1669 DP_TRAIN_PRE_EMPHASIS_MASK);
1670 switch (signal_levels) {
1671 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1672 return DDI_BUF_EMP_400MV_0DB_HSW;
1673 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1674 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1675 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1676 return DDI_BUF_EMP_400MV_6DB_HSW;
1677 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1678 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1680 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1681 return DDI_BUF_EMP_600MV_0DB_HSW;
1682 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1683 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1684 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1685 return DDI_BUF_EMP_600MV_6DB_HSW;
1687 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1688 return DDI_BUF_EMP_800MV_0DB_HSW;
1689 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1690 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1692 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1693 "0x%x\n", signal_levels);
1694 return DDI_BUF_EMP_400MV_0DB_HSW;
1699 intel_dp_set_link_train(struct intel_dp *intel_dp,
1700 uint32_t dp_reg_value,
1701 uint8_t dp_train_pat)
1703 struct drm_device *dev = intel_dp->base.base.dev;
1704 struct drm_i915_private *dev_priv = dev->dev_private;
1708 if (IS_HASWELL(dev)) {
1709 temp = I915_READ(DP_TP_CTL(intel_dp->port));
1711 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1712 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1714 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1716 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1717 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1718 case DP_TRAINING_PATTERN_DISABLE:
1719 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1720 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1722 if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) &
1723 DP_TP_STATUS_IDLE_DONE), 1))
1724 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1726 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1727 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1730 case DP_TRAINING_PATTERN_1:
1731 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1733 case DP_TRAINING_PATTERN_2:
1734 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1736 case DP_TRAINING_PATTERN_3:
1737 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1740 I915_WRITE(DP_TP_CTL(intel_dp->port), temp);
1742 } else if (HAS_PCH_CPT(dev) &&
1743 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1744 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1746 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1747 case DP_TRAINING_PATTERN_DISABLE:
1748 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1750 case DP_TRAINING_PATTERN_1:
1751 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1753 case DP_TRAINING_PATTERN_2:
1754 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1756 case DP_TRAINING_PATTERN_3:
1757 DRM_ERROR("DP training pattern 3 not supported\n");
1758 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1763 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1765 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1766 case DP_TRAINING_PATTERN_DISABLE:
1767 dp_reg_value |= DP_LINK_TRAIN_OFF;
1769 case DP_TRAINING_PATTERN_1:
1770 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1772 case DP_TRAINING_PATTERN_2:
1773 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1775 case DP_TRAINING_PATTERN_3:
1776 DRM_ERROR("DP training pattern 3 not supported\n");
1777 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1782 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1783 POSTING_READ(intel_dp->output_reg);
1785 intel_dp_aux_native_write_1(intel_dp,
1786 DP_TRAINING_PATTERN_SET,
1789 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1790 DP_TRAINING_PATTERN_DISABLE) {
1791 ret = intel_dp_aux_native_write(intel_dp,
1792 DP_TRAINING_LANE0_SET,
1793 intel_dp->train_set,
1794 intel_dp->lane_count);
1795 if (ret != intel_dp->lane_count)
1802 /* Enable corresponding port and start training pattern 1 */
1804 intel_dp_start_link_train(struct intel_dp *intel_dp)
1806 struct drm_encoder *encoder = &intel_dp->base.base;
1807 struct drm_device *dev = encoder->dev;
1810 bool clock_recovery = false;
1811 int voltage_tries, loop_tries;
1812 uint32_t DP = intel_dp->DP;
1814 if (IS_HASWELL(dev))
1815 intel_ddi_prepare_link_retrain(encoder);
1817 /* Write the link configuration data */
1818 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1819 intel_dp->link_configuration,
1820 DP_LINK_CONFIGURATION_SIZE);
1824 memset(intel_dp->train_set, 0, 4);
1828 clock_recovery = false;
1830 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1831 uint8_t link_status[DP_LINK_STATUS_SIZE];
1832 uint32_t signal_levels;
1834 if (IS_HASWELL(dev)) {
1835 signal_levels = intel_dp_signal_levels_hsw(
1836 intel_dp->train_set[0]);
1837 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1838 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1839 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1840 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1841 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1842 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1843 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1845 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1846 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1848 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1851 if (!intel_dp_set_link_train(intel_dp, DP,
1852 DP_TRAINING_PATTERN_1 |
1853 DP_LINK_SCRAMBLING_DISABLE))
1855 /* Set training pattern 1 */
1858 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1859 DRM_ERROR("failed to get link status\n");
1863 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1864 DRM_DEBUG_KMS("clock recovery OK\n");
1865 clock_recovery = true;
1869 /* Check to see if we've tried the max voltage */
1870 for (i = 0; i < intel_dp->lane_count; i++)
1871 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1873 if (i == intel_dp->lane_count && voltage_tries == 5) {
1874 if (++loop_tries == 5) {
1875 DRM_DEBUG_KMS("too many full retries, give up\n");
1878 memset(intel_dp->train_set, 0, 4);
1883 /* Check to see if we've tried the same voltage 5 times */
1884 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
1885 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1890 /* Compute new intel_dp->train_set as requested by target */
1891 intel_get_adjust_train(intel_dp, link_status);
1898 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1900 struct drm_device *dev = intel_dp->base.base.dev;
1901 bool channel_eq = false;
1902 int tries, cr_tries;
1903 uint32_t DP = intel_dp->DP;
1905 /* channel equalization */
1910 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1911 uint32_t signal_levels;
1912 uint8_t link_status[DP_LINK_STATUS_SIZE];
1915 DRM_ERROR("failed to train DP, aborting\n");
1916 intel_dp_link_down(intel_dp);
1920 if (IS_HASWELL(dev)) {
1921 signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1922 DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1923 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1924 signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1925 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1926 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1927 signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1928 DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1930 signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1931 DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1934 /* channel eq pattern */
1935 if (!intel_dp_set_link_train(intel_dp, DP,
1936 DP_TRAINING_PATTERN_2 |
1937 DP_LINK_SCRAMBLING_DISABLE))
1941 if (!intel_dp_get_link_status(intel_dp, link_status))
1944 /* Make sure clock is still ok */
1945 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1946 intel_dp_start_link_train(intel_dp);
1951 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1956 /* Try 5 times, then try clock recovery if that fails */
1958 intel_dp_link_down(intel_dp);
1959 intel_dp_start_link_train(intel_dp);
1965 /* Compute new intel_dp->train_set as requested by target */
1966 intel_get_adjust_train(intel_dp, link_status);
1971 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1973 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
1977 intel_dp_link_down(struct intel_dp *intel_dp)
1979 struct drm_device *dev = intel_dp->base.base.dev;
1980 struct drm_i915_private *dev_priv = dev->dev_private;
1981 uint32_t DP = intel_dp->DP;
1984 * DDI code has a strict mode set sequence and we should try to respect
1985 * it, otherwise we might hang the machine in many different ways. So we
1986 * really should be disabling the port only on a complete crtc_disable
1987 * sequence. This function is just called under two conditions on DDI
1989 * - Link train failed while doing crtc_enable, and on this case we
1990 * really should respect the mode set sequence and wait for a
1992 * - Someone turned the monitor off and intel_dp_check_link_status
1993 * called us. We don't need to disable the whole port on this case, so
1994 * when someone turns the monitor on again,
1995 * intel_ddi_prepare_link_retrain will take care of redoing the link
1998 if (IS_HASWELL(dev))
2001 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2004 DRM_DEBUG_KMS("\n");
2006 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2007 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2008 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2010 DP &= ~DP_LINK_TRAIN_MASK;
2011 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2013 POSTING_READ(intel_dp->output_reg);
2017 if (HAS_PCH_IBX(dev) &&
2018 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2019 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2021 /* Hardware workaround: leaving our transcoder select
2022 * set to transcoder B while it's off will prevent the
2023 * corresponding HDMI output on transcoder A.
2025 * Combine this with another hardware workaround:
2026 * transcoder select bit can only be cleared while the
2029 DP &= ~DP_PIPEB_SELECT;
2030 I915_WRITE(intel_dp->output_reg, DP);
2032 /* Changes to enable or select take place the vblank
2033 * after being written.
2036 /* We can arrive here never having been attached
2037 * to a CRTC, for instance, due to inheriting
2038 * random state from the BIOS.
2040 * If the pipe is not running, play safe and
2041 * wait for the clocks to stabilise before
2044 POSTING_READ(intel_dp->output_reg);
2047 intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
2050 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2051 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2052 POSTING_READ(intel_dp->output_reg);
2053 msleep(intel_dp->panel_power_down_delay);
2057 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2059 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2060 sizeof(intel_dp->dpcd)) == 0)
2061 return false; /* aux transfer failed */
2063 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2064 return false; /* DPCD not present */
2066 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2067 DP_DWN_STRM_PORT_PRESENT))
2068 return true; /* native DP sink */
2070 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2071 return true; /* no per-port downstream info */
2073 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2074 intel_dp->downstream_ports,
2075 DP_MAX_DOWNSTREAM_PORTS) == 0)
2076 return false; /* downstream port status fetch failed */
2082 intel_dp_probe_oui(struct intel_dp *intel_dp)
2086 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2089 ironlake_edp_panel_vdd_on(intel_dp);
2091 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2092 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2093 buf[0], buf[1], buf[2]);
2095 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2096 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2097 buf[0], buf[1], buf[2]);
2099 ironlake_edp_panel_vdd_off(intel_dp, false);
2103 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2107 ret = intel_dp_aux_native_read_retry(intel_dp,
2108 DP_DEVICE_SERVICE_IRQ_VECTOR,
2109 sink_irq_vector, 1);
2117 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2119 /* NAK by default */
2120 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_ACK);
2124 * According to DP spec
2127 * 2. Configure link according to Receiver Capabilities
2128 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2129 * 4. Check link status on receipt of hot-plug interrupt
2133 intel_dp_check_link_status(struct intel_dp *intel_dp)
2136 u8 link_status[DP_LINK_STATUS_SIZE];
2138 if (!intel_dp->base.connectors_active)
2141 if (WARN_ON(!intel_dp->base.base.crtc))
2144 /* Try to read receiver status if the link appears to be up */
2145 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2146 intel_dp_link_down(intel_dp);
2150 /* Now read the DPCD to see if it's actually running */
2151 if (!intel_dp_get_dpcd(intel_dp)) {
2152 intel_dp_link_down(intel_dp);
2156 /* Try to read the source of the interrupt */
2157 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2158 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2159 /* Clear interrupt source */
2160 intel_dp_aux_native_write_1(intel_dp,
2161 DP_DEVICE_SERVICE_IRQ_VECTOR,
2164 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2165 intel_dp_handle_test_request(intel_dp);
2166 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2167 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2170 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2171 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2172 drm_get_encoder_name(&intel_dp->base.base));
2173 intel_dp_start_link_train(intel_dp);
2174 intel_dp_complete_link_train(intel_dp);
2178 /* XXX this is probably wrong for multiple downstream ports */
2179 static enum drm_connector_status
2180 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2182 uint8_t *dpcd = intel_dp->dpcd;
2186 if (!intel_dp_get_dpcd(intel_dp))
2187 return connector_status_disconnected;
2189 /* if there's no downstream port, we're done */
2190 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2191 return connector_status_connected;
2193 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2194 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2197 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2199 return connector_status_unknown;
2200 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2201 : connector_status_disconnected;
2204 /* If no HPD, poke DDC gently */
2205 if (drm_probe_ddc(&intel_dp->adapter))
2206 return connector_status_connected;
2208 /* Well we tried, say unknown for unreliable port types */
2209 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2210 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2211 return connector_status_unknown;
2213 /* Anything else is out of spec, warn and ignore */
2214 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2215 return connector_status_disconnected;
2218 static enum drm_connector_status
2219 ironlake_dp_detect(struct intel_dp *intel_dp)
2221 enum drm_connector_status status;
2223 /* Can't disconnect eDP, but you can close the lid... */
2224 if (is_edp(intel_dp)) {
2225 status = intel_panel_detect(intel_dp->base.base.dev);
2226 if (status == connector_status_unknown)
2227 status = connector_status_connected;
2231 return intel_dp_detect_dpcd(intel_dp);
2234 static enum drm_connector_status
2235 g4x_dp_detect(struct intel_dp *intel_dp)
2237 struct drm_device *dev = intel_dp->base.base.dev;
2238 struct drm_i915_private *dev_priv = dev->dev_private;
2241 switch (intel_dp->output_reg) {
2243 bit = DPB_HOTPLUG_LIVE_STATUS;
2246 bit = DPC_HOTPLUG_LIVE_STATUS;
2249 bit = DPD_HOTPLUG_LIVE_STATUS;
2252 return connector_status_unknown;
2255 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2256 return connector_status_disconnected;
2258 return intel_dp_detect_dpcd(intel_dp);
2261 static struct edid *
2262 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2264 struct intel_connector *intel_connector = to_intel_connector(connector);
2266 /* use cached edid if we have one */
2267 if (intel_connector->edid) {
2272 if (IS_ERR(intel_connector->edid))
2275 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2276 edid = kmalloc(size, GFP_KERNEL);
2280 memcpy(edid, intel_connector->edid, size);
2284 return drm_get_edid(connector, adapter);
2288 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2290 struct intel_connector *intel_connector = to_intel_connector(connector);
2292 /* use cached edid if we have one */
2293 if (intel_connector->edid) {
2295 if (IS_ERR(intel_connector->edid))
2298 return intel_connector_update_modes(connector,
2299 intel_connector->edid);
2302 return intel_ddc_get_modes(connector, adapter);
2307 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2309 * \return true if DP port is connected.
2310 * \return false if DP port is disconnected.
2312 static enum drm_connector_status
2313 intel_dp_detect(struct drm_connector *connector, bool force)
2315 struct intel_dp *intel_dp = intel_attached_dp(connector);
2316 struct drm_device *dev = intel_dp->base.base.dev;
2317 enum drm_connector_status status;
2318 struct edid *edid = NULL;
2320 intel_dp->has_audio = false;
2322 if (HAS_PCH_SPLIT(dev))
2323 status = ironlake_dp_detect(intel_dp);
2325 status = g4x_dp_detect(intel_dp);
2327 DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2328 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2329 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2330 intel_dp->dpcd[6], intel_dp->dpcd[7]);
2332 if (status != connector_status_connected)
2335 intel_dp_probe_oui(intel_dp);
2337 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2338 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2340 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2342 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2347 return connector_status_connected;
2350 static int intel_dp_get_modes(struct drm_connector *connector)
2352 struct intel_dp *intel_dp = intel_attached_dp(connector);
2353 struct intel_connector *intel_connector = to_intel_connector(connector);
2354 struct drm_device *dev = intel_dp->base.base.dev;
2357 /* We should parse the EDID data and find out if it has an audio sink
2360 ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2364 /* if eDP has no EDID, fall back to fixed mode */
2365 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2366 struct drm_display_mode *mode;
2367 mode = drm_mode_duplicate(dev,
2368 intel_connector->panel.fixed_mode);
2370 drm_mode_probed_add(connector, mode);
2378 intel_dp_detect_audio(struct drm_connector *connector)
2380 struct intel_dp *intel_dp = intel_attached_dp(connector);
2382 bool has_audio = false;
2384 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2386 has_audio = drm_detect_monitor_audio(edid);
2394 intel_dp_set_property(struct drm_connector *connector,
2395 struct drm_property *property,
2398 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2399 struct intel_dp *intel_dp = intel_attached_dp(connector);
2402 ret = drm_connector_property_set_value(connector, property, val);
2406 if (property == dev_priv->force_audio_property) {
2410 if (i == intel_dp->force_audio)
2413 intel_dp->force_audio = i;
2415 if (i == HDMI_AUDIO_AUTO)
2416 has_audio = intel_dp_detect_audio(connector);
2418 has_audio = (i == HDMI_AUDIO_ON);
2420 if (has_audio == intel_dp->has_audio)
2423 intel_dp->has_audio = has_audio;
2427 if (property == dev_priv->broadcast_rgb_property) {
2428 if (val == !!intel_dp->color_range)
2431 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2438 if (intel_dp->base.base.crtc) {
2439 struct drm_crtc *crtc = intel_dp->base.base.crtc;
2440 intel_set_mode(crtc, &crtc->mode,
2441 crtc->x, crtc->y, crtc->fb);
2448 intel_dp_destroy(struct drm_connector *connector)
2450 struct drm_device *dev = connector->dev;
2451 struct intel_dp *intel_dp = intel_attached_dp(connector);
2452 struct intel_connector *intel_connector = to_intel_connector(connector);
2454 if (!IS_ERR_OR_NULL(intel_connector->edid))
2455 kfree(intel_connector->edid);
2457 if (is_edp(intel_dp)) {
2458 intel_panel_destroy_backlight(dev);
2459 intel_panel_fini(&intel_connector->panel);
2462 drm_sysfs_connector_remove(connector);
2463 drm_connector_cleanup(connector);
2467 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2469 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2471 i2c_del_adapter(&intel_dp->adapter);
2472 drm_encoder_cleanup(encoder);
2473 if (is_edp(intel_dp)) {
2474 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2475 ironlake_panel_vdd_off_sync(intel_dp);
2480 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2481 .mode_fixup = intel_dp_mode_fixup,
2482 .mode_set = intel_dp_mode_set,
2483 .disable = intel_encoder_noop,
2486 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw = {
2487 .mode_fixup = intel_dp_mode_fixup,
2488 .mode_set = intel_ddi_mode_set,
2489 .disable = intel_encoder_noop,
2492 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2493 .dpms = intel_connector_dpms,
2494 .detect = intel_dp_detect,
2495 .fill_modes = drm_helper_probe_single_connector_modes,
2496 .set_property = intel_dp_set_property,
2497 .destroy = intel_dp_destroy,
2500 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2501 .get_modes = intel_dp_get_modes,
2502 .mode_valid = intel_dp_mode_valid,
2503 .best_encoder = intel_best_encoder,
2506 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2507 .destroy = intel_dp_encoder_destroy,
2511 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2513 struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
2515 intel_dp_check_link_status(intel_dp);
2518 /* Return which DP Port should be selected for Transcoder DP control */
2520 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2522 struct drm_device *dev = crtc->dev;
2523 struct intel_encoder *encoder;
2525 for_each_encoder_on_crtc(dev, crtc, encoder) {
2526 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2528 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT ||
2529 intel_dp->base.type == INTEL_OUTPUT_EDP)
2530 return intel_dp->output_reg;
2536 /* check the VBT to see whether the eDP is on DP-D port */
2537 bool intel_dpd_is_edp(struct drm_device *dev)
2539 struct drm_i915_private *dev_priv = dev->dev_private;
2540 struct child_device_config *p_child;
2543 if (!dev_priv->child_dev_num)
2546 for (i = 0; i < dev_priv->child_dev_num; i++) {
2547 p_child = dev_priv->child_dev + i;
2549 if (p_child->dvo_port == PORT_IDPD &&
2550 p_child->device_type == DEVICE_TYPE_eDP)
2557 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2559 intel_attach_force_audio_property(connector);
2560 intel_attach_broadcast_rgb_property(connector);
2564 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2566 struct drm_i915_private *dev_priv = dev->dev_private;
2567 struct drm_connector *connector;
2568 struct intel_dp *intel_dp;
2569 struct intel_encoder *intel_encoder;
2570 struct intel_connector *intel_connector;
2571 struct drm_display_mode *fixed_mode = NULL;
2572 const char *name = NULL;
2575 intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
2579 intel_dp->output_reg = output_reg;
2580 intel_dp->port = port;
2581 /* Preserve the current hw state. */
2582 intel_dp->DP = I915_READ(intel_dp->output_reg);
2584 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2585 if (!intel_connector) {
2589 intel_encoder = &intel_dp->base;
2590 intel_dp->attached_connector = intel_connector;
2592 if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
2593 if (intel_dpd_is_edp(dev))
2594 intel_dp->is_pch_edp = true;
2597 * FIXME : We need to initialize built-in panels before external panels.
2598 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2600 if (IS_VALLEYVIEW(dev) && output_reg == DP_C) {
2601 type = DRM_MODE_CONNECTOR_eDP;
2602 intel_encoder->type = INTEL_OUTPUT_EDP;
2603 } else if (output_reg == DP_A || is_pch_edp(intel_dp)) {
2604 type = DRM_MODE_CONNECTOR_eDP;
2605 intel_encoder->type = INTEL_OUTPUT_EDP;
2607 type = DRM_MODE_CONNECTOR_DisplayPort;
2608 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2611 connector = &intel_connector->base;
2612 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2613 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2615 connector->polled = DRM_CONNECTOR_POLL_HPD;
2617 intel_encoder->cloneable = false;
2619 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2620 ironlake_panel_vdd_work);
2622 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2624 connector->interlace_allowed = true;
2625 connector->doublescan_allowed = 0;
2627 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2628 DRM_MODE_ENCODER_TMDS);
2630 if (IS_HASWELL(dev))
2631 drm_encoder_helper_add(&intel_encoder->base,
2632 &intel_dp_helper_funcs_hsw);
2634 drm_encoder_helper_add(&intel_encoder->base,
2635 &intel_dp_helper_funcs);
2637 intel_connector_attach_encoder(intel_connector, intel_encoder);
2638 drm_sysfs_connector_add(connector);
2640 if (IS_HASWELL(dev)) {
2641 intel_encoder->enable = intel_enable_ddi;
2642 intel_encoder->pre_enable = intel_ddi_pre_enable;
2643 intel_encoder->disable = intel_disable_ddi;
2644 intel_encoder->post_disable = intel_ddi_post_disable;
2645 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
2647 intel_encoder->enable = intel_enable_dp;
2648 intel_encoder->pre_enable = intel_pre_enable_dp;
2649 intel_encoder->disable = intel_disable_dp;
2650 intel_encoder->post_disable = intel_post_disable_dp;
2651 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2653 intel_connector->get_hw_state = intel_connector_get_hw_state;
2655 /* Set up the DDC bus. */
2661 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2665 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2669 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2673 WARN(1, "Invalid port %c\n", port_name(port));
2677 /* Cache some DPCD data in the eDP case */
2678 if (is_edp(intel_dp)) {
2679 struct edp_power_seq cur, vbt;
2680 u32 pp_on, pp_off, pp_div;
2682 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2683 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2684 pp_div = I915_READ(PCH_PP_DIVISOR);
2686 if (!pp_on || !pp_off || !pp_div) {
2687 DRM_INFO("bad panel power sequencing delays, disabling panel\n");
2688 intel_dp_encoder_destroy(&intel_dp->base.base);
2689 intel_dp_destroy(&intel_connector->base);
2693 /* Pull timing values out of registers */
2694 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2695 PANEL_POWER_UP_DELAY_SHIFT;
2697 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2698 PANEL_LIGHT_ON_DELAY_SHIFT;
2700 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2701 PANEL_LIGHT_OFF_DELAY_SHIFT;
2703 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2704 PANEL_POWER_DOWN_DELAY_SHIFT;
2706 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2707 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2709 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2710 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2712 vbt = dev_priv->edp.pps;
2714 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2715 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2717 #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10)
2719 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2720 intel_dp->backlight_on_delay = get_delay(t8);
2721 intel_dp->backlight_off_delay = get_delay(t9);
2722 intel_dp->panel_power_down_delay = get_delay(t10);
2723 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2725 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2726 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2727 intel_dp->panel_power_cycle_delay);
2729 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2730 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2733 intel_dp_i2c_init(intel_dp, intel_connector, name);
2735 if (is_edp(intel_dp)) {
2737 struct drm_display_mode *scan;
2740 ironlake_edp_panel_vdd_on(intel_dp);
2741 ret = intel_dp_get_dpcd(intel_dp);
2742 ironlake_edp_panel_vdd_off(intel_dp, false);
2745 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2746 dev_priv->no_aux_handshake =
2747 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2748 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2750 /* if this fails, presume the device is a ghost */
2751 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2752 intel_dp_encoder_destroy(&intel_dp->base.base);
2753 intel_dp_destroy(&intel_connector->base);
2757 ironlake_edp_panel_vdd_on(intel_dp);
2758 edid = drm_get_edid(connector, &intel_dp->adapter);
2760 if (drm_add_edid_modes(connector, edid)) {
2761 drm_mode_connector_update_edid_property(connector, edid);
2762 drm_edid_to_eld(connector, edid);
2765 edid = ERR_PTR(-EINVAL);
2768 edid = ERR_PTR(-ENOENT);
2770 intel_connector->edid = edid;
2772 /* prefer fixed mode from EDID if available */
2773 list_for_each_entry(scan, &connector->probed_modes, head) {
2774 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2775 fixed_mode = drm_mode_duplicate(dev, scan);
2780 /* fallback to VBT if available for eDP */
2781 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2782 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2784 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2787 ironlake_edp_panel_vdd_off(intel_dp, false);
2790 intel_encoder->hot_plug = intel_dp_hot_plug;
2792 if (is_edp(intel_dp)) {
2793 intel_panel_init(&intel_connector->panel, fixed_mode);
2794 intel_panel_setup_backlight(connector);
2797 intel_dp_add_properties(intel_dp, connector);
2799 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2800 * 0xd. Failure to do so will result in spurious interrupts being
2801 * generated on the port when a cable is not attached.
2803 if (IS_G4X(dev) && !IS_GM45(dev)) {
2804 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2805 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);