drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 /**
  42  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  43  * @intel_dp: DP struct
  44  *
  45  * If a CPU or PCH DP output is attached to an eDP panel, this function
  46  * will return true, and false otherwise.
  47  */
  48 static bool is_edp(struct intel_dp *intel_dp)
  49 {
  50         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  51
  52         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  53 }
  54
  55 /**
  56  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  57  * @intel_dp: DP struct
  58  *
  59  * Returns true if the given DP struct corresponds to a PCH DP port attached
  60  * to an eDP panel, false otherwise.  Helpful for determining whether we
  61  * may need FDI resources for a given DP output or not.
  62  */
  63 static bool is_pch_edp(struct intel_dp *intel_dp)
  64 {
  65         return intel_dp->is_pch_edp;
  66 }
  67
  68 /**
  69  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  70  * @intel_dp: DP struct
  71  *
  72  * Returns true if the given DP struct corresponds to a CPU eDP port.
  73  */
  74 static bool is_cpu_edp(struct intel_dp *intel_dp)
  75 {
  76         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  77 }
  78
  79 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  80 {
  81         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  82
  83         return intel_dig_port->base.base.dev;
  84 }
  85
  86 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  87 {
  88         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  89 }
  90
  91 /**
  92  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  93  * @encoder: DRM encoder
  94  *
  95  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
  96  * by intel_display.c.
  97  */
  98 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  99 {
 100         struct intel_dp *intel_dp;
 101
 102         if (!encoder)
 103                 return false;
 104
 105         intel_dp = enc_to_intel_dp(encoder);
 106
 107         return is_pch_edp(intel_dp);
 108 }
 109
 110 static void intel_dp_link_down(struct intel_dp *intel_dp);
 111
 112 void
 113 intel_edp_link_config(struct intel_encoder *intel_encoder,
 114                        int *lane_num, int *link_bw)
 115 {
 116         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
 117
 118         *lane_num = intel_dp->lane_count;
 119         *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 120 }
 121
 122 int
 123 intel_edp_target_clock(struct intel_encoder *intel_encoder,
 124                        struct drm_display_mode *mode)
 125 {
 126         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
 127         struct intel_connector *intel_connector = intel_dp->attached_connector;
 128
 129         if (intel_connector->panel.fixed_mode)
 130                 return intel_connector->panel.fixed_mode->clock;
 131         else
 132                 return mode->clock;
 133 }
 134
 135 static int
 136 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 137 {
 138         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 139
 140         switch (max_link_bw) {
 141         case DP_LINK_BW_1_62:
 142         case DP_LINK_BW_2_7:
 143                 break;
 144         default:
 145                 max_link_bw = DP_LINK_BW_1_62;
 146                 break;
 147         }
 148         return max_link_bw;
 149 }
 150
 151 static int
 152 intel_dp_link_clock(uint8_t link_bw)
 153 {
 154         if (link_bw == DP_LINK_BW_2_7)
 155                 return 270000;
 156         else
 157                 return 162000;
 158 }
 159
 160 /*
 161  * The units on the numbers in the next two are... bizarre.  Examples will
 162  * make it clearer; this one parallels an example in the eDP spec.
 163  *
 164  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 165  *
 166  *     270000 * 1 * 8 / 10 == 216000
 167  *
 168  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 169  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 170  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 171  * 119000.  At 18bpp that's 2142000 kilobits per second.
 172  *
 173  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 174  * get the result in decakilobits instead of kilobits.
 175  */
 176
 177 static int
 178 intel_dp_link_required(int pixel_clock, int bpp)
 179 {
 180         return (pixel_clock * bpp + 9) / 10;
 181 }
 182
 183 static int
 184 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 185 {
 186         return (max_link_clock * max_lanes * 8) / 10;
 187 }
 188
 189 static bool
 190 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
 191                           struct drm_display_mode *mode,
 192                           bool adjust_mode)
 193 {
 194         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
 195         int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 196         int max_rate, mode_rate;
 197
 198         mode_rate = intel_dp_link_required(mode->clock, 24);
 199         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 200
 201         if (mode_rate > max_rate) {
 202                 mode_rate = intel_dp_link_required(mode->clock, 18);
 203                 if (mode_rate > max_rate)
 204                         return false;
 205
 206                 if (adjust_mode)
 207                         mode->private_flags
 208                                 |= INTEL_MODE_DP_FORCE_6BPC;
 209
 210                 return true;
 211         }
 212
 213         return true;
 214 }
 215
 216 static int
 217 intel_dp_mode_valid(struct drm_connector *connector,
 218                     struct drm_display_mode *mode)
 219 {
 220         struct intel_dp *intel_dp = intel_attached_dp(connector);
 221         struct intel_connector *intel_connector = to_intel_connector(connector);
 222         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 223
 224         if (is_edp(intel_dp) && fixed_mode) {
 225                 if (mode->hdisplay > fixed_mode->hdisplay)
 226                         return MODE_PANEL;
 227
 228                 if (mode->vdisplay > fixed_mode->vdisplay)
 229                         return MODE_PANEL;
 230         }
 231
 232         if (!intel_dp_adjust_dithering(intel_dp, mode, false))
 233                 return MODE_CLOCK_HIGH;
 234
 235         if (mode->clock < 10000)
 236                 return MODE_CLOCK_LOW;
 237
 238         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 239                 return MODE_H_ILLEGAL;
 240
 241         return MODE_OK;
 242 }
 243
 244 static uint32_t
 245 pack_aux(uint8_t *src, int src_bytes)
 246 {
 247         int     i;
 248         uint32_t v = 0;
 249
 250         if (src_bytes > 4)
 251                 src_bytes = 4;
 252         for (i = 0; i < src_bytes; i++)
 253                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 254         return v;
 255 }
 256
 257 static void
 258 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 259 {
 260         int i;
 261         if (dst_bytes > 4)
 262                 dst_bytes = 4;
 263         for (i = 0; i < dst_bytes; i++)
 264                 dst[i] = src >> ((3-i) * 8);
 265 }
 266
 267 /* hrawclock is 1/4 the FSB frequency */
 268 static int
 269 intel_hrawclk(struct drm_device *dev)
 270 {
 271         struct drm_i915_private *dev_priv = dev->dev_private;
 272         uint32_t clkcfg;
 273
 274         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 275         if (IS_VALLEYVIEW(dev))
 276                 return 200;
 277
 278         clkcfg = I915_READ(CLKCFG);
 279         switch (clkcfg & CLKCFG_FSB_MASK) {
 280         case CLKCFG_FSB_400:
 281                 return 100;
 282         case CLKCFG_FSB_533:
 283                 return 133;
 284         case CLKCFG_FSB_667:
 285                 return 166;
 286         case CLKCFG_FSB_800:
 287                 return 200;
 288         case CLKCFG_FSB_1067:
 289                 return 266;
 290         case CLKCFG_FSB_1333:
 291                 return 333;
 292         /* these two are just a guess; one of them might be right */
 293         case CLKCFG_FSB_1600:
 294         case CLKCFG_FSB_1600_ALT:
 295                 return 400;
 296         default:
 297                 return 133;
 298         }
 299 }
 300
 301 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 302 {
 303         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 304         struct drm_i915_private *dev_priv = dev->dev_private;
 305
 306         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 307 }
 308
 309 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 310 {
 311         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 312         struct drm_i915_private *dev_priv = dev->dev_private;
 313
 314         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 315 }
 316
 317 static void
 318 intel_dp_check_edp(struct intel_dp *intel_dp)
 319 {
 320         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 321         struct drm_i915_private *dev_priv = dev->dev_private;
 322
 323         if (!is_edp(intel_dp))
 324                 return;
 325         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 326                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 327                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 328                               I915_READ(PCH_PP_STATUS),
 329                               I915_READ(PCH_PP_CONTROL));
 330         }
 331 }
 332
 333 static int
 334 intel_dp_aux_ch(struct intel_dp *intel_dp,
 335                 uint8_t *send, int send_bytes,
 336                 uint8_t *recv, int recv_size)
 337 {
 338         uint32_t output_reg = intel_dp->output_reg;
 339         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 340         struct drm_device *dev = intel_dig_port->base.base.dev;
 341         struct drm_i915_private *dev_priv = dev->dev_private;
 342         uint32_t ch_ctl = output_reg + 0x10;
 343         uint32_t ch_data = ch_ctl + 4;
 344         int i;
 345         int recv_bytes;
 346         uint32_t status;
 347         uint32_t aux_clock_divider;
 348         int try, precharge;
 349
 350         if (IS_HASWELL(dev)) {
 351                 switch (intel_dig_port->port) {
 352                 case PORT_A:
 353                         ch_ctl = DPA_AUX_CH_CTL;
 354                         ch_data = DPA_AUX_CH_DATA1;
 355                         break;
 356                 case PORT_B:
 357                         ch_ctl = PCH_DPB_AUX_CH_CTL;
 358                         ch_data = PCH_DPB_AUX_CH_DATA1;
 359                         break;
 360                 case PORT_C:
 361                         ch_ctl = PCH_DPC_AUX_CH_CTL;
 362                         ch_data = PCH_DPC_AUX_CH_DATA1;
 363                         break;
 364                 case PORT_D:
 365                         ch_ctl = PCH_DPD_AUX_CH_CTL;
 366                         ch_data = PCH_DPD_AUX_CH_DATA1;
 367                         break;
 368                 default:
 369                         BUG();
 370                 }
 371         }
 372
 373         intel_dp_check_edp(intel_dp);
 374         /* The clock divider is based off the hrawclk,
 375          * and would like to run at 2MHz. So, take the
 376          * hrawclk value and divide by 2 and use that
 377          *
 378          * Note that PCH attached eDP panels should use a 125MHz input
 379          * clock divider.
 380          */
 381         if (is_cpu_edp(intel_dp)) {
 382                 if (IS_HASWELL(dev))
 383                         aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
 384                 else if (IS_VALLEYVIEW(dev))
 385                         aux_clock_divider = 100;
 386                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 387                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 388                 else
 389                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 390         } else if (HAS_PCH_SPLIT(dev))
 391                 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 392         else
 393                 aux_clock_divider = intel_hrawclk(dev) / 2;
 394
 395         if (IS_GEN6(dev))
 396                 precharge = 3;
 397         else
 398                 precharge = 5;
 399
 400         /* Try to wait for any previous AUX channel activity */
 401         for (try = 0; try < 3; try++) {
 402                 status = I915_READ(ch_ctl);
 403                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 404                         break;
 405                 msleep(1);
 406         }
 407
 408         if (try == 3) {
 409                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 410                      I915_READ(ch_ctl));
 411                 return -EBUSY;
 412         }
 413
 414         /* Must try at least 3 times according to DP spec */
 415         for (try = 0; try < 5; try++) {
 416                 /* Load the send data into the aux channel data registers */
 417                 for (i = 0; i < send_bytes; i += 4)
 418                         I915_WRITE(ch_data + i,
 419                                    pack_aux(send + i, send_bytes - i));
 420
 421                 /* Send the command and wait for it to complete */
 422                 I915_WRITE(ch_ctl,
 423                            DP_AUX_CH_CTL_SEND_BUSY |
 424                            DP_AUX_CH_CTL_TIME_OUT_400us |
 425                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 426                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 427                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 428                            DP_AUX_CH_CTL_DONE |
 429                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 430                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 431                 for (;;) {
 432                         status = I915_READ(ch_ctl);
 433                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 434                                 break;
 435                         udelay(100);
 436                 }
 437
 438                 /* Clear done status and any errors */
 439                 I915_WRITE(ch_ctl,
 440                            status |
 441                            DP_AUX_CH_CTL_DONE |
 442                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 443                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 444
 445                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 446                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 447                         continue;
 448                 if (status & DP_AUX_CH_CTL_DONE)
 449                         break;
 450         }
 451
 452         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 453                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 454                 return -EBUSY;
 455         }
 456
 457         /* Check for timeout or receive error.
 458          * Timeouts occur when the sink is not connected
 459          */
 460         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 461                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 462                 return -EIO;
 463         }
 464
 465         /* Timeouts occur when the device isn't connected, so they're
 466          * "normal" -- don't fill the kernel log with these */
 467         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 468                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 469                 return -ETIMEDOUT;
 470         }
 471
 472         /* Unload any bytes sent back from the other side */
 473         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 474                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 475         if (recv_bytes > recv_size)
 476                 recv_bytes = recv_size;
 477
 478         for (i = 0; i < recv_bytes; i += 4)
 479                 unpack_aux(I915_READ(ch_data + i),
 480                            recv + i, recv_bytes - i);
 481
 482         return recv_bytes;
 483 }
 484
 485 /* Write data to the aux channel in native mode */
 486 static int
 487 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 488                           uint16_t address, uint8_t *send, int send_bytes)
 489 {
 490         int ret;
 491         uint8_t msg[20];
 492         int msg_bytes;
 493         uint8_t ack;
 494
 495         intel_dp_check_edp(intel_dp);
 496         if (send_bytes > 16)
 497                 return -1;
 498         msg[0] = AUX_NATIVE_WRITE << 4;
 499         msg[1] = address >> 8;
 500         msg[2] = address & 0xff;
 501         msg[3] = send_bytes - 1;
 502         memcpy(&msg[4], send, send_bytes);
 503         msg_bytes = send_bytes + 4;
 504         for (;;) {
 505                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 506                 if (ret < 0)
 507                         return ret;
 508                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 509                         break;
 510                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 511                         udelay(100);
 512                 else
 513                         return -EIO;
 514         }
 515         return send_bytes;
 516 }
 517
 518 /* Write a single byte to the aux channel in native mode */
 519 static int
 520 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 521                             uint16_t address, uint8_t byte)
 522 {
 523         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 524 }
 525
 526 /* read bytes from a native aux channel */
 527 static int
 528 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 529                          uint16_t address, uint8_t *recv, int recv_bytes)
 530 {
 531         uint8_t msg[4];
 532         int msg_bytes;
 533         uint8_t reply[20];
 534         int reply_bytes;
 535         uint8_t ack;
 536         int ret;
 537
 538         intel_dp_check_edp(intel_dp);
 539         msg[0] = AUX_NATIVE_READ << 4;
 540         msg[1] = address >> 8;
 541         msg[2] = address & 0xff;
 542         msg[3] = recv_bytes - 1;
 543
 544         msg_bytes = 4;
 545         reply_bytes = recv_bytes + 1;
 546
 547         for (;;) {
 548                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 549                                       reply, reply_bytes);
 550                 if (ret == 0)
 551                         return -EPROTO;
 552                 if (ret < 0)
 553                         return ret;
 554                 ack = reply[0];
 555                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 556                         memcpy(recv, reply + 1, ret - 1);
 557                         return ret - 1;
 558                 }
 559                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 560                         udelay(100);
 561                 else
 562                         return -EIO;
 563         }
 564 }
 565
 566 static int
 567 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 568                     uint8_t write_byte, uint8_t *read_byte)
 569 {
 570         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 571         struct intel_dp *intel_dp = container_of(adapter,
 572                                                 struct intel_dp,
 573                                                 adapter);
 574         uint16_t address = algo_data->address;
 575         uint8_t msg[5];
 576         uint8_t reply[2];
 577         unsigned retry;
 578         int msg_bytes;
 579         int reply_bytes;
 580         int ret;
 581
 582         intel_dp_check_edp(intel_dp);
 583         /* Set up the command byte */
 584         if (mode & MODE_I2C_READ)
 585                 msg[0] = AUX_I2C_READ << 4;
 586         else
 587                 msg[0] = AUX_I2C_WRITE << 4;
 588
 589         if (!(mode & MODE_I2C_STOP))
 590                 msg[0] |= AUX_I2C_MOT << 4;
 591
 592         msg[1] = address >> 8;
 593         msg[2] = address;
 594
 595         switch (mode) {
 596         case MODE_I2C_WRITE:
 597                 msg[3] = 0;
 598                 msg[4] = write_byte;
 599                 msg_bytes = 5;
 600                 reply_bytes = 1;
 601                 break;
 602         case MODE_I2C_READ:
 603                 msg[3] = 0;
 604                 msg_bytes = 4;
 605                 reply_bytes = 2;
 606                 break;
 607         default:
 608                 msg_bytes = 3;
 609                 reply_bytes = 1;
 610                 break;
 611         }
 612
 613         for (retry = 0; retry < 5; retry++) {
 614                 ret = intel_dp_aux_ch(intel_dp,
 615                                       msg, msg_bytes,
 616                                       reply, reply_bytes);
 617                 if (ret < 0) {
 618                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 619                         return ret;
 620                 }
 621
 622                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 623                 case AUX_NATIVE_REPLY_ACK:
 624                         /* I2C-over-AUX Reply field is only valid
 625                          * when paired with AUX ACK.
 626                          */
 627                         break;
 628                 case AUX_NATIVE_REPLY_NACK:
 629                         DRM_DEBUG_KMS("aux_ch native nack\n");
 630                         return -EREMOTEIO;
 631                 case AUX_NATIVE_REPLY_DEFER:
 632                         udelay(100);
 633                         continue;
 634                 default:
 635                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 636                                   reply[0]);
 637                         return -EREMOTEIO;
 638                 }
 639
 640                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 641                 case AUX_I2C_REPLY_ACK:
 642                         if (mode == MODE_I2C_READ) {
 643                                 *read_byte = reply[1];
 644                         }
 645                         return reply_bytes - 1;
 646                 case AUX_I2C_REPLY_NACK:
 647                         DRM_DEBUG_KMS("aux_i2c nack\n");
 648                         return -EREMOTEIO;
 649                 case AUX_I2C_REPLY_DEFER:
 650                         DRM_DEBUG_KMS("aux_i2c defer\n");
 651                         udelay(100);
 652                         break;
 653                 default:
 654                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 655                         return -EREMOTEIO;
 656                 }
 657         }
 658
 659         DRM_ERROR("too many retries, giving up\n");
 660         return -EREMOTEIO;
 661 }
 662
 663 static int
 664 intel_dp_i2c_init(struct intel_dp *intel_dp,
 665                   struct intel_connector *intel_connector, const char *name)
 666 {
 667         int     ret;
 668
 669         DRM_DEBUG_KMS("i2c_init %s\n", name);
 670         intel_dp->algo.running = false;
 671         intel_dp->algo.address = 0;
 672         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 673
 674         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 675         intel_dp->adapter.owner = THIS_MODULE;
 676         intel_dp->adapter.class = I2C_CLASS_DDC;
 677         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 678         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 679         intel_dp->adapter.algo_data = &intel_dp->algo;
 680         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 681
 682         ironlake_edp_panel_vdd_on(intel_dp);
 683         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 684         ironlake_edp_panel_vdd_off(intel_dp, false);
 685         return ret;
 686 }
 687
 688 bool
 689 intel_dp_mode_fixup(struct drm_encoder *encoder,
 690                     const struct drm_display_mode *mode,
 691                     struct drm_display_mode *adjusted_mode)
 692 {
 693         struct drm_device *dev = encoder->dev;
 694         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 695         struct intel_connector *intel_connector = intel_dp->attached_connector;
 696         int lane_count, clock;
 697         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 698         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 699         int bpp, mode_rate;
 700         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 701
 702         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 703                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 704                                        adjusted_mode);
 705                 intel_pch_panel_fitting(dev,
 706                                         intel_connector->panel.fitting_mode,
 707                                         mode, adjusted_mode);
 708         }
 709
 710         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 711                 return false;
 712
 713         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 714                       "max bw %02x pixel clock %iKHz\n",
 715                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 716
 717         if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
 718                 return false;
 719
 720         bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
 721         mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
 722
 723         for (clock = 0; clock <= max_clock; clock++) {
 724                 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 725                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
 726
 727                         if (mode_rate <= link_avail) {
 728                                 intel_dp->link_bw = bws[clock];
 729                                 intel_dp->lane_count = lane_count;
 730                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
 731                                 DRM_DEBUG_KMS("DP link bw %02x lane "
 732                                                 "count %d clock %d bpp %d\n",
 733                                        intel_dp->link_bw, intel_dp->lane_count,
 734                                        adjusted_mode->clock, bpp);
 735                                 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 736                                               mode_rate, link_avail);
 737                                 return true;
 738                         }
 739                 }
 740         }
 741
 742         return false;
 743 }
 744
 745 struct intel_dp_m_n {
 746         uint32_t        tu;
 747         uint32_t        gmch_m;
 748         uint32_t        gmch_n;
 749         uint32_t        link_m;
 750         uint32_t        link_n;
 751 };
 752
 753 static void
 754 intel_reduce_ratio(uint32_t *num, uint32_t *den)
 755 {
 756         while (*num > 0xffffff || *den > 0xffffff) {
 757                 *num >>= 1;
 758                 *den >>= 1;
 759         }
 760 }
 761
 762 static void
 763 intel_dp_compute_m_n(int bpp,
 764                      int nlanes,
 765                      int pixel_clock,
 766                      int link_clock,
 767                      struct intel_dp_m_n *m_n)
 768 {
 769         m_n->tu = 64;
 770         m_n->gmch_m = (pixel_clock * bpp) >> 3;
 771         m_n->gmch_n = link_clock * nlanes;
 772         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
 773         m_n->link_m = pixel_clock;
 774         m_n->link_n = link_clock;
 775         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
 776 }
 777
 778 void
 779 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 780                  struct drm_display_mode *adjusted_mode)
 781 {
 782         struct drm_device *dev = crtc->dev;
 783         struct intel_encoder *intel_encoder;
 784         struct intel_dp *intel_dp;
 785         struct drm_i915_private *dev_priv = dev->dev_private;
 786         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 787         int lane_count = 4;
 788         struct intel_dp_m_n m_n;
 789         int pipe = intel_crtc->pipe;
 790         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 791
 792         /*
 793          * Find the lane count in the intel_encoder private
 794          */
 795         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 796                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
 797
 798                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
 799                     intel_encoder->type == INTEL_OUTPUT_EDP)
 800                 {
 801                         lane_count = intel_dp->lane_count;
 802                         break;
 803                 }
 804         }
 805
 806         /*
 807          * Compute the GMCH and Link ratios. The '3' here is
 808          * the number of bytes_per_pixel post-LUT, which we always
 809          * set up for 8-bits of R/G/B, or 3 bytes total.
 810          */
 811         intel_dp_compute_m_n(intel_crtc->bpp, lane_count,
 812                              mode->clock, adjusted_mode->clock, &m_n);
 813
 814         if (IS_HASWELL(dev)) {
 815                 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
 816                            TU_SIZE(m_n.tu) | m_n.gmch_m);
 817                 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
 818                 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
 819                 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
 820         } else if (HAS_PCH_SPLIT(dev)) {
 821                 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 822                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 823                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 824                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 825         } else if (IS_VALLEYVIEW(dev)) {
 826                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 827                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
 828                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
 829                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
 830         } else {
 831                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 832                            TU_SIZE(m_n.tu) | m_n.gmch_m);
 833                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 834                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 835                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 836         }
 837 }
 838
 839 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 840 {
 841         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 842         intel_dp->link_configuration[0] = intel_dp->link_bw;
 843         intel_dp->link_configuration[1] = intel_dp->lane_count;
 844         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 845         /*
 846          * Check for DPCD version > 1.1 and enhanced framing support
 847          */
 848         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 849             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 850                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 851         }
 852 }
 853
 854 static void
 855 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 856                   struct drm_display_mode *adjusted_mode)
 857 {
 858         struct drm_device *dev = encoder->dev;
 859         struct drm_i915_private *dev_priv = dev->dev_private;
 860         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 861         struct drm_crtc *crtc = encoder->crtc;
 862         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 863
 864         /*
 865          * There are four kinds of DP registers:
 866          *
 867          *      IBX PCH
 868          *      SNB CPU
 869          *      IVB CPU
 870          *      CPT PCH
 871          *
 872          * IBX PCH and CPU are the same for almost everything,
 873          * except that the CPU DP PLL is configured in this
 874          * register
 875          *
 876          * CPT PCH is quite different, having many bits moved
 877          * to the TRANS_DP_CTL register instead. That
 878          * configuration happens (oddly) in ironlake_pch_enable
 879          */
 880
 881         /* Preserve the BIOS-computed detected bit. This is
 882          * supposed to be read-only.
 883          */
 884         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 885
 886         /* Handle DP bits in common between all three register formats */
 887         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 888
 889         switch (intel_dp->lane_count) {
 890         case 1:
 891                 intel_dp->DP |= DP_PORT_WIDTH_1;
 892                 break;
 893         case 2:
 894                 intel_dp->DP |= DP_PORT_WIDTH_2;
 895                 break;
 896         case 4:
 897                 intel_dp->DP |= DP_PORT_WIDTH_4;
 898                 break;
 899         }
 900         if (intel_dp->has_audio) {
 901                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 902                                  pipe_name(intel_crtc->pipe));
 903                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 904                 intel_write_eld(encoder, adjusted_mode);
 905         }
 906
 907         intel_dp_init_link_config(intel_dp);
 908
 909         /* Split out the IBX/CPU vs CPT settings */
 910
 911         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 912                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 913                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 914                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 915                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 916                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 917
 918                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 919                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 920
 921                 intel_dp->DP |= intel_crtc->pipe << 29;
 922
 923                 /* don't miss out required setting for eDP */
 924                 if (adjusted_mode->clock < 200000)
 925                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 926                 else
 927                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 928         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 929                 intel_dp->DP |= intel_dp->color_range;
 930
 931                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 932                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 933                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 934                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 935                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 936
 937                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 938                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 939
 940                 if (intel_crtc->pipe == 1)
 941                         intel_dp->DP |= DP_PIPEB_SELECT;
 942
 943                 if (is_cpu_edp(intel_dp)) {
 944                         /* don't miss out required setting for eDP */
 945                         if (adjusted_mode->clock < 200000)
 946                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 947                         else
 948                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 949                 }
 950         } else {
 951                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 952         }
 953 }
 954
 955 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 956 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
 957
 958 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
 959 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 960
 961 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
 962 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
 963
 964 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
 965                                        u32 mask,
 966                                        u32 value)
 967 {
 968         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 969         struct drm_i915_private *dev_priv = dev->dev_private;
 970
 971         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
 972                       mask, value,
 973                       I915_READ(PCH_PP_STATUS),
 974                       I915_READ(PCH_PP_CONTROL));
 975
 976         if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
 977                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
 978                           I915_READ(PCH_PP_STATUS),
 979                           I915_READ(PCH_PP_CONTROL));
 980         }
 981 }
 982
 983 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
 984 {
 985         DRM_DEBUG_KMS("Wait for panel power on\n");
 986         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
 987 }
 988
 989 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
 990 {
 991         DRM_DEBUG_KMS("Wait for panel power off time\n");
 992         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
 993 }
 994
 995 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
 996 {
 997         DRM_DEBUG_KMS("Wait for panel power cycle\n");
 998         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
 999 }
1000
1001
1002 /* Read the current pp_control value, unlocking the register if it
1003  * is locked
1004  */
1005
1006 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1007 {
1008         u32     control = I915_READ(PCH_PP_CONTROL);
1009
1010         control &= ~PANEL_UNLOCK_MASK;
1011         control |= PANEL_UNLOCK_REGS;
1012         return control;
1013 }
1014
1015 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1016 {
1017         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1018         struct drm_i915_private *dev_priv = dev->dev_private;
1019         u32 pp;
1020
1021         if (!is_edp(intel_dp))
1022                 return;
1023         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1024
1025         WARN(intel_dp->want_panel_vdd,
1026              "eDP VDD already requested on\n");
1027
1028         intel_dp->want_panel_vdd = true;
1029
1030         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1031                 DRM_DEBUG_KMS("eDP VDD already on\n");
1032                 return;
1033         }
1034
1035         if (!ironlake_edp_have_panel_power(intel_dp))
1036                 ironlake_wait_panel_power_cycle(intel_dp);
1037
1038         pp = ironlake_get_pp_control(dev_priv);
1039         pp |= EDP_FORCE_VDD;
1040         I915_WRITE(PCH_PP_CONTROL, pp);
1041         POSTING_READ(PCH_PP_CONTROL);
1042         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1043                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1044
1045         /*
1046          * If the panel wasn't on, delay before accessing aux channel
1047          */
1048         if (!ironlake_edp_have_panel_power(intel_dp)) {
1049                 DRM_DEBUG_KMS("eDP was not running\n");
1050                 msleep(intel_dp->panel_power_up_delay);
1051         }
1052 }
1053
1054 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1055 {
1056         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1057         struct drm_i915_private *dev_priv = dev->dev_private;
1058         u32 pp;
1059
1060         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1061                 pp = ironlake_get_pp_control(dev_priv);
1062                 pp &= ~EDP_FORCE_VDD;
1063                 I915_WRITE(PCH_PP_CONTROL, pp);
1064                 POSTING_READ(PCH_PP_CONTROL);
1065
1066                 /* Make sure sequencer is idle before allowing subsequent activity */
1067                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1068                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1069
1070                 msleep(intel_dp->panel_power_down_delay);
1071         }
1072 }
1073
1074 static void ironlake_panel_vdd_work(struct work_struct *__work)
1075 {
1076         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1077                                                  struct intel_dp, panel_vdd_work);
1078         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1079
1080         mutex_lock(&dev->mode_config.mutex);
1081         ironlake_panel_vdd_off_sync(intel_dp);
1082         mutex_unlock(&dev->mode_config.mutex);
1083 }
1084
1085 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1086 {
1087         if (!is_edp(intel_dp))
1088                 return;
1089
1090         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1091         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1092
1093         intel_dp->want_panel_vdd = false;
1094
1095         if (sync) {
1096                 ironlake_panel_vdd_off_sync(intel_dp);
1097         } else {
1098                 /*
1099                  * Queue the timer to fire a long
1100                  * time from now (relative to the power down delay)
1101                  * to keep the panel power up across a sequence of operations
1102                  */
1103                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1104                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1105         }
1106 }
1107
1108 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1109 {
1110         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1111         struct drm_i915_private *dev_priv = dev->dev_private;
1112         u32 pp;
1113
1114         if (!is_edp(intel_dp))
1115                 return;
1116
1117         DRM_DEBUG_KMS("Turn eDP power on\n");
1118
1119         if (ironlake_edp_have_panel_power(intel_dp)) {
1120                 DRM_DEBUG_KMS("eDP power already on\n");
1121                 return;
1122         }
1123
1124         ironlake_wait_panel_power_cycle(intel_dp);
1125
1126         pp = ironlake_get_pp_control(dev_priv);
1127         if (IS_GEN5(dev)) {
1128                 /* ILK workaround: disable reset around power sequence */
1129                 pp &= ~PANEL_POWER_RESET;
1130                 I915_WRITE(PCH_PP_CONTROL, pp);
1131                 POSTING_READ(PCH_PP_CONTROL);
1132         }
1133
1134         pp |= POWER_TARGET_ON;
1135         if (!IS_GEN5(dev))
1136                 pp |= PANEL_POWER_RESET;
1137
1138         I915_WRITE(PCH_PP_CONTROL, pp);
1139         POSTING_READ(PCH_PP_CONTROL);
1140
1141         ironlake_wait_panel_on(intel_dp);
1142
1143         if (IS_GEN5(dev)) {
1144                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1145                 I915_WRITE(PCH_PP_CONTROL, pp);
1146                 POSTING_READ(PCH_PP_CONTROL);
1147         }
1148 }
1149
1150 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1151 {
1152         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1153         struct drm_i915_private *dev_priv = dev->dev_private;
1154         u32 pp;
1155
1156         if (!is_edp(intel_dp))
1157                 return;
1158
1159         DRM_DEBUG_KMS("Turn eDP power off\n");
1160
1161         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1162
1163         pp = ironlake_get_pp_control(dev_priv);
1164         /* We need to switch off panel power _and_ force vdd, for otherwise some
1165          * panels get very unhappy and cease to work. */
1166         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1167         I915_WRITE(PCH_PP_CONTROL, pp);
1168         POSTING_READ(PCH_PP_CONTROL);
1169
1170         intel_dp->want_panel_vdd = false;
1171
1172         ironlake_wait_panel_off(intel_dp);
1173 }
1174
1175 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1176 {
1177         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1178         struct drm_device *dev = intel_dig_port->base.base.dev;
1179         struct drm_i915_private *dev_priv = dev->dev_private;
1180         int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1181         u32 pp;
1182
1183         if (!is_edp(intel_dp))
1184                 return;
1185
1186         DRM_DEBUG_KMS("\n");
1187         /*
1188          * If we enable the backlight right away following a panel power
1189          * on, we may see slight flicker as the panel syncs with the eDP
1190          * link.  So delay a bit to make sure the image is solid before
1191          * allowing it to appear.
1192          */
1193         msleep(intel_dp->backlight_on_delay);
1194         pp = ironlake_get_pp_control(dev_priv);
1195         pp |= EDP_BLC_ENABLE;
1196         I915_WRITE(PCH_PP_CONTROL, pp);
1197         POSTING_READ(PCH_PP_CONTROL);
1198
1199         intel_panel_enable_backlight(dev, pipe);
1200 }
1201
1202 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1203 {
1204         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1205         struct drm_i915_private *dev_priv = dev->dev_private;
1206         u32 pp;
1207
1208         if (!is_edp(intel_dp))
1209                 return;
1210
1211         intel_panel_disable_backlight(dev);
1212
1213         DRM_DEBUG_KMS("\n");
1214         pp = ironlake_get_pp_control(dev_priv);
1215         pp &= ~EDP_BLC_ENABLE;
1216         I915_WRITE(PCH_PP_CONTROL, pp);
1217         POSTING_READ(PCH_PP_CONTROL);
1218         msleep(intel_dp->backlight_off_delay);
1219 }
1220
1221 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1222 {
1223         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1224         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1225         struct drm_device *dev = crtc->dev;
1226         struct drm_i915_private *dev_priv = dev->dev_private;
1227         u32 dpa_ctl;
1228
1229         assert_pipe_disabled(dev_priv,
1230                              to_intel_crtc(crtc)->pipe);
1231
1232         DRM_DEBUG_KMS("\n");
1233         dpa_ctl = I915_READ(DP_A);
1234         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1235         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1236
1237         /* We don't adjust intel_dp->DP while tearing down the link, to
1238          * facilitate link retraining (e.g. after hotplug). Hence clear all
1239          * enable bits here to ensure that we don't enable too much. */
1240         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1241         intel_dp->DP |= DP_PLL_ENABLE;
1242         I915_WRITE(DP_A, intel_dp->DP);
1243         POSTING_READ(DP_A);
1244         udelay(200);
1245 }
1246
1247 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1248 {
1249         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1250         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1251         struct drm_device *dev = crtc->dev;
1252         struct drm_i915_private *dev_priv = dev->dev_private;
1253         u32 dpa_ctl;
1254
1255         assert_pipe_disabled(dev_priv,
1256                              to_intel_crtc(crtc)->pipe);
1257
1258         dpa_ctl = I915_READ(DP_A);
1259         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1260              "dp pll off, should be on\n");
1261         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1262
1263         /* We can't rely on the value tracked for the DP register in
1264          * intel_dp->DP because link_down must not change that (otherwise link
1265          * re-training will fail. */
1266         dpa_ctl &= ~DP_PLL_ENABLE;
1267         I915_WRITE(DP_A, dpa_ctl);
1268         POSTING_READ(DP_A);
1269         udelay(200);
1270 }
1271
1272 /* If the sink supports it, try to set the power state appropriately */
1273 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1274 {
1275         int ret, i;
1276
1277         /* Should have a valid DPCD by this point */
1278         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1279                 return;
1280
1281         if (mode != DRM_MODE_DPMS_ON) {
1282                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1283                                                   DP_SET_POWER_D3);
1284                 if (ret != 1)
1285                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1286         } else {
1287                 /*
1288                  * When turning on, we need to retry for 1ms to give the sink
1289                  * time to wake up.
1290                  */
1291                 for (i = 0; i < 3; i++) {
1292                         ret = intel_dp_aux_native_write_1(intel_dp,
1293                                                           DP_SET_POWER,
1294                                                           DP_SET_POWER_D0);
1295                         if (ret == 1)
1296                                 break;
1297                         msleep(1);
1298                 }
1299         }
1300 }
1301
1302 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1303                                   enum pipe *pipe)
1304 {
1305         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1306         struct drm_device *dev = encoder->base.dev;
1307         struct drm_i915_private *dev_priv = dev->dev_private;
1308         u32 tmp = I915_READ(intel_dp->output_reg);
1309
1310         if (!(tmp & DP_PORT_EN))
1311                 return false;
1312
1313         if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1314                 *pipe = PORT_TO_PIPE_CPT(tmp);
1315         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1316                 *pipe = PORT_TO_PIPE(tmp);
1317         } else {
1318                 u32 trans_sel;
1319                 u32 trans_dp;
1320                 int i;
1321
1322                 switch (intel_dp->output_reg) {
1323                 case PCH_DP_B:
1324                         trans_sel = TRANS_DP_PORT_SEL_B;
1325                         break;
1326                 case PCH_DP_C:
1327                         trans_sel = TRANS_DP_PORT_SEL_C;
1328                         break;
1329                 case PCH_DP_D:
1330                         trans_sel = TRANS_DP_PORT_SEL_D;
1331                         break;
1332                 default:
1333                         return true;
1334                 }
1335
1336                 for_each_pipe(i) {
1337                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1338                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1339                                 *pipe = i;
1340                                 return true;
1341                         }
1342                 }
1343
1344                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1345                               intel_dp->output_reg);
1346         }
1347
1348         return true;
1349 }
1350
1351 static void intel_disable_dp(struct intel_encoder *encoder)
1352 {
1353         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1354
1355         /* Make sure the panel is off before trying to change the mode. But also
1356          * ensure that we have vdd while we switch off the panel. */
1357         ironlake_edp_panel_vdd_on(intel_dp);
1358         ironlake_edp_backlight_off(intel_dp);
1359         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1360         ironlake_edp_panel_off(intel_dp);
1361
1362         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1363         if (!is_cpu_edp(intel_dp))
1364                 intel_dp_link_down(intel_dp);
1365 }
1366
1367 static void intel_post_disable_dp(struct intel_encoder *encoder)
1368 {
1369         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1370
1371         if (is_cpu_edp(intel_dp)) {
1372                 intel_dp_link_down(intel_dp);
1373                 ironlake_edp_pll_off(intel_dp);
1374         }
1375 }
1376
1377 static void intel_enable_dp(struct intel_encoder *encoder)
1378 {
1379         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1380         struct drm_device *dev = encoder->base.dev;
1381         struct drm_i915_private *dev_priv = dev->dev_private;
1382         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1383
1384         if (WARN_ON(dp_reg & DP_PORT_EN))
1385                 return;
1386
1387         ironlake_edp_panel_vdd_on(intel_dp);
1388         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1389         intel_dp_start_link_train(intel_dp);
1390         ironlake_edp_panel_on(intel_dp);
1391         ironlake_edp_panel_vdd_off(intel_dp, true);
1392         intel_dp_complete_link_train(intel_dp);
1393         ironlake_edp_backlight_on(intel_dp);
1394 }
1395
1396 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1397 {
1398         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1399
1400         if (is_cpu_edp(intel_dp))
1401                 ironlake_edp_pll_on(intel_dp);
1402 }
1403
1404 /*
1405  * Native read with retry for link status and receiver capability reads for
1406  * cases where the sink may still be asleep.
1407  */
1408 static bool
1409 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1410                                uint8_t *recv, int recv_bytes)
1411 {
1412         int ret, i;
1413
1414         /*
1415          * Sinks are *supposed* to come up within 1ms from an off state,
1416          * but we're also supposed to retry 3 times per the spec.
1417          */
1418         for (i = 0; i < 3; i++) {
1419                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1420                                                recv_bytes);
1421                 if (ret == recv_bytes)
1422                         return true;
1423                 msleep(1);
1424         }
1425
1426         return false;
1427 }
1428
1429 /*
1430  * Fetch AUX CH registers 0x202 - 0x207 which contain
1431  * link status information
1432  */
1433 static bool
1434 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1435 {
1436         return intel_dp_aux_native_read_retry(intel_dp,
1437                                               DP_LANE0_1_STATUS,
1438                                               link_status,
1439                                               DP_LINK_STATUS_SIZE);
1440 }
1441
1442 #if 0
1443 static char     *voltage_names[] = {
1444         "0.4V", "0.6V", "0.8V", "1.2V"
1445 };
1446 static char     *pre_emph_names[] = {
1447         "0dB", "3.5dB", "6dB", "9.5dB"
1448 };
1449 static char     *link_train_names[] = {
1450         "pattern 1", "pattern 2", "idle", "off"
1451 };
1452 #endif
1453
1454 /*
1455  * These are source-specific values; current Intel hardware supports
1456  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1457  */
1458
1459 static uint8_t
1460 intel_dp_voltage_max(struct intel_dp *intel_dp)
1461 {
1462         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1463
1464         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1465                 return DP_TRAIN_VOLTAGE_SWING_800;
1466         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1467                 return DP_TRAIN_VOLTAGE_SWING_1200;
1468         else
1469                 return DP_TRAIN_VOLTAGE_SWING_800;
1470 }
1471
1472 static uint8_t
1473 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1474 {
1475         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1476
1477         if (IS_HASWELL(dev)) {
1478                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1479                 case DP_TRAIN_VOLTAGE_SWING_400:
1480                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1481                 case DP_TRAIN_VOLTAGE_SWING_600:
1482                         return DP_TRAIN_PRE_EMPHASIS_6;
1483                 case DP_TRAIN_VOLTAGE_SWING_800:
1484                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1485                 case DP_TRAIN_VOLTAGE_SWING_1200:
1486                 default:
1487                         return DP_TRAIN_PRE_EMPHASIS_0;
1488                 }
1489         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1490                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1491                 case DP_TRAIN_VOLTAGE_SWING_400:
1492                         return DP_TRAIN_PRE_EMPHASIS_6;
1493                 case DP_TRAIN_VOLTAGE_SWING_600:
1494                 case DP_TRAIN_VOLTAGE_SWING_800:
1495                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1496                 default:
1497                         return DP_TRAIN_PRE_EMPHASIS_0;
1498                 }
1499         } else {
1500                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1501                 case DP_TRAIN_VOLTAGE_SWING_400:
1502                         return DP_TRAIN_PRE_EMPHASIS_6;
1503                 case DP_TRAIN_VOLTAGE_SWING_600:
1504                         return DP_TRAIN_PRE_EMPHASIS_6;
1505                 case DP_TRAIN_VOLTAGE_SWING_800:
1506                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1507                 case DP_TRAIN_VOLTAGE_SWING_1200:
1508                 default:
1509                         return DP_TRAIN_PRE_EMPHASIS_0;
1510                 }
1511         }
1512 }
1513
1514 static void
1515 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1516 {
1517         uint8_t v = 0;
1518         uint8_t p = 0;
1519         int lane;
1520         uint8_t voltage_max;
1521         uint8_t preemph_max;
1522
1523         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1524                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1525                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1526
1527                 if (this_v > v)
1528                         v = this_v;
1529                 if (this_p > p)
1530                         p = this_p;
1531         }
1532
1533         voltage_max = intel_dp_voltage_max(intel_dp);
1534         if (v >= voltage_max)
1535                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1536
1537         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1538         if (p >= preemph_max)
1539                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1540
1541         for (lane = 0; lane < 4; lane++)
1542                 intel_dp->train_set[lane] = v | p;
1543 }
1544
1545 static uint32_t
1546 intel_dp_signal_levels(uint8_t train_set)
1547 {
1548         uint32_t        signal_levels = 0;
1549
1550         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1551         case DP_TRAIN_VOLTAGE_SWING_400:
1552         default:
1553                 signal_levels |= DP_VOLTAGE_0_4;
1554                 break;
1555         case DP_TRAIN_VOLTAGE_SWING_600:
1556                 signal_levels |= DP_VOLTAGE_0_6;
1557                 break;
1558         case DP_TRAIN_VOLTAGE_SWING_800:
1559                 signal_levels |= DP_VOLTAGE_0_8;
1560                 break;
1561         case DP_TRAIN_VOLTAGE_SWING_1200:
1562                 signal_levels |= DP_VOLTAGE_1_2;
1563                 break;
1564         }
1565         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1566         case DP_TRAIN_PRE_EMPHASIS_0:
1567         default:
1568                 signal_levels |= DP_PRE_EMPHASIS_0;
1569                 break;
1570         case DP_TRAIN_PRE_EMPHASIS_3_5:
1571                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1572                 break;
1573         case DP_TRAIN_PRE_EMPHASIS_6:
1574                 signal_levels |= DP_PRE_EMPHASIS_6;
1575                 break;
1576         case DP_TRAIN_PRE_EMPHASIS_9_5:
1577                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1578                 break;
1579         }
1580         return signal_levels;
1581 }
1582
1583 /* Gen6's DP voltage swing and pre-emphasis control */
1584 static uint32_t
1585 intel_gen6_edp_signal_levels(uint8_t train_set)
1586 {
1587         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1588                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1589         switch (signal_levels) {
1590         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1591         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1592                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1593         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1594                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1595         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1596         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1597                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1598         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1599         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1600                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1601         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1602         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1603                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1604         default:
1605                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1606                               "0x%x\n", signal_levels);
1607                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1608         }
1609 }
1610
1611 /* Gen7's DP voltage swing and pre-emphasis control */
1612 static uint32_t
1613 intel_gen7_edp_signal_levels(uint8_t train_set)
1614 {
1615         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1616                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1617         switch (signal_levels) {
1618         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1619                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1620         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1621                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1622         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1623                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1624
1625         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1626                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1627         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1628                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1629
1630         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1631                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1632         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1633                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1634
1635         default:
1636                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1637                               "0x%x\n", signal_levels);
1638                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1639         }
1640 }
1641
1642 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1643 static uint32_t
1644 intel_dp_signal_levels_hsw(uint8_t train_set)
1645 {
1646         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1647                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1648         switch (signal_levels) {
1649         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1650                 return DDI_BUF_EMP_400MV_0DB_HSW;
1651         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1652                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1653         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1654                 return DDI_BUF_EMP_400MV_6DB_HSW;
1655         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1656                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1657
1658         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1659                 return DDI_BUF_EMP_600MV_0DB_HSW;
1660         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1661                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1662         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1663                 return DDI_BUF_EMP_600MV_6DB_HSW;
1664
1665         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1666                 return DDI_BUF_EMP_800MV_0DB_HSW;
1667         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1668                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1669         default:
1670                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1671                               "0x%x\n", signal_levels);
1672                 return DDI_BUF_EMP_400MV_0DB_HSW;
1673         }
1674 }
1675
1676 static bool
1677 intel_dp_set_link_train(struct intel_dp *intel_dp,
1678                         uint32_t dp_reg_value,
1679                         uint8_t dp_train_pat)
1680 {
1681         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1682         struct drm_device *dev = intel_dig_port->base.base.dev;
1683         struct drm_i915_private *dev_priv = dev->dev_private;
1684         enum port port = intel_dig_port->port;
1685         int ret;
1686         uint32_t temp;
1687
1688         if (IS_HASWELL(dev)) {
1689                 temp = I915_READ(DP_TP_CTL(port));
1690
1691                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1692                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1693                 else
1694                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1695
1696                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1697                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1698                 case DP_TRAINING_PATTERN_DISABLE:
1699                         temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1700                         I915_WRITE(DP_TP_CTL(port), temp);
1701
1702                         if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1703                                       DP_TP_STATUS_IDLE_DONE), 1))
1704                                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1705
1706                         temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1707                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1708
1709                         break;
1710                 case DP_TRAINING_PATTERN_1:
1711                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1712                         break;
1713                 case DP_TRAINING_PATTERN_2:
1714                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1715                         break;
1716                 case DP_TRAINING_PATTERN_3:
1717                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1718                         break;
1719                 }
1720                 I915_WRITE(DP_TP_CTL(port), temp);
1721
1722         } else if (HAS_PCH_CPT(dev) &&
1723                    (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1724                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1725
1726                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1727                 case DP_TRAINING_PATTERN_DISABLE:
1728                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1729                         break;
1730                 case DP_TRAINING_PATTERN_1:
1731                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1732                         break;
1733                 case DP_TRAINING_PATTERN_2:
1734                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1735                         break;
1736                 case DP_TRAINING_PATTERN_3:
1737                         DRM_ERROR("DP training pattern 3 not supported\n");
1738                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1739                         break;
1740                 }
1741
1742         } else {
1743                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1744
1745                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1746                 case DP_TRAINING_PATTERN_DISABLE:
1747                         dp_reg_value |= DP_LINK_TRAIN_OFF;
1748                         break;
1749                 case DP_TRAINING_PATTERN_1:
1750                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1751                         break;
1752                 case DP_TRAINING_PATTERN_2:
1753                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1754                         break;
1755                 case DP_TRAINING_PATTERN_3:
1756                         DRM_ERROR("DP training pattern 3 not supported\n");
1757                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1758                         break;
1759                 }
1760         }
1761
1762         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1763         POSTING_READ(intel_dp->output_reg);
1764
1765         intel_dp_aux_native_write_1(intel_dp,
1766                                     DP_TRAINING_PATTERN_SET,
1767                                     dp_train_pat);
1768
1769         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1770             DP_TRAINING_PATTERN_DISABLE) {
1771                 ret = intel_dp_aux_native_write(intel_dp,
1772                                                 DP_TRAINING_LANE0_SET,
1773                                                 intel_dp->train_set,
1774                                                 intel_dp->lane_count);
1775                 if (ret != intel_dp->lane_count)
1776                         return false;
1777         }
1778
1779         return true;
1780 }
1781
1782 /* Enable corresponding port and start training pattern 1 */
1783 void
1784 intel_dp_start_link_train(struct intel_dp *intel_dp)
1785 {
1786         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1787         struct drm_device *dev = encoder->dev;
1788         int i;
1789         uint8_t voltage;
1790         bool clock_recovery = false;
1791         int voltage_tries, loop_tries;
1792         uint32_t DP = intel_dp->DP;
1793
1794         if (IS_HASWELL(dev))
1795                 intel_ddi_prepare_link_retrain(encoder);
1796
1797         /* Write the link configuration data */
1798         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1799                                   intel_dp->link_configuration,
1800                                   DP_LINK_CONFIGURATION_SIZE);
1801
1802         DP |= DP_PORT_EN;
1803
1804         memset(intel_dp->train_set, 0, 4);
1805         voltage = 0xff;
1806         voltage_tries = 0;
1807         loop_tries = 0;
1808         clock_recovery = false;
1809         for (;;) {
1810                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1811                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1812                 uint32_t    signal_levels;
1813
1814                 if (IS_HASWELL(dev)) {
1815                         signal_levels = intel_dp_signal_levels_hsw(
1816                                                         intel_dp->train_set[0]);
1817                         DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1818                 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1819                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1820                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1821                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1822                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1823                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1824                 } else {
1825                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1826                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1827                 }
1828                 DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n",
1829                               signal_levels);
1830
1831                 /* Set training pattern 1 */
1832                 if (!intel_dp_set_link_train(intel_dp, DP,
1833                                              DP_TRAINING_PATTERN_1 |
1834                                              DP_LINK_SCRAMBLING_DISABLE))
1835                         break;
1836
1837                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1838                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1839                         DRM_ERROR("failed to get link status\n");
1840                         break;
1841                 }
1842
1843                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1844                         DRM_DEBUG_KMS("clock recovery OK\n");
1845                         clock_recovery = true;
1846                         break;
1847                 }
1848
1849                 /* Check to see if we've tried the max voltage */
1850                 for (i = 0; i < intel_dp->lane_count; i++)
1851                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1852                                 break;
1853                 if (i == intel_dp->lane_count && voltage_tries == 5) {
1854                         if (++loop_tries == 5) {
1855                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1856                                 break;
1857                         }
1858                         memset(intel_dp->train_set, 0, 4);
1859                         voltage_tries = 0;
1860                         continue;
1861                 }
1862
1863                 /* Check to see if we've tried the same voltage 5 times */
1864                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
1865                         voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1866                         voltage_tries = 0;
1867                 } else
1868                         ++voltage_tries;
1869
1870                 /* Compute new intel_dp->train_set as requested by target */
1871                 intel_get_adjust_train(intel_dp, link_status);
1872         }
1873
1874         intel_dp->DP = DP;
1875 }
1876
1877 void
1878 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1879 {
1880         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1881         bool channel_eq = false;
1882         int tries, cr_tries;
1883         uint32_t DP = intel_dp->DP;
1884
1885         /* channel equalization */
1886         tries = 0;
1887         cr_tries = 0;
1888         channel_eq = false;
1889         for (;;) {
1890                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1891                 uint32_t    signal_levels;
1892                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1893
1894                 if (cr_tries > 5) {
1895                         DRM_ERROR("failed to train DP, aborting\n");
1896                         intel_dp_link_down(intel_dp);
1897                         break;
1898                 }
1899
1900                 if (IS_HASWELL(dev)) {
1901                         signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]);
1902                         DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels;
1903                 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1904                         signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]);
1905                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels;
1906                 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1907                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1908                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1909                 } else {
1910                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]);
1911                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1912                 }
1913
1914                 /* channel eq pattern */
1915                 if (!intel_dp_set_link_train(intel_dp, DP,
1916                                              DP_TRAINING_PATTERN_2 |
1917                                              DP_LINK_SCRAMBLING_DISABLE))
1918                         break;
1919
1920                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1921                 if (!intel_dp_get_link_status(intel_dp, link_status))
1922                         break;
1923
1924                 /* Make sure clock is still ok */
1925                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1926                         intel_dp_start_link_train(intel_dp);
1927                         cr_tries++;
1928                         continue;
1929                 }
1930
1931                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
1932                         channel_eq = true;
1933                         break;
1934                 }
1935
1936                 /* Try 5 times, then try clock recovery if that fails */
1937                 if (tries > 5) {
1938                         intel_dp_link_down(intel_dp);
1939                         intel_dp_start_link_train(intel_dp);
1940                         tries = 0;
1941                         cr_tries++;
1942                         continue;
1943                 }
1944
1945                 /* Compute new intel_dp->train_set as requested by target */
1946                 intel_get_adjust_train(intel_dp, link_status);
1947                 ++tries;
1948         }
1949
1950         if (channel_eq)
1951                 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
1952
1953         intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
1954 }
1955
1956 static void
1957 intel_dp_link_down(struct intel_dp *intel_dp)
1958 {
1959         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1960         struct drm_device *dev = intel_dig_port->base.base.dev;
1961         struct drm_i915_private *dev_priv = dev->dev_private;
1962         uint32_t DP = intel_dp->DP;
1963
1964         /*
1965          * DDI code has a strict mode set sequence and we should try to respect
1966          * it, otherwise we might hang the machine in many different ways. So we
1967          * really should be disabling the port only on a complete crtc_disable
1968          * sequence. This function is just called under two conditions on DDI
1969          * code:
1970          * - Link train failed while doing crtc_enable, and on this case we
1971          *   really should respect the mode set sequence and wait for a
1972          *   crtc_disable.
1973          * - Someone turned the monitor off and intel_dp_check_link_status
1974          *   called us. We don't need to disable the whole port on this case, so
1975          *   when someone turns the monitor on again,
1976          *   intel_ddi_prepare_link_retrain will take care of redoing the link
1977          *   train.
1978          */
1979         if (IS_HASWELL(dev))
1980                 return;
1981
1982         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
1983                 return;
1984
1985         DRM_DEBUG_KMS("\n");
1986
1987         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1988                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1989                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1990         } else {
1991                 DP &= ~DP_LINK_TRAIN_MASK;
1992                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1993         }
1994         POSTING_READ(intel_dp->output_reg);
1995
1996         msleep(17);
1997
1998         if (HAS_PCH_IBX(dev) &&
1999             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2000                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2001
2002                 /* Hardware workaround: leaving our transcoder select
2003                  * set to transcoder B while it's off will prevent the
2004                  * corresponding HDMI output on transcoder A.
2005                  *
2006                  * Combine this with another hardware workaround:
2007                  * transcoder select bit can only be cleared while the
2008                  * port is enabled.
2009                  */
2010                 DP &= ~DP_PIPEB_SELECT;
2011                 I915_WRITE(intel_dp->output_reg, DP);
2012
2013                 /* Changes to enable or select take place the vblank
2014                  * after being written.
2015                  */
2016                 if (crtc == NULL) {
2017                         /* We can arrive here never having been attached
2018                          * to a CRTC, for instance, due to inheriting
2019                          * random state from the BIOS.
2020                          *
2021                          * If the pipe is not running, play safe and
2022                          * wait for the clocks to stabilise before
2023                          * continuing.
2024                          */
2025                         POSTING_READ(intel_dp->output_reg);
2026                         msleep(50);
2027                 } else
2028                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
2029         }
2030
2031         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2032         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2033         POSTING_READ(intel_dp->output_reg);
2034         msleep(intel_dp->panel_power_down_delay);
2035 }
2036
2037 static bool
2038 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2039 {
2040         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2041                                            sizeof(intel_dp->dpcd)) == 0)
2042                 return false; /* aux transfer failed */
2043
2044         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2045                 return false; /* DPCD not present */
2046
2047         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2048               DP_DWN_STRM_PORT_PRESENT))
2049                 return true; /* native DP sink */
2050
2051         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2052                 return true; /* no per-port downstream info */
2053
2054         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2055                                            intel_dp->downstream_ports,
2056                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2057                 return false; /* downstream port status fetch failed */
2058
2059         return true;
2060 }
2061
2062 static void
2063 intel_dp_probe_oui(struct intel_dp *intel_dp)
2064 {
2065         u8 buf[3];
2066
2067         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2068                 return;
2069
2070         ironlake_edp_panel_vdd_on(intel_dp);
2071
2072         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2073                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2074                               buf[0], buf[1], buf[2]);
2075
2076         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2077                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2078                               buf[0], buf[1], buf[2]);
2079
2080         ironlake_edp_panel_vdd_off(intel_dp, false);
2081 }
2082
2083 static bool
2084 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2085 {
2086         int ret;
2087
2088         ret = intel_dp_aux_native_read_retry(intel_dp,
2089                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2090                                              sink_irq_vector, 1);
2091         if (!ret)
2092                 return false;
2093
2094         return true;
2095 }
2096
2097 static void
2098 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2099 {
2100         /* NAK by default */
2101         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2102 }
2103
2104 /*
2105  * According to DP spec
2106  * 5.1.2:
2107  *  1. Read DPCD
2108  *  2. Configure link according to Receiver Capabilities
2109  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2110  *  4. Check link status on receipt of hot-plug interrupt
2111  */
2112
2113 void
2114 intel_dp_check_link_status(struct intel_dp *intel_dp)
2115 {
2116         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2117         u8 sink_irq_vector;
2118         u8 link_status[DP_LINK_STATUS_SIZE];
2119
2120         if (!intel_encoder->connectors_active)
2121                 return;
2122
2123         if (WARN_ON(!intel_encoder->base.crtc))
2124                 return;
2125
2126         /* Try to read receiver status if the link appears to be up */
2127         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2128                 intel_dp_link_down(intel_dp);
2129                 return;
2130         }
2131
2132         /* Now read the DPCD to see if it's actually running */
2133         if (!intel_dp_get_dpcd(intel_dp)) {
2134                 intel_dp_link_down(intel_dp);
2135                 return;
2136         }
2137
2138         /* Try to read the source of the interrupt */
2139         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2140             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2141                 /* Clear interrupt source */
2142                 intel_dp_aux_native_write_1(intel_dp,
2143                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2144                                             sink_irq_vector);
2145
2146                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2147                         intel_dp_handle_test_request(intel_dp);
2148                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2149                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2150         }
2151
2152         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2153                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2154                               drm_get_encoder_name(&intel_encoder->base));
2155                 intel_dp_start_link_train(intel_dp);
2156                 intel_dp_complete_link_train(intel_dp);
2157         }
2158 }
2159
2160 /* XXX this is probably wrong for multiple downstream ports */
2161 static enum drm_connector_status
2162 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2163 {
2164         uint8_t *dpcd = intel_dp->dpcd;
2165         bool hpd;
2166         uint8_t type;
2167
2168         if (!intel_dp_get_dpcd(intel_dp))
2169                 return connector_status_disconnected;
2170
2171         /* if there's no downstream port, we're done */
2172         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2173                 return connector_status_connected;
2174
2175         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2176         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2177         if (hpd) {
2178                 uint8_t reg;
2179                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2180                                                     &reg, 1))
2181                         return connector_status_unknown;
2182                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2183                                               : connector_status_disconnected;
2184         }
2185
2186         /* If no HPD, poke DDC gently */
2187         if (drm_probe_ddc(&intel_dp->adapter))
2188                 return connector_status_connected;
2189
2190         /* Well we tried, say unknown for unreliable port types */
2191         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2192         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2193                 return connector_status_unknown;
2194
2195         /* Anything else is out of spec, warn and ignore */
2196         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2197         return connector_status_disconnected;
2198 }
2199
2200 static enum drm_connector_status
2201 ironlake_dp_detect(struct intel_dp *intel_dp)
2202 {
2203         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2204         enum drm_connector_status status;
2205
2206         /* Can't disconnect eDP, but you can close the lid... */
2207         if (is_edp(intel_dp)) {
2208                 status = intel_panel_detect(dev);
2209                 if (status == connector_status_unknown)
2210                         status = connector_status_connected;
2211                 return status;
2212         }
2213
2214         return intel_dp_detect_dpcd(intel_dp);
2215 }
2216
2217 static enum drm_connector_status
2218 g4x_dp_detect(struct intel_dp *intel_dp)
2219 {
2220         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2221         struct drm_i915_private *dev_priv = dev->dev_private;
2222         uint32_t bit;
2223
2224         switch (intel_dp->output_reg) {
2225         case DP_B:
2226                 bit = DPB_HOTPLUG_LIVE_STATUS;
2227                 break;
2228         case DP_C:
2229                 bit = DPC_HOTPLUG_LIVE_STATUS;
2230                 break;
2231         case DP_D:
2232                 bit = DPD_HOTPLUG_LIVE_STATUS;
2233                 break;
2234         default:
2235                 return connector_status_unknown;
2236         }
2237
2238         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2239                 return connector_status_disconnected;
2240
2241         return intel_dp_detect_dpcd(intel_dp);
2242 }
2243
2244 static struct edid *
2245 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2246 {
2247         struct intel_connector *intel_connector = to_intel_connector(connector);
2248
2249         /* use cached edid if we have one */
2250         if (intel_connector->edid) {
2251                 struct edid *edid;
2252                 int size;
2253
2254                 /* invalid edid */
2255                 if (IS_ERR(intel_connector->edid))
2256                         return NULL;
2257
2258                 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2259                 edid = kmalloc(size, GFP_KERNEL);
2260                 if (!edid)
2261                         return NULL;
2262
2263                 memcpy(edid, intel_connector->edid, size);
2264                 return edid;
2265         }
2266
2267         return drm_get_edid(connector, adapter);
2268 }
2269
2270 static int
2271 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2272 {
2273         struct intel_connector *intel_connector = to_intel_connector(connector);
2274
2275         /* use cached edid if we have one */
2276         if (intel_connector->edid) {
2277                 /* invalid edid */
2278                 if (IS_ERR(intel_connector->edid))
2279                         return 0;
2280
2281                 return intel_connector_update_modes(connector,
2282                                                     intel_connector->edid);
2283         }
2284
2285         return intel_ddc_get_modes(connector, adapter);
2286 }
2287
2288
2289 /**
2290  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
2291  *
2292  * \return true if DP port is connected.
2293  * \return false if DP port is disconnected.
2294  */
2295 static enum drm_connector_status
2296 intel_dp_detect(struct drm_connector *connector, bool force)
2297 {
2298         struct intel_dp *intel_dp = intel_attached_dp(connector);
2299         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2300         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2301         struct drm_device *dev = connector->dev;
2302         enum drm_connector_status status;
2303         struct edid *edid = NULL;
2304         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2305
2306         intel_dp->has_audio = false;
2307
2308         if (HAS_PCH_SPLIT(dev))
2309                 status = ironlake_dp_detect(intel_dp);
2310         else
2311                 status = g4x_dp_detect(intel_dp);
2312
2313         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2314                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2315         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2316
2317         if (status != connector_status_connected)
2318                 return status;
2319
2320         intel_dp_probe_oui(intel_dp);
2321
2322         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2323                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2324         } else {
2325                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2326                 if (edid) {
2327                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2328                         kfree(edid);
2329                 }
2330         }
2331
2332         if (intel_encoder->type != INTEL_OUTPUT_EDP)
2333                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2334         return connector_status_connected;
2335 }
2336
2337 static int intel_dp_get_modes(struct drm_connector *connector)
2338 {
2339         struct intel_dp *intel_dp = intel_attached_dp(connector);
2340         struct intel_connector *intel_connector = to_intel_connector(connector);
2341         struct drm_device *dev = connector->dev;
2342         int ret;
2343
2344         /* We should parse the EDID data and find out if it has an audio sink
2345          */
2346
2347         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2348         if (ret)
2349                 return ret;
2350
2351         /* if eDP has no EDID, fall back to fixed mode */
2352         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2353                 struct drm_display_mode *mode;
2354                 mode = drm_mode_duplicate(dev,
2355                                           intel_connector->panel.fixed_mode);
2356                 if (mode) {
2357                         drm_mode_probed_add(connector, mode);
2358                         return 1;
2359                 }
2360         }
2361         return 0;
2362 }
2363
2364 static bool
2365 intel_dp_detect_audio(struct drm_connector *connector)
2366 {
2367         struct intel_dp *intel_dp = intel_attached_dp(connector);
2368         struct edid *edid;
2369         bool has_audio = false;
2370
2371         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2372         if (edid) {
2373                 has_audio = drm_detect_monitor_audio(edid);
2374                 kfree(edid);
2375         }
2376
2377         return has_audio;
2378 }
2379
2380 static int
2381 intel_dp_set_property(struct drm_connector *connector,
2382                       struct drm_property *property,
2383                       uint64_t val)
2384 {
2385         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2386         struct intel_connector *intel_connector = to_intel_connector(connector);
2387         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2388         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2389         int ret;
2390
2391         ret = drm_connector_property_set_value(connector, property, val);
2392         if (ret)
2393                 return ret;
2394
2395         if (property == dev_priv->force_audio_property) {
2396                 int i = val;
2397                 bool has_audio;
2398
2399                 if (i == intel_dp->force_audio)
2400                         return 0;
2401
2402                 intel_dp->force_audio = i;
2403
2404                 if (i == HDMI_AUDIO_AUTO)
2405                         has_audio = intel_dp_detect_audio(connector);
2406                 else
2407                         has_audio = (i == HDMI_AUDIO_ON);
2408
2409                 if (has_audio == intel_dp->has_audio)
2410                         return 0;
2411
2412                 intel_dp->has_audio = has_audio;
2413                 goto done;
2414         }
2415
2416         if (property == dev_priv->broadcast_rgb_property) {
2417                 if (val == !!intel_dp->color_range)
2418                         return 0;
2419
2420                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
2421                 goto done;
2422         }
2423
2424         if (is_edp(intel_dp) &&
2425             property == connector->dev->mode_config.scaling_mode_property) {
2426                 if (val == DRM_MODE_SCALE_NONE) {
2427                         DRM_DEBUG_KMS("no scaling not supported\n");
2428                         return -EINVAL;
2429                 }
2430
2431                 if (intel_connector->panel.fitting_mode == val) {
2432                         /* the eDP scaling property is not changed */
2433                         return 0;
2434                 }
2435                 intel_connector->panel.fitting_mode = val;
2436
2437                 goto done;
2438         }
2439
2440         return -EINVAL;
2441
2442 done:
2443         if (intel_encoder->base.crtc) {
2444                 struct drm_crtc *crtc = intel_encoder->base.crtc;
2445                 intel_set_mode(crtc, &crtc->mode,
2446                                crtc->x, crtc->y, crtc->fb);
2447         }
2448
2449         return 0;
2450 }
2451
2452 static void
2453 intel_dp_destroy(struct drm_connector *connector)
2454 {
2455         struct drm_device *dev = connector->dev;
2456         struct intel_dp *intel_dp = intel_attached_dp(connector);
2457         struct intel_connector *intel_connector = to_intel_connector(connector);
2458
2459         if (!IS_ERR_OR_NULL(intel_connector->edid))
2460                 kfree(intel_connector->edid);
2461
2462         if (is_edp(intel_dp)) {
2463                 intel_panel_destroy_backlight(dev);
2464                 intel_panel_fini(&intel_connector->panel);
2465         }
2466
2467         drm_sysfs_connector_remove(connector);
2468         drm_connector_cleanup(connector);
2469         kfree(connector);
2470 }
2471
2472 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2473 {
2474         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2475         struct intel_dp *intel_dp = &intel_dig_port->dp;
2476
2477         i2c_del_adapter(&intel_dp->adapter);
2478         drm_encoder_cleanup(encoder);
2479         if (is_edp(intel_dp)) {
2480                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2481                 ironlake_panel_vdd_off_sync(intel_dp);
2482         }
2483         kfree(intel_dig_port);
2484 }
2485
2486 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2487         .mode_fixup = intel_dp_mode_fixup,
2488         .mode_set = intel_dp_mode_set,
2489         .disable = intel_encoder_noop,
2490 };
2491
2492 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2493         .dpms = intel_connector_dpms,
2494         .detect = intel_dp_detect,
2495         .fill_modes = drm_helper_probe_single_connector_modes,
2496         .set_property = intel_dp_set_property,
2497         .destroy = intel_dp_destroy,
2498 };
2499
2500 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2501         .get_modes = intel_dp_get_modes,
2502         .mode_valid = intel_dp_mode_valid,
2503         .best_encoder = intel_best_encoder,
2504 };
2505
2506 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2507         .destroy = intel_dp_encoder_destroy,
2508 };
2509
2510 static void
2511 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2512 {
2513         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2514
2515         intel_dp_check_link_status(intel_dp);
2516 }
2517
2518 /* Return which DP Port should be selected for Transcoder DP control */
2519 int
2520 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2521 {
2522         struct drm_device *dev = crtc->dev;
2523         struct intel_encoder *intel_encoder;
2524         struct intel_dp *intel_dp;
2525
2526         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2527                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2528
2529                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2530                     intel_encoder->type == INTEL_OUTPUT_EDP)
2531                         return intel_dp->output_reg;
2532         }
2533
2534         return -1;
2535 }
2536
2537 /* check the VBT to see whether the eDP is on DP-D port */
2538 bool intel_dpd_is_edp(struct drm_device *dev)
2539 {
2540         struct drm_i915_private *dev_priv = dev->dev_private;
2541         struct child_device_config *p_child;
2542         int i;
2543
2544         if (!dev_priv->child_dev_num)
2545                 return false;
2546
2547         for (i = 0; i < dev_priv->child_dev_num; i++) {
2548                 p_child = dev_priv->child_dev + i;
2549
2550                 if (p_child->dvo_port == PORT_IDPD &&
2551                     p_child->device_type == DEVICE_TYPE_eDP)
2552                         return true;
2553         }
2554         return false;
2555 }
2556
2557 static void
2558 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2559 {
2560         struct intel_connector *intel_connector = to_intel_connector(connector);
2561
2562         intel_attach_force_audio_property(connector);
2563         intel_attach_broadcast_rgb_property(connector);
2564
2565         if (is_edp(intel_dp)) {
2566                 drm_mode_create_scaling_mode_property(connector->dev);
2567                 drm_connector_attach_property(
2568                         connector,
2569                         connector->dev->mode_config.scaling_mode_property,
2570                         DRM_MODE_SCALE_ASPECT);
2571                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2572         }
2573 }
2574
2575 static void
2576 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2577                                     struct intel_dp *intel_dp)
2578 {
2579         struct drm_i915_private *dev_priv = dev->dev_private;
2580         struct edp_power_seq cur, vbt, spec, final;
2581         u32 pp_on, pp_off, pp_div, pp;
2582
2583         /* Workaround: Need to write PP_CONTROL with the unlock key as
2584          * the very first thing. */
2585         pp = ironlake_get_pp_control(dev_priv);
2586         I915_WRITE(PCH_PP_CONTROL, pp);
2587
2588         pp_on = I915_READ(PCH_PP_ON_DELAYS);
2589         pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2590         pp_div = I915_READ(PCH_PP_DIVISOR);
2591
2592         /* Pull timing values out of registers */
2593         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2594                 PANEL_POWER_UP_DELAY_SHIFT;
2595
2596         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2597                 PANEL_LIGHT_ON_DELAY_SHIFT;
2598
2599         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2600                 PANEL_LIGHT_OFF_DELAY_SHIFT;
2601
2602         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2603                 PANEL_POWER_DOWN_DELAY_SHIFT;
2604
2605         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2606                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2607
2608         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2609                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2610
2611         vbt = dev_priv->edp.pps;
2612
2613         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2614          * our hw here, which are all in 100usec. */
2615         spec.t1_t3 = 210 * 10;
2616         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2617         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2618         spec.t10 = 500 * 10;
2619         /* This one is special and actually in units of 100ms, but zero
2620          * based in the hw (so we need to add 100 ms). But the sw vbt
2621          * table multiplies it with 1000 to make it in units of 100usec,
2622          * too. */
2623         spec.t11_t12 = (510 + 100) * 10;
2624
2625         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2626                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2627
2628         /* Use the max of the register settings and vbt. If both are
2629          * unset, fall back to the spec limits. */
2630 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
2631                                        spec.field : \
2632                                        max(cur.field, vbt.field))
2633         assign_final(t1_t3);
2634         assign_final(t8);
2635         assign_final(t9);
2636         assign_final(t10);
2637         assign_final(t11_t12);
2638 #undef assign_final
2639
2640 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
2641         intel_dp->panel_power_up_delay = get_delay(t1_t3);
2642         intel_dp->backlight_on_delay = get_delay(t8);
2643         intel_dp->backlight_off_delay = get_delay(t9);
2644         intel_dp->panel_power_down_delay = get_delay(t10);
2645         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2646 #undef get_delay
2647
2648         /* And finally store the new values in the power sequencer. */
2649         pp_on = (final.t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2650                 (final.t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2651         pp_off = (final.t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2652                  (final.t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2653         /* Compute the divisor for the pp clock, simply match the Bspec
2654          * formula. */
2655         pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2656                         << PP_REFERENCE_DIVIDER_SHIFT;
2657         pp_div |= (DIV_ROUND_UP(final.t11_t12, 1000)
2658                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
2659
2660         /* Haswell doesn't have any port selection bits for the panel
2661          * power sequencer any more. */
2662         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2663                 if (is_cpu_edp(intel_dp))
2664                         pp_on |= PANEL_POWER_PORT_DP_A;
2665                 else
2666                         pp_on |= PANEL_POWER_PORT_DP_D;
2667         }
2668
2669         I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2670         I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2671         I915_WRITE(PCH_PP_DIVISOR, pp_div);
2672
2673
2674         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2675                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2676                       intel_dp->panel_power_cycle_delay);
2677
2678         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2679                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2680
2681         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2682                       I915_READ(PCH_PP_ON_DELAYS),
2683                       I915_READ(PCH_PP_OFF_DELAYS),
2684                       I915_READ(PCH_PP_DIVISOR));
2685 }
2686
2687 void
2688 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2689                         struct intel_connector *intel_connector)
2690 {
2691         struct drm_connector *connector = &intel_connector->base;
2692         struct intel_dp *intel_dp = &intel_dig_port->dp;
2693         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2694         struct drm_device *dev = intel_encoder->base.dev;
2695         struct drm_i915_private *dev_priv = dev->dev_private;
2696         struct drm_display_mode *fixed_mode = NULL;
2697         enum port port = intel_dig_port->port;
2698         const char *name = NULL;
2699         int type;
2700
2701         /* Preserve the current hw state. */
2702         intel_dp->DP = I915_READ(intel_dp->output_reg);
2703         intel_dp->attached_connector = intel_connector;
2704
2705         if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2706                 if (intel_dpd_is_edp(dev))
2707                         intel_dp->is_pch_edp = true;
2708
2709         /*
2710          * FIXME : We need to initialize built-in panels before external panels.
2711          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2712          */
2713         if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2714                 type = DRM_MODE_CONNECTOR_eDP;
2715                 intel_encoder->type = INTEL_OUTPUT_EDP;
2716         } else if (port == PORT_A || is_pch_edp(intel_dp)) {
2717                 type = DRM_MODE_CONNECTOR_eDP;
2718                 intel_encoder->type = INTEL_OUTPUT_EDP;
2719         } else {
2720                 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2721                  * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2722                  * rewrite it.
2723                  */
2724                 type = DRM_MODE_CONNECTOR_DisplayPort;
2725         }
2726
2727         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2728         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2729
2730         connector->polled = DRM_CONNECTOR_POLL_HPD;
2731         connector->interlace_allowed = true;
2732         connector->doublescan_allowed = 0;
2733
2734         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2735                           ironlake_panel_vdd_work);
2736
2737         intel_connector_attach_encoder(intel_connector, intel_encoder);
2738         drm_sysfs_connector_add(connector);
2739
2740         if (IS_HASWELL(dev))
2741                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2742         else
2743                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2744
2745
2746         /* Set up the DDC bus. */
2747         switch (port) {
2748         case PORT_A:
2749                 name = "DPDDC-A";
2750                 break;
2751         case PORT_B:
2752                 dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS;
2753                 name = "DPDDC-B";
2754                 break;
2755         case PORT_C:
2756                 dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS;
2757                 name = "DPDDC-C";
2758                 break;
2759         case PORT_D:
2760                 dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS;
2761                 name = "DPDDC-D";
2762                 break;
2763         default:
2764                 WARN(1, "Invalid port %c\n", port_name(port));
2765                 break;
2766         }
2767
2768         if (is_edp(intel_dp))
2769                 intel_dp_init_panel_power_sequencer(dev, intel_dp);
2770
2771         intel_dp_i2c_init(intel_dp, intel_connector, name);
2772
2773         /* Cache DPCD and EDID for edp. */
2774         if (is_edp(intel_dp)) {
2775                 bool ret;
2776                 struct drm_display_mode *scan;
2777                 struct edid *edid;
2778
2779                 ironlake_edp_panel_vdd_on(intel_dp);
2780                 ret = intel_dp_get_dpcd(intel_dp);
2781                 ironlake_edp_panel_vdd_off(intel_dp, false);
2782
2783                 if (ret) {
2784                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2785                                 dev_priv->no_aux_handshake =
2786                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2787                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2788                 } else {
2789                         /* if this fails, presume the device is a ghost */
2790                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2791                         intel_dp_encoder_destroy(&intel_encoder->base);
2792                         intel_dp_destroy(connector);
2793                         return;
2794                 }
2795
2796                 ironlake_edp_panel_vdd_on(intel_dp);
2797                 edid = drm_get_edid(connector, &intel_dp->adapter);
2798                 if (edid) {
2799                         if (drm_add_edid_modes(connector, edid)) {
2800                                 drm_mode_connector_update_edid_property(connector, edid);
2801                                 drm_edid_to_eld(connector, edid);
2802                         } else {
2803                                 kfree(edid);
2804                                 edid = ERR_PTR(-EINVAL);
2805                         }
2806                 } else {
2807                         edid = ERR_PTR(-ENOENT);
2808                 }
2809                 intel_connector->edid = edid;
2810
2811                 /* prefer fixed mode from EDID if available */
2812                 list_for_each_entry(scan, &connector->probed_modes, head) {
2813                         if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2814                                 fixed_mode = drm_mode_duplicate(dev, scan);
2815                                 break;
2816                         }
2817                 }
2818
2819                 /* fallback to VBT if available for eDP */
2820                 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2821                         fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2822                         if (fixed_mode)
2823                                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2824                 }
2825
2826                 ironlake_edp_panel_vdd_off(intel_dp, false);
2827         }
2828
2829         if (is_edp(intel_dp)) {
2830                 intel_panel_init(&intel_connector->panel, fixed_mode);
2831                 intel_panel_setup_backlight(connector);
2832         }
2833
2834         intel_dp_add_properties(intel_dp, connector);
2835
2836         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2837          * 0xd.  Failure to do so will result in spurious interrupts being
2838          * generated on the port when a cable is not attached.
2839          */
2840         if (IS_G4X(dev) && !IS_GM45(dev)) {
2841                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2842                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2843         }
2844 }
2845
2846 void
2847 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2848 {
2849         struct intel_digital_port *intel_dig_port;
2850         struct intel_encoder *intel_encoder;
2851         struct drm_encoder *encoder;
2852         struct intel_connector *intel_connector;
2853
2854         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2855         if (!intel_dig_port)
2856                 return;
2857
2858         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2859         if (!intel_connector) {
2860                 kfree(intel_dig_port);
2861                 return;
2862         }
2863
2864         intel_encoder = &intel_dig_port->base;
2865         encoder = &intel_encoder->base;
2866
2867         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2868                          DRM_MODE_ENCODER_TMDS);
2869         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2870
2871         intel_encoder->enable = intel_enable_dp;
2872         intel_encoder->pre_enable = intel_pre_enable_dp;
2873         intel_encoder->disable = intel_disable_dp;
2874         intel_encoder->post_disable = intel_post_disable_dp;
2875         intel_encoder->get_hw_state = intel_dp_get_hw_state;
2876
2877         intel_dig_port->port = port;
2878         intel_dig_port->dp.output_reg = output_reg;
2879
2880         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2881         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2882         intel_encoder->cloneable = false;
2883         intel_encoder->hot_plug = intel_dp_hot_plug;
2884
2885         intel_dp_init_connector(intel_dig_port, intel_connector);
2886 }