2 * Linux CAN-bus device driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.2 9 Jul 2003
10 #include "../include/can.h"
11 #include "../include/can_sysdep.h"
12 #include "../include/main.h"
13 #include "../include/pccan.h"
14 #include "../include/i82527.h"
15 #include "../include/sja1000.h"
17 int pccanf_request_io(struct candevice_t *candev)
19 if (!can_request_io_region(candev->io_addr+0x4000,0x20,DEVICE_NAME)) {
20 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr+0x4000);
23 else if (!can_request_io_region(candev->io_addr+0x6000,0x04,DEVICE_NAME)) {
24 can_release_io_region(candev->io_addr+0x4000,0x20);
25 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr+0x6000);
29 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr+0x4000, candev->io_addr+0x4000+0x20-1);
30 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr+0x6000, candev->io_addr+0x6000+0x04-1);
35 int pccand_request_io(struct candevice_t *candev)
37 if (pccanf_request_io(candev))
40 if (!can_request_io_region(candev->io_addr+0x5000,0x20,DEVICE_NAME)) {
41 pccanf_release_io(candev);
42 CANMSG("Unable to open port: 0x%lx\n",candev->io_addr+0x5000);
46 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", candev->io_addr+0x5000, candev->io_addr+0x5000+0x20-1);
51 int pccanq_request_io(struct candevice_t *candev)
53 unsigned long io_addr;
56 if (pccand_request_io(candev))
59 for(i=0, io_addr=candev->io_addr+0x2000; i<8; i++, io_addr+=0x400) {
60 if (!can_request_io_region(io_addr,0x40,DEVICE_NAME)) {
61 CANMSG("Unable to open port: 0x%lx\n",io_addr);
64 can_release_io_region(io_addr,0x40);
66 pccand_release_io(candev);
69 DEBUGMSG("Registered IO-memory: 0x%lx - 0x%lx\n", io_addr, io_addr+0x40-1);
74 int pccanf_release_io(struct candevice_t *candev)
76 can_release_io_region(candev->io_addr+0x4000,0x20);
77 can_release_io_region(candev->io_addr+0x6000,0x04);
82 int pccand_release_io(struct candevice_t *candev)
84 pccanf_release_io(candev);
85 can_release_io_region(candev->io_addr+0x5000,0x20);
90 int pccanq_release_io(struct candevice_t *candev)
92 unsigned long io_addr;
95 pccand_release_io(candev);
97 for(i=0, io_addr=candev->io_addr+0x2000; i<8; i++, io_addr+=0x400) {
98 can_release_io_region(io_addr,0x40);
104 int pccanf_reset(struct candevice_t *candev)
108 DEBUGMSG("Resetting pccanf/s hardware ...\n");
109 while (i < 1000000) {
111 outb(0x00,candev->res_addr);
113 outb(0x01,candev->res_addr);
114 outb(0x00,candev->chip[0]->chip_base_addr+SJACR);
116 /* Check hardware reset status */
118 while ( (inb(candev->chip[0]->chip_base_addr+SJACR) & sjaCR_RR)
124 CANMSG("Reset status timeout!\n");
125 CANMSG("Please check your hardware.\n");
129 DEBUGMSG("Chip[0] reset status ok.\n");
134 int pccand_reset(struct candevice_t *candev)
138 DEBUGMSG("Resetting pccan-d hardware ...\n");
139 while (i < 1000000) {
141 outb(0x00,candev->res_addr);
143 outb(0x01,candev->res_addr);
144 outb(0x00,candev->chip[0]->chip_base_addr+SJACR);
145 outb(0x00,candev->chip[1]->chip_base_addr+SJACR);
147 /* Check hardware reset status */
149 for (chip_nr=0; chip_nr<2; chip_nr++) {
151 while ( (inb(candev->chip[chip_nr]->chip_base_addr +
152 SJACR) & sjaCR_RR) && (i<=15) ) {
157 CANMSG("Reset status timeout!\n");
158 CANMSG("Please check your hardware.\n");
162 DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
167 int pccanq_reset(struct candevice_t *candev)
172 can_disable_irq(candev->chip[i]->chip_irq);
174 DEBUGMSG("Resetting pccan-q hardware ...\n");
177 outb(0x00,candev->res_addr);
179 outb_p(0x01,candev->res_addr);
181 outb(0x00,candev->chip[2]->chip_base_addr+SJACR);
182 outb(0x00,candev->chip[3]->chip_base_addr+SJACR);
184 /* Check hardware reset status */
185 for (chip_nr=0; chip_nr<2; chip_nr++) {
187 while( (inb(candev->chip[chip_nr]->chip_base_addr +
188 iCPU) & iCPU_RST) && (i<=15) ) {
193 CANMSG("Reset status timeout!\n");
194 CANMSG("Please check your hardware.\n");
198 DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
200 for (chip_nr=2; chip_nr<4; chip_nr++) {
202 while( (inb(candev->chip[chip_nr]->chip_base_addr +
203 SJACR) & sjaCR_RR) && (i<=15) ) {
208 CANMSG("Reset status timeout!\n");
209 CANMSG("Please check your hardware.\n");
213 DEBUGMSG("Chip%d reset status ok.\n",chip_nr);
217 can_enable_irq(candev->chip[i]->chip_irq);
222 int pccan_init_hw_data(struct candevice_t *candev)
224 candev->res_addr=candev->io_addr+0x6001;
225 candev->flags |= CANDEV_PROGRAMMABLE_IRQ;
227 if (!strcmp(candev->hwname,"pccan-q")) {
228 candev->nr_82527_chips=2;
229 candev->nr_sja1000_chips=2;
230 candev->nr_all_chips=4;
232 if (!strcmp(candev->hwname,"pccan-f") |
233 !strcmp(candev->hwname,"pccan-s")) {
234 candev->nr_82527_chips=0;
235 candev->nr_sja1000_chips=1;
236 candev->nr_all_chips=1;
238 if (!strcmp(candev->hwname,"pccan-d")) {
239 candev->nr_82527_chips=0;
240 candev->nr_sja1000_chips=2;
241 candev->nr_all_chips=2;
247 int pccan_init_chip_data(struct candevice_t *candev, int chipnr)
249 if (!strcmp(candev->hwname,"pccan-q")) {
251 candev->chip[chipnr]->chip_type="i82527";
252 candev->chip[chipnr]->flags = CHIP_SEGMENTED;
253 candev->chip[chipnr]->int_cpu_reg=iCPU_DSC;
254 candev->chip[chipnr]->int_clk_reg=iCLK_SL1;
255 candev->chip[chipnr]->int_bus_reg=iBUS_CBY;
256 candev->chip[chipnr]->sja_cdr_reg = 0;
257 candev->chip[chipnr]->sja_ocr_reg = 0;
260 candev->chip[chipnr]->chip_type="sja1000";
261 candev->chip[chipnr]->flags = 0;
262 candev->chip[chipnr]->int_cpu_reg = 0;
263 candev->chip[chipnr]->int_clk_reg = 0;
264 candev->chip[chipnr]->int_bus_reg = 0;
265 candev->chip[chipnr]->sja_cdr_reg =
267 candev->chip[chipnr]->sja_ocr_reg =
268 sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
270 candev->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x2000+candev->io_addr;
273 candev->chip[chipnr]->chip_type="sja1000";
274 candev->chip[chipnr]->chip_base_addr=0x1000*chipnr+0x4000+candev->io_addr;
275 candev->chip[chipnr]->flags = 0;
276 candev->chip[chipnr]->int_cpu_reg = 0;
277 candev->chip[chipnr]->int_clk_reg = 0;
278 candev->chip[chipnr]->int_bus_reg = 0;
279 candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CLK_OFF;
280 candev->chip[chipnr]->sja_ocr_reg =
281 sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
284 candev->chip[chipnr]->clock = 16000000;
289 int pccan_init_obj_data(struct chip_t *chip, int objnr)
291 if (!strcmp(chip->chip_type,"sja1000")) {
292 chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
294 else { /* The spacing for this card is 0x3c0 */
295 chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr+(objnr+1)*0x10+(int)((objnr+1)/4)*0x3c0;
301 int pccan_program_irq(struct candevice_t *candev)
307 unsigned char irq_reg_value=0;
310 for (i=0; i<4; i++) {
311 switch (candev->chip[i]->chip_irq) {
316 irq_reg_value |= (IRQ3<<(i*2));
320 irq_reg_value |= (IRQ5<<(i*2));
324 irq_reg_value |= (IRQ9<<(i*2));
328 CANMSG("Supplied interrupt is not supported by the hardware\n");
333 outb(irq_reg_value,0x6000+candev->io_addr);
334 DEBUGMSG("Configured pccan hardware interrupts\n");
335 outb(0x80,0x6000+candev->io_addr+0x02);
336 DEBUGMSG("Selected pccan on-board 16 MHz oscillator\n");
341 inline void pccan_write_register(unsigned data, unsigned long address)
346 unsigned pccan_read_register(unsigned long address)
351 int pccanf_register(struct hwspecops_t *hwspecops)
353 hwspecops->request_io = pccanf_request_io;
354 hwspecops->release_io = pccanf_release_io;
355 hwspecops->reset = pccanf_reset;
356 hwspecops->init_hw_data = pccan_init_hw_data;
357 hwspecops->init_chip_data = pccan_init_chip_data;
358 hwspecops->init_obj_data = pccan_init_obj_data;
359 hwspecops->write_register = pccan_write_register;
360 hwspecops->read_register = pccan_read_register;
361 hwspecops->program_irq = pccan_program_irq;
366 int pccand_register(struct hwspecops_t *hwspecops)
368 hwspecops->request_io = pccand_request_io;
369 hwspecops->release_io = pccand_release_io;
370 hwspecops->reset = pccand_reset;
371 hwspecops->init_hw_data = pccan_init_hw_data;
372 hwspecops->init_chip_data = pccan_init_chip_data;
373 hwspecops->init_obj_data = pccan_init_obj_data;
374 hwspecops->write_register = pccan_write_register;
375 hwspecops->read_register = pccan_read_register;
376 hwspecops->program_irq = pccan_program_irq;
381 int pccanq_register(struct hwspecops_t *hwspecops)
383 hwspecops->request_io = pccanq_request_io;
384 hwspecops->release_io = pccanq_release_io;
385 hwspecops->reset = pccanq_reset;
386 hwspecops->init_hw_data = pccan_init_hw_data;
387 hwspecops->init_chip_data = pccan_init_chip_data;
388 hwspecops->init_obj_data = pccan_init_obj_data;
389 hwspecops->write_register = pccan_write_register;
390 hwspecops->read_register = pccan_read_register;
391 hwspecops->program_irq = pccan_program_irq;