2 * Linux CAN-bus device driver.
3 * Written by Arnaud Westenberg email:arnaud@wanadoo.nl
4 * Rewritten for new CAN queues by Pavel Pisa - OCERA team member
5 * email:pisa@cmp.felk.cvut.cz
6 * This software is released under the GPL-License.
7 * Version lincan-0.3 17 Jun 2004
10 #include "../include/can.h"
11 #include "../include/can_sysdep.h"
12 #include "../include/main.h"
13 #include "../include/sja1000p.h"
14 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14)) && defined(CONFIG_GENERIC_HARDIRQS)
15 #include <linux/irq.h>
17 #include <asm/arch/hardware.h>
18 #include <asm/arch/imx-regs.h>
20 #define EIM_CS1U __REG(IMX_EIM_BASE + 0x08)
21 #define EIM_CS1L __REG(IMX_EIM_BASE + 0x0C)
24 * IO_RANGE is the io-memory range that gets reserved, please adjust according
25 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
26 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
28 #define PIMX1_CAN_IO_ADDRESS 0x12000000
29 #define PIMX1_CAN_IO_RANGE 0x100
30 #define PIMX1_CAN_IRQ IRQ_GPIOB(17)
31 #define PIMX1_CAN_RESET_ADDR 0x0
35 static CAN_DEFINE_SPINLOCK(pimx1_setup_hardware_lock);
37 int pimx1_setup_hardware(struct candevice_t *candev)
39 can_spin_irqflags_t flags;
41 can_spin_lock_irqsave(&pimx1_setup_hardware_lock,flags);
42 /* CNC=0; WSC=10-1; WWS=0; EDC=2; OEA=6; OEN=2; WEA=8; WEN=2 */
43 EIM_CS1U = 0x00000902;
44 EIM_CS1L = 0x82820903;
45 imx_gpio_mode(PA21_PF_A0);
47 #if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,14))
48 /* Setup IRQ port as input */
49 imx_gpio_mode(GPIO_PORTB | GPIO_GIUS | GPIO_IN | GPIO_PUEN | 17);
50 /* Setup SJA1000 reset as output */
51 imx_gpio_mode(GPIO_PORTB | GPIO_GIUS | GPIO_OUT | GPIO_DR | 15);
53 imx_gpio_mode(GPIO_PORTB | GPIO_IN | GPIO_PUEN | GPIO_GPIO | 17);
54 imx_gpio_mode(GPIO_PORTB | GPIO_OUT | GPIO_GPIO | 15);
58 can_spin_unlock_irqrestore(&pimx1_setup_hardware_lock,flags);
60 set_irq_type(PIMX1_CAN_IRQ, IRQT_LOW);
67 * pimx1_request_io: - reserve io or memory range for can board
68 * @candev: pointer to candevice/board which asks for io. Field @io_addr
69 * of @candev is used in most cases to define start of the range
71 * The function pimx1_request_io() is used to reserve the io-memory. If your
72 * hardware uses a dedicated memory range as hardware control registers you
73 * will have to add the code to reserve this memory as well.
74 * %IO_RANGE is the io-memory range that gets reserved, please adjust according
75 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
76 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
77 * Return Value: The function returns zero on success or %-ENODEV on failure
78 * File: src/pikronisa.c
80 int pimx1_request_io(struct candevice_t *candev)
84 if(pimx1_setup_hardware(candev)<0){
85 CANMSG("PiMX1 board hardware setup failure\n");
89 if (!can_request_mem_region(candev->io_addr,PIMX1_CAN_IO_RANGE,DEVICE_NAME " - pimx1")) {
90 CANMSG("Unable to request IO-memory: 0x%lx\n",candev->io_addr);
93 if ( !( remap_addr = (long) ioremap( candev->io_addr, PIMX1_CAN_IO_RANGE ) ) ) {
94 CANMSG("Unable to access I/O memory at: 0x%lx\n", candev->io_addr);
95 can_release_mem_region(candev->io_addr,PIMX1_CAN_IO_RANGE);
98 can_base_addr_fixup(candev, remap_addr);
99 CANMSG("Registered IO-memory: 0x%lx - 0x%lx (VMA 0x%lx)\n",
100 candev->io_addr, candev->io_addr + PIMX1_CAN_IO_RANGE - 1, (long)remap_addr);
105 * pimx1_elease_io - free reserved io memory range
106 * @candev: pointer to candevice/board which releases io
108 * The function pimx1_release_io() is used to free reserved io-memory.
109 * In case you have reserved more io memory, don't forget to free it here.
110 * IO_RANGE is the io-memory range that gets released, please adjust according
111 * your hardware. Example: #define IO_RANGE 0x100 for i82527 chips or
112 * #define IO_RANGE 0x20 for sja1000 chips in basic CAN mode.
113 * Return Value: The function always returns zero
114 * File: src/pikronisa.c
116 int pimx1_release_io(struct candevice_t *candev)
118 /* release I/O memory mapping */
119 iounmap((void*)candev->dev_base_addr);
120 can_release_mem_region(candev->io_addr,PIMX1_CAN_IO_RANGE);
126 * pimx1_write_register - Low level write register routine
127 * @data: data to be written
128 * @address: memory address to write to
130 * The function pimx1_write_register() is used to write to hardware registers
131 * on the CAN chip. You should only have to edit this function if your hardware
132 * uses some specific write process.
133 * Return Value: The function does not return a value
134 * File: src/pikronisa.c
136 void pimx1_write_register(unsigned data, can_ioptr_t address)
138 /*DEBUGMSG("pimx1_write_register: addr=0x%lx data=0x%x\n",
140 can_writeb(data,address);
144 * pimx1_read_register - Low level read register routine
145 * @address: memory address to read from
147 * The function pimx1_read_register() is used to read from hardware registers
148 * on the CAN chip. You should only have to edit this function if your hardware
149 * uses some specific read process.
150 * Return Value: The function returns the value stored in @address
151 * File: src/pikronisa.c
153 unsigned pimx1_read_register(can_ioptr_t address)
155 return can_readb(address);
159 * pimx1_reset - hardware reset routine
160 * @candev: Pointer to candevice/board structure
162 * The function pimx1_reset() is used to give a hardware reset. This is
163 * rather hardware specific so I haven't included example code. Don't forget to
164 * check the reset status of the chip before returning.
165 * Return Value: The function returns zero on success or %-ENODEV on failure
166 * File: src/pikronisa.c
168 int pimx1_reset(struct candevice_t *candev)
171 struct canchip_t *chip=candev->chip[0];
174 pimx1_write_register(sjaMOD_RM, chip->chip_base_addr+SJAMOD);
177 cdr=pimx1_read_register(chip->chip_base_addr+SJACDR);
178 pimx1_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
180 pimx1_write_register(0, chip->chip_base_addr+SJAIER);
183 pimx1_write_register(0, chip->chip_base_addr+SJAMOD);
184 while (pimx1_read_register(chip->chip_base_addr+SJAMOD)&sjaMOD_RM){
185 if(!i--) return -ENODEV;
187 pimx1_write_register(0, chip->chip_base_addr+SJAMOD);
190 cdr=pimx1_read_register(chip->chip_base_addr+SJACDR);
191 pimx1_write_register(cdr|sjaCDR_PELICAN, chip->chip_base_addr+SJACDR);
193 pimx1_write_register(0, chip->chip_base_addr+SJAIER);
199 * pimx1_init_hw_data - Initialize hardware cards
200 * @candev: Pointer to candevice/board structure
202 * The function pimx1_init_hw_data() is used to initialize the hardware
203 * structure containing information about the installed CAN-board.
204 * %RESET_ADDR represents the io-address of the hardware reset register.
205 * %NR_82527 represents the number of intel 82527 chips on the board.
206 * %NR_SJA1000 represents the number of philips sja1000 chips on the board.
207 * The flags entry can currently only be %CANDEV_PROGRAMMABLE_IRQ to indicate that
208 * the hardware uses programmable interrupts.
209 * Return Value: The function always returns zero
210 * File: src/pikronisa.c
212 int pimx1_init_hw_data(struct candevice_t *candev)
214 candev->res_addr=PIMX1_CAN_RESET_ADDR;
215 candev->io_addr=PIMX1_CAN_IO_ADDRESS;
216 candev->dev_base_addr=PIMX1_CAN_IO_ADDRESS;
217 candev->nr_82527_chips=0;
218 candev->nr_sja1000_chips=1;
219 candev->nr_all_chips=1;
220 candev->flags |= CANDEV_PROGRAMMABLE_IRQ*0;
226 * pimx1_init_chip_data - Initialize chips
227 * @candev: Pointer to candevice/board structure
228 * @chipnr: Number of the CAN chip on the hardware card
230 * The function pimx1_init_chip_data() is used to initialize the hardware
231 * structure containing information about the CAN chips.
232 * %CHIP_TYPE represents the type of CAN chip. %CHIP_TYPE can be "i82527" or
234 * The @chip_base_addr entry represents the start of the 'official' memory map
235 * of the installed chip. It's likely that this is the same as the @io_addr
236 * argument supplied at module loading time.
237 * The @clock entry holds the chip clock value in Hz.
238 * The entry @sja_cdr_reg holds hardware specific options for the Clock Divider
239 * register. Options defined in the %sja1000.h file:
240 * %sjaCDR_CLKOUT_MASK, %sjaCDR_CLK_OFF, %sjaCDR_RXINPEN, %sjaCDR_CBP, %sjaCDR_PELICAN
241 * The entry @sja_ocr_reg holds hardware specific options for the Output Control
242 * register. Options defined in the %sja1000.h file:
243 * %sjaOCR_MODE_BIPHASE, %sjaOCR_MODE_TEST, %sjaOCR_MODE_NORMAL, %sjaOCR_MODE_CLOCK,
244 * %sjaOCR_TX0_LH, %sjaOCR_TX1_ZZ.
245 * The entry @int_clk_reg holds hardware specific options for the Clock Out
246 * register. Options defined in the %i82527.h file:
247 * %iCLK_CD0, %iCLK_CD1, %iCLK_CD2, %iCLK_CD3, %iCLK_SL0, %iCLK_SL1.
248 * The entry @int_bus_reg holds hardware specific options for the Bus
249 * Configuration register. Options defined in the %i82527.h file:
250 * %iBUS_DR0, %iBUS_DR1, %iBUS_DT1, %iBUS_POL, %iBUS_CBY.
251 * The entry @int_cpu_reg holds hardware specific options for the cpu interface
252 * register. Options defined in the %i82527.h file:
253 * %iCPU_CEN, %iCPU_MUX, %iCPU_SLP, %iCPU_PWD, %iCPU_DMC, %iCPU_DSC, %iCPU_RST.
254 * Return Value: The function always returns zero
255 * File: src/pikronisa.c
257 int pimx1_init_chip_data(struct candevice_t *candev, int chipnr)
259 /*sja1000_fill_chipspecops(candev->chip[chipnr]);*/
260 sja1000p_fill_chipspecops(candev->chip[chipnr]);
262 candev->chip[chipnr]->chip_base_addr=candev->io_addr;
263 candev->chip[chipnr]->chip_irq=PIMX1_CAN_IRQ;
264 candev->chip[chipnr]->clock = 24000000;
265 candev->chip[chipnr]->int_clk_reg = 0x0;
266 candev->chip[chipnr]->int_bus_reg = 0x0;
267 candev->chip[chipnr]->sja_cdr_reg = sjaCDR_CBP | sjaCDR_CLK_OFF;
268 candev->chip[chipnr]->sja_ocr_reg = sjaOCR_MODE_NORMAL | sjaOCR_TX0_LH;
274 * pimx1_init_obj_data - Initialize message buffers
275 * @chip: Pointer to chip specific structure
276 * @objnr: Number of the message buffer
278 * The function pimx1_init_obj_data() is used to initialize the hardware
279 * structure containing information about the different message objects on the
280 * CAN chip. In case of the sja1000 there's only one message object but on the
281 * i82527 chip there are 15.
282 * The code below is for a i82527 chip and initializes the object base addresses
283 * The entry @obj_base_addr represents the first memory address of the message
284 * object. In case of the sja1000 @obj_base_addr is taken the same as the chips
286 * Unless the hardware uses a segmented memory map, flags can be set zero.
287 * Return Value: The function always returns zero
288 * File: src/pikronisa.c
290 int pimx1_init_obj_data(struct canchip_t *chip, int objnr)
292 chip->msgobj[objnr]->obj_base_addr=chip->chip_base_addr;
297 * pimx1_program_irq - program interrupts
298 * @candev: Pointer to candevice/board structure
300 * The function pimx1_program_irq() is used for hardware that uses
301 * programmable interrupts. If your hardware doesn't use programmable interrupts
302 * you should not set the @candevices_t->flags entry to %CANDEV_PROGRAMMABLE_IRQ and
303 * leave this function unedited. Again this function is hardware specific so
304 * there's no example code.
305 * Return value: The function returns zero on success or %-ENODEV on failure
306 * File: src/pikronisa.c
308 int pimx1_program_irq(struct candevice_t *candev)
313 /* !!! Don't change this function !!! */
314 int pimx1_register(struct hwspecops_t *hwspecops)
316 hwspecops->request_io = pimx1_request_io;
317 hwspecops->release_io = pimx1_release_io;
318 hwspecops->reset = pimx1_reset;
319 hwspecops->init_hw_data = pimx1_init_hw_data;
320 hwspecops->init_chip_data = pimx1_init_chip_data;
321 hwspecops->init_obj_data = pimx1_init_obj_data;
322 hwspecops->write_register = pimx1_write_register;
323 hwspecops->read_register = pimx1_read_register;
324 hwspecops->program_irq = pimx1_program_irq;