namespace Bootstrap {
inline void set_asid()
{}
+
+inline void set_ttbcr()
+{}
}
//---------------------------------------------------------------------------
INTERFACE [arm && (armv6 || armv7)]:
+#include "kmem_space.h"
+
namespace Bootstrap {
inline void
set_asid()
{
asm volatile ("mcr p15, 0, %0, c13, c0, 1" : : "r" (0)); // ASID 0
}
+
+inline void set_ttbcr()
+{
+ asm volatile("mcr p15, 0, %[ttbcr], c2, c0, 2" // TTBCR
+ : : [ttbcr] "r" (Page::Ttbcr_bits));
+}
}
//---------------------------------------------------------------------------
Bootstrap::do_arm_1176_cache_alias_workaround();
Bootstrap::set_asid();
- asm volatile("mcr p15, 0, %[ttbcr], c2, c0, 2" // TTBCR
- : : [ttbcr] "r" (Page::Ttbcr_bits));
+ Bootstrap::set_ttbcr();
Mem::dsb();
asm volatile("mcr p15, 0, %[null], c8, c7, 0" // TLBIALL
: : [null] "r" (0));
{
copro_enable();
- fpu.cpu(cpu)._fpsid = Fpsid(fpsid_read());
- if (cpu == Cpu_number::boot_cpu())
+ Fpu &f = fpu.cpu(cpu);
+ f._fpsid = Fpsid(fpsid_read());
+ if (cpu == Cpu_number::boot_cpu() && f._fpsid.arch_version() > 1)
save_32r = (mvfr0() & 0xf) == 2;
if (!resume)
disable();
- fpu.cpu(cpu).set_owner(0);
+ f.set_owner(0);
}
IMPLEMENT inline NEEDS ["fpu_state.h", "mem.h", "static_assert.h"]
{
Mword tmp;
asm volatile("stc p11, cr0, [%0], #128 \n"
- "cmp %1, #0 \n"
+ "cmp %2, #0 \n"
"stcnel p11, cr0, [%0], #128 \n"
: "=r" (tmp) : "0" (r->state), "r" (save_32r));
}
{
Mword tmp;
asm volatile("ldc p11, cr0, [%0], #128 \n"
- "cmp %1, #0 \n"
+ "cmp %2, #0 \n"
"ldcnel p11, cr0, [%0], #128 \n"
: "=r" (tmp) : "0" (r->state), "r" (save_32r));
}