8 class Vm_svm : public Vm
11 static void resume_vm_svm(Mword phys_vmcb, Mword *regs)
12 asm("resume_vm_svm") __attribute__((__regparm__(3)));
13 Unsigned8 _asid[Config::Max_num_cpus];
14 Unsigned32 _asid_generation[Config::Max_num_cpus];
23 // ------------------------------------------------------------------------
24 INTERFACE [svm && debug]:
26 EXTENSION class Vm_svm
29 struct Log_vm_svm_exit
31 Mword exitcode, exitinfo1, exitinfo2, rip;
34 static unsigned log_fmt_svm(Tb_entry *, int max, char *buf) asm ("__fmt_vm_svm_exit");
37 // ------------------------------------------------------------------------
41 #include "mem_space.h"
45 #include "thread.h" // XXX: circular dep, move this out here!
46 #include "thread_state.h" // XXX: circular dep, move this out here!
49 // ------------------------------------------------------------------------
50 IMPLEMENTATION [svm && ia32]:
54 PRIVATE inline NEEDS["virt.h"]
56 Vm_svm::get_vm_cr3(Vmcb *)
58 // When running in 32bit mode we already return the page-table of our Vm
59 // object, whether we're running with shadow or nested paging
60 return mem_space()->phys_dir();
63 //----------------------------------------------------------------------------
64 IMPLEMENTATION [svm && amd64]:
68 PRIVATE inline NEEDS["virt.h"]
70 Vm_svm::get_vm_cr3(Vmcb *v)
72 // When we have nested paging, we just return the 4lvl host page-table of
75 return mem_space()->phys_dir();
77 // When running with shadow paging and the guest is running in long mode
78 // and has paging enabled, we can just return the 4lvl page table of our
80 if ( (v->state_save_area.efer & EFER_LME)
81 && (v->state_save_area.cr0 & CR0_PG))
82 return mem_space()->phys_dir();
84 // Now it's getting tricky when running with shadow paging.
85 // We need to obey the following rules:
86 // - When the guest is not running in 64bit mode the CR3 one can set for
87 // the page-table must be below 4G physical memory (i.e. bit 32-63 must
88 // be zero). This is unfortunate when the host has memory above 4G as
89 // Fiasco gets its memory from the end of physical memory, i.e.
90 // page-table memory is above 4G.
91 // - We need an appropriate page-table format for 32bit!
92 // That means either a 2lvl page-table or a 3lvl PAE one. That would
93 // require to maintain two page-tables for the guest, one for 32bit
94 // mode execution and one for 64 bit execution. It is needed either for
95 // the transition from real to long-mode via protected mode or for
97 // There's one trick to avoid having two PTs: 4lvl-PTs and 3lvl-PAE-PTs
98 // have much in common so that it's possible to just take the the PDPE
99 // one of the host as the 3lvl-PAE-PT for the guest. Well, not quite.
100 // The problem is that SVM checks that MBZ bits in the PAE-PT entries
101 // are really 0 as written in the spec. Now the 4lvl PT contains rights
102 // bits there, so that this type of PT is refused and does not work on
104 // So why is the code still here? Well, QEmu isn't so picky about the
105 // bits in the PDPE and it thus works there...
106 Address vm_cr3 = mem_space()->dir()->walk(Virt_addr(0), 0).e->addr();
107 if (EXPECT_FALSE(!vm_cr3))
109 // force allocation of new secondary page-table level
110 mem_space()->dir()->alloc_cast<Mem_space_q_alloc>()
111 ->walk(Virt_addr(0), 1, Mem_space_q_alloc(ram_quota(),
112 Mapped_allocator::allocator()));
113 vm_cr3 = mem_space()->dir()->walk(Virt_addr(0), 0).e->addr();
116 if (EXPECT_FALSE(vm_cr3 >= 1UL << 32))
118 WARN("svm: Host page-table not under 4G, sorry.\n");
125 //----------------------------------------------------------------------------
126 IMPLEMENTATION [svm]:
132 return _asid[current_cpu()];
137 Vm_svm::asid (Unsigned8 asid)
139 _asid[current_cpu()] = asid;
144 Vm_svm::asid_generation ()
146 return _asid_generation[current_cpu()];
151 Vm_svm::asid_generation (Unsigned32 generation)
153 _asid_generation[current_cpu()] = generation;
157 Vm_svm::Vm_svm(Ram_quota *q)
160 memset(_asid, 0, sizeof(_asid));
161 memset(_asid_generation, 0, sizeof(_asid_generation));
166 Vm_svm::operator new (size_t size, void *p)
168 assert (size == sizeof (Vm_svm));
174 Vm_svm::operator delete (void *ptr)
176 Vm_svm *t = reinterpret_cast<Vm_svm*>(ptr);
177 allocator<Vm_svm>()->q_free(t->ram_quota(), ptr);
183 // - force fpu ownership
184 // - debug registers not covered by VMCB
188 Vm_svm::copy_state_save_area(Vmcb *dest, Vmcb *src)
190 Vmcb_state_save_area *d = &dest->state_save_area;
191 Vmcb_state_save_area *s = &src->state_save_area;
193 d->es_sel = s->es_sel;
194 d->es_attrib = s->es_attrib;
195 d->es_limit = s->es_limit;
196 d->es_base = s->es_base;
198 d->cs_sel = s->cs_sel;
199 d->cs_attrib = s->cs_attrib;
200 d->cs_limit = s->cs_limit;
201 d->cs_base = s->cs_base;
203 d->ss_sel = s->ss_sel;
204 d->ss_attrib = s->ss_attrib;
205 d->ss_limit = s->ss_limit;
206 d->ss_base = s->ss_base;
208 d->ds_sel = s->ds_sel;
209 d->ds_attrib = s->ds_attrib;
210 d->ds_limit = s->ds_limit;
211 d->ds_base = s->ds_base;
213 d->fs_sel = s->fs_sel;
214 d->fs_attrib = s->fs_attrib;
215 d->fs_limit = s->fs_limit;
216 d->fs_base = s->fs_base;
218 d->gs_sel = s->gs_sel;
219 d->gs_attrib = s->gs_attrib;
220 d->gs_limit = s->gs_limit;
221 d->gs_base = s->gs_base;
223 d->gdtr_sel = s->gdtr_sel;
224 d->gdtr_attrib = s->gdtr_attrib;
225 d->gdtr_limit = s->gdtr_limit;
226 d->gdtr_base = s->gdtr_base;
228 d->ldtr_sel = s->ldtr_sel;
229 d->ldtr_attrib = s->ldtr_attrib;
230 d->ldtr_limit = s->ldtr_limit;
231 d->ldtr_base = s->ldtr_base;
233 d->idtr_sel = s->idtr_sel;
234 d->idtr_attrib = s->idtr_attrib;
235 d->idtr_limit = s->idtr_limit;
236 d->idtr_base = s->idtr_base;
238 d->tr_sel = s->tr_sel;
239 d->tr_attrib = s->tr_attrib;
240 d->tr_limit = s->tr_limit;
241 d->tr_base = s->tr_base;
251 d->rflags = s->rflags;
260 d->sfmask = s->sfmask;
261 d->kernelgsbase = s->kernelgsbase;
262 d->sysenter_cs = s->sysenter_cs;
263 d->sysenter_esp = s->sysenter_esp;
264 d->sysenter_eip = s->sysenter_eip;
268 d->dbgctl = s->dbgctl;
269 d->br_from = s->br_from;
271 d->lastexcpfrom = s->lastexcpfrom;
272 d->last_excpto = s->last_excpto;
278 Vm_svm::copy_control_area(Vmcb *dest, Vmcb *src)
280 Vmcb_control_area *d = &dest->control_area;
281 Vmcb_control_area *s = &src->control_area;
283 d->intercept_rd_crX = s->intercept_rd_crX;
284 d->intercept_wr_crX = s->intercept_wr_crX;
286 d->intercept_rd_drX = s->intercept_rd_drX;
287 d->intercept_wr_drX = s->intercept_wr_drX;
289 d->intercept_exceptions = s->intercept_exceptions;
291 d->intercept_instruction0 = s->intercept_instruction0;
292 d->intercept_instruction1 = s->intercept_instruction1;
294 // skip iopm_base_pa and msrpm_base_pa
296 d->tsc_offset = s->tsc_offset;
297 d->guest_asid_tlb_ctl = s->guest_asid_tlb_ctl;
298 d->interrupt_ctl = s->interrupt_ctl;
299 d->interrupt_shadow = s->interrupt_shadow;
300 d->exitcode = s->exitcode;
301 d->exitinfo1 = s->exitinfo1;
302 d->exitinfo2 = s->exitinfo2;
303 d->exitintinfo = s->exitintinfo;
304 d->np_enable = s->np_enable;
306 d->eventinj = s->eventinj;
308 d->lbr_virtualization_enable = s->lbr_virtualization_enable;
312 /* skip anything that does not change */
315 Vm_svm::copy_control_area_back(Vmcb *dest, Vmcb *src)
317 Vmcb_control_area *d = &dest->control_area;
318 Vmcb_control_area *s = &src->control_area;
320 d->interrupt_ctl = s->interrupt_ctl;
321 d->interrupt_shadow = s->interrupt_shadow;
323 d->exitcode = s->exitcode;
324 d->exitinfo1 = s->exitinfo1;
325 d->exitinfo2 = s->exitinfo2;
326 d->exitintinfo = s->exitintinfo;
328 d->eventinj = s->eventinj;
331 /** \brief Choose an ASID for this Vm.
333 * Choose an ASID for this Vm. The ASID provided by userspace is ignored
334 * instead the kernel picks one.
335 * Userspace uses the flush-bit to receive a new ASID for this Vm.
336 * All ASIDs are flushed as soon as the kernel runs out of ASIDs.
338 * @param vmcb_s external VMCB provided by userspace
339 * @param kernel_vmcb_s our VMCB
344 Vm_svm::configure_asid (Vmcb *vmcb_s, Vmcb *kernel_vmcb_s)
346 assert (cpu_lock.test());
348 Svm &s = Svm::cpus.cpu(current_cpu());
350 if (// vmm requests flush
351 ((vmcb_s->control_area.guest_asid_tlb_ctl >> 32) & 1) == 1 ||
352 // our asid is not valid or expired
353 !(s.asid_valid(asid(), asid_generation())))
356 asid_generation(s.global_asid_generation());
359 assert(s.asid_valid(asid(), asid_generation()));
361 kernel_vmcb_s->control_area.guest_asid_tlb_ctl = asid();
362 if (s.flush_all_asids())
364 kernel_vmcb_s->control_area.guest_asid_tlb_ctl |= (1ULL << 32);
365 s.flush_all_asids(false);
368 kernel_vmcb_s->control_area.guest_asid_tlb_ctl = 1;
369 kernel_vmcb_s->control_area.guest_asid_tlb_ctl |= (1ULL << 32);
375 Vm_svm::sys_vm_run(Syscall_frame *f, Utcb *utcb)
378 Unsigned64 orig_cr3, orig_ncr3;
380 assert (cpu_lock.test());
382 /* these 4 must not use ldt entries */
383 assert (!(Cpu::get_cs() & (1 << 2)));
384 assert (!(Cpu::get_ss() & (1 << 2)));
385 assert (!(Cpu::get_ds() & (1 << 2)));
386 assert (!(Cpu::get_es() & (1 << 2)));
388 Svm &s = Svm::cpus.cpu(current_cpu());
390 L4_msg_tag const &tag = f->tag();
392 if (EXPECT_FALSE(!s.svm_enabled()))
394 WARN("svm: not supported/enabled\n");
395 return commit_result(-L4_err::EInval);
398 if (EXPECT_FALSE(tag.words() < 1 + Svm::Gpregs_words))
400 WARN("svm: Invalid message length\n");
401 return commit_result(-L4_err::EInval);
404 L4_snd_item_iter vmcb_item(utcb, tag.words());
406 if (EXPECT_FALSE(!tag.items() || !vmcb_item.next()))
407 return commit_result(-L4_err::EInval);
409 L4_fpage vmcb_fpage(vmcb_item.get()->d);
411 if (EXPECT_FALSE(!vmcb_fpage.is_mempage()))
413 WARN("svm: Fpage invalid\n");
414 return commit_error(utcb, L4_error::Overflow);
417 if (EXPECT_FALSE(vmcb_fpage.order() < 12))
418 return commit_result(-L4_err::EInval);
420 Vmcb *vmcb_s = (Vmcb *)(Virt_addr(vmcb_fpage.mem_address()).value());
421 Vmcb *kernel_vmcb_s = s.kernel_vmcb();
423 if (EXPECT_FALSE(vmcb_s->np_enabled() && !s.has_npt()))
425 WARN("svm: No NPT available\n");
426 return commit_result(-L4_err::EInval);
429 Address vm_cr3 = get_vm_cr3(vmcb_s);
430 // can only fail on 64bit, will be optimized away on 32bit
431 if (EXPECT_FALSE(is_64bit() && !vm_cr3))
432 return commit_result(-L4_err::ENomem);
434 Mem_space::Phys_addr phys_vmcb;
435 Mem_space::Size size;
437 unsigned int page_attribs;
439 Mem_space *const curr_mem_space = current()->space()->mem_space();
440 resident = curr_mem_space->v_lookup(Virt_addr(vmcb_s), &phys_vmcb, &size, &page_attribs);
444 WARN("svm: VMCB invalid\n");
445 return commit_result(-L4_err::EInval);
448 // currently only support for nested pagetables
449 // if shadow page tables are to be allowed then cr0
450 // needs further scrutiny and cr3 must not be accessible
451 if((vmcb_s->control_area.np_enable & 1) != 1)
452 return commit_result(-L4_err::EInval);
455 // neither EFER.LME nor EFER.LMA must be set
456 if (EXPECT_FALSE(!is_64bit()
457 && (vmcb_s->state_save_area.efer & (EFER_LME | EFER_LMA))))
459 WARN("svm: EFER invalid %llx\n", vmcb_s->state_save_area.efer);
460 return commit_result(-L4_err::EInval);
463 // EFER.SVME must be set
464 if (!(vmcb_s->state_save_area.efer & 0x1000))
466 WARN("svm: EFER invalid %llx\n", vmcb_s->state_save_area.efer);
467 return commit_result(-L4_err::EInval);
469 // allow PAE in combination with NPT
471 // CR4.PAE must be clear
472 if(vmcb_s->state_save_area.cr4 & 0x20)
473 return commit_result(-L4_err::EInval);
477 // This generates a circular dep between thread<->task, this cries for a
478 // new abstraction...
479 if (!(current()->state() & Thread_fpu_owner))
481 if (!current_thread()->switchin_fpu())
483 WARN("svm: switchin_fpu failed\n");
484 return commit_result(-L4_err::EInval);
488 #if 0 //should never happen
489 host_cr0 = Cpu::get_cr0();
490 // the VMM does not currently own the fpu but wants to
491 // make it available for the guest. This may happen
492 // if it was descheduled between activating the fpu and
493 // executing the vm_run operation
494 if (!(vmcb_s->state_save_area.cr0 & 0x8) && (host_cr0 & 0x8))
496 WARN("svm: FPU TS\n");
497 return commit_result(-L4_err::EInval);
501 // increment our refcount, and drop it at the end automatically
502 Ref_ptr<Vm_svm> pin_myself(this);
506 orig_cr3 = vmcb_s->state_save_area.cr3;
507 orig_ncr3 = vmcb_s->control_area.n_cr3;
509 copy_control_area(kernel_vmcb_s, vmcb_s);
510 copy_state_save_area(kernel_vmcb_s, vmcb_s);
512 if (EXPECT_FALSE(is_64bit() && !kernel_vmcb_s->np_enabled()
513 && (kernel_vmcb_s->state_save_area.cr0 & CR0_PG)
514 && !(kernel_vmcb_s->state_save_area.cr4 & CR4_PAE)))
516 WARN("svm: No 32bit shadow page-tables on AMD64, use PAE!\n");
517 return commit_result(-L4_err::EInval);
520 // set MCE according to host
521 kernel_vmcb_s->state_save_area.cr4 |= Cpu::get_cr4() & CR4_MCE;
523 // allow w access to cr0, cr2, cr3
524 // allow r access to cr0, cr2, cr3, cr4
525 // to do: check if enabling PAE in cr4 needs to be controlled
527 // allow r/w access to dr[0-7]
528 kernel_vmcb_s->control_area.intercept_rd_drX |= 0xff00;
529 kernel_vmcb_s->control_area.intercept_wr_drX |= 0xff00;
532 // intercept exception vectors 0-31
533 kernel_vmcb_s->control_area.intercept_exceptions = 0xffffffff;
536 // enable iopm and msrpm
537 kernel_vmcb_s->control_area.intercept_instruction0 |= 0x18000000;
538 // intercept FERR_FREEZE and shutdown events
539 kernel_vmcb_s->control_area.intercept_instruction0 |= 0xc0000000;
540 // intercept INTR/NMI/SMI/INIT
541 kernel_vmcb_s->control_area.intercept_instruction0 |= 0xf;
543 kernel_vmcb_s->control_area.intercept_instruction0 |= (1 << 22);
545 kernel_vmcb_s->control_area.intercept_instruction0 |= (1 << 24);
546 // intercept task switch
547 kernel_vmcb_s->control_area.intercept_instruction0 |= (1 << 29);
548 // intercept shutdown
549 kernel_vmcb_s->control_area.intercept_instruction0 |= (1 << 31);
550 // intercept MONITOR/MWAIT
551 kernel_vmcb_s->control_area.intercept_instruction1 |= (1 << 10) | (1 << 11);
553 // intercept virtualization related instructions
554 // vmrun interception is required by the hardware
555 kernel_vmcb_s->control_area.intercept_instruction1 |= 0xff;
557 Mword kernel_vmcb_pa = s.kernel_vmcb_pa();
558 Unsigned64 iopm_base_pa = s.iopm_base_pa();
559 Unsigned64 msrpm_base_pa = s.msrpm_base_pa();
561 kernel_vmcb_s->control_area.iopm_base_pa = iopm_base_pa;
562 kernel_vmcb_s->control_area.msrpm_base_pa = msrpm_base_pa;
564 configure_asid(vmcb_s, kernel_vmcb_s);
566 // 7:0 V_TPR, 8 V_IRQ, 15:9 reserved SBZ,
567 // 19:16 V_INTR_PRIO, 20 V_IGN_TPR, 23:21 reserved SBZ
568 // 24 V_INTR_MASKING 31:25 reserved SBZ
569 // 39:32 V_INTR_VECTOR, 63:40 reserved SBZ
571 kernel_vmcb_s->control_area.interrupt_ctl = 0x10f0000;
573 // enable IRQ masking virtualization
574 kernel_vmcb_s->control_area.interrupt_ctl |= 0x01000000;
577 // 0 INTERRUPT_SHADOW, 31:1 reserved SBZ
578 // 63:32 reserved SBZ
579 kernel_vmcb_s->control_area.interrupt_shadow = 0;
582 kernel_vmcb_s->control_area.exitcode = 0;
583 kernel_vmcb_s->control_area.exitinfo1 = 0;
584 kernel_vmcb_s->control_area.exitinfo2 = 0;
585 kernel_vmcb_s->control_area.exitintinfo = 0;
588 // 0/1 NP_ENABLE, 31:1 reserved SBZ
589 kernel_vmcb_s->control_area.np_enable = 1;
591 // 31 VALID, EVENTINJ
592 kernel_vmcb_s->control_area.eventinj = 0;
596 kernel_vmcb_s->control_area.n_cr3 = vm_cr3;
598 if (!kernel_vmcb_s->np_enabled())
600 // to do: check that the vmtask has the
601 // VM property set, i.e. does not contain mappings
602 // to the fiasco kernel regions or runs with PL 3
604 // printf("nested paging disabled, use n_cr3 as cr3\n");
605 kernel_vmcb_s->state_save_area.cr3 = vm_cr3;
607 // intercept accesses to cr0, cr3 and cr4
608 kernel_vmcb_s->control_area.intercept_rd_crX = 0xfff9;
609 kernel_vmcb_s->control_area.intercept_wr_crX = 0xfff9;
613 kernel_vmcb_s->control_area.lbr_virtualization_enable = 0;
618 // - initialize VM_HSAVE_PA (done)
619 // - supply trusted msrpm_base_pa and iopm_base_pa (done)
620 // - save host state not covered by VMRUN/VMEXIT (ldt, some segments etc) (done)
621 // - disable interupts (done)
622 // - trigger interecepted device and timer interrupts (done, not necessary)
623 // - check host CR0.TS (floating point registers) (done)
625 Unsigned64 sysenter_cs, sysenter_eip, sysenter_esp;
630 sysenter_cs = Cpu::rdmsr(MSR_SYSENTER_CS);
631 sysenter_eip = Cpu::rdmsr(MSR_SYSENTER_EIP);
632 sysenter_esp = Cpu::rdmsr(MSR_SYSENTER_ESP);
637 ldtr = Cpu::get_ldt();
641 tr_entry = (*Cpu::cpus.cpu(current_cpu()).get_gdt())[tr / 8];
644 // to do: check if the nested page table walker looks
645 // into the TLB. if so, global pages have to be disabled in
647 cr4 = Cpu::get_cr4();
650 // disable support for global pages as the vm task has
651 // a divergent upper memory region from the regular tasks
652 Cpu::set_cr4(cr4 & ~CR4_PGE);
655 resume_vm_svm(kernel_vmcb_pa, &utcb->values[1]);
663 Cpu::wrmsr(sysenter_cs, MSR_SYSENTER_CS);
664 Cpu::wrmsr(sysenter_eip, MSR_SYSENTER_EIP);
665 Cpu::wrmsr(sysenter_esp, MSR_SYSENTER_ESP);
674 tss_entry = (*Cpu::cpus.cpu(current_cpu()).get_gdt())[tr / 8];
675 tss_entry.access &= 0xfd;
676 (*Cpu::cpus.cpu(current_cpu()).get_gdt())[tr / 8] = tss_entry;
678 Cpu::set_tr(tr); // TODO move under stgi in asm
680 copy_state_save_area(vmcb_s, kernel_vmcb_s);
681 copy_control_area_back(vmcb_s, kernel_vmcb_s);
683 if (!(vmcb_s->np_enabled()))
684 vmcb_s->state_save_area.cr3 = orig_cr3;
686 vmcb_s->control_area.n_cr3 = orig_ncr3;
688 LOG_TRACE("VM-SVM", "svm", current(), __fmt_vm_svm_exit,
689 Log_vm_svm_exit *l = tbe->payload<Log_vm_svm_exit>();
690 l->exitcode = vmcb_s->control_area.exitcode;
691 l->exitinfo1 = vmcb_s->control_area.exitinfo1;
692 l->exitinfo2 = vmcb_s->control_area.exitinfo2;
693 l->rip = vmcb_s->state_save_area.rip;
696 return commit_result(L4_error::None);
701 Vm_svm::invoke(L4_obj_ref obj, Mword rights, Syscall_frame *f, Utcb *utcb)
703 vm_invoke<Vm_svm>(obj, rights, f, utcb);
706 // ------------------------------------------------------------------------
707 IMPLEMENTATION [svm && debug]:
711 Vm_svm::log_fmt_svm(Tb_entry *e, int max, char *buf)
713 Log_vm_svm_exit *l = e->payload<Log_vm_svm_exit>();
714 return snprintf(buf, max, "ec=%lx ei1=%08lx ei2=%08lx rip=%08lx",
715 l->exitcode, l->exitinfo1, l->exitinfo2, l->rip);