6 #include "irq_chip_ia32.h"
9 #include "static_init.h"
10 #include "boot_alloc.h"
12 class Irq_chip_msi : public Irq_chip_ia32
15 // this is somehow arbitrary
16 enum { Max_msis = 0x40 };
17 Irq_chip_msi() : Irq_chip_ia32(Max_msis) {}
20 class Irq_mgr_msi : public Irq_mgr
23 mutable Irq_chip_msi _chip;
29 Irq_chip_msi::chip_type() const
34 Irq_chip_msi::alloc(Irq_base *irq, Mword pin)
36 return valloc(irq, pin, 0);
41 Irq_chip_msi::unbind(Irq_base *irq)
43 extern char entry_int_apic_ignore[];
44 //Mword n = irq->pin();
45 // hm: no way to mask an MSI: mask(n);
46 vfree(irq, &entry_int_apic_ignore);
47 Irq_chip_icu::unbind(irq);
52 Irq_chip_msi::msg(Mword pin)
55 return _entry[pin].vector();
61 Irq_chip_msi::set_mode(Mword, Mode)
65 Irq_chip_msi::is_edge_triggered(Mword) const
69 Irq_chip_msi::set_cpu(Mword, Cpu_number)
73 Irq_chip_msi::mask(Mword)
77 Irq_chip_msi::ack(Mword)
78 { ::Apic::irq_ack(); }
81 Irq_chip_msi::mask_and_ack(Mword)
82 { ::Apic::irq_ack(); }
85 Irq_chip_msi::unmask(Mword)
89 PUBLIC inline explicit
90 Irq_mgr_msi::Irq_mgr_msi(Irq_mgr *o) : _orig(o) {}
93 Irq_mgr_msi::chip(Mword irq) const
96 return Irq(&_chip, irq & ~0x80000000);
98 return _orig->chip(irq);
103 Irq_mgr_msi::nr_irqs() const
104 { return _orig->nr_irqs(); }
108 Irq_mgr_msi::nr_msis() const
109 { return _chip.nr_irqs(); }
113 Irq_mgr_msi::msg(Mword irq) const
115 if (irq & 0x80000000)
116 return _chip.msg(irq & ~0x80000000);
122 Irq_mgr_msi::legacy_override(Mword irq)
124 if (irq & 0x80000000)
127 return _orig->legacy_override(irq);
131 PUBLIC static FIASCO_INIT
136 Irq_mgr::mgr = m = new Boot_object<Irq_mgr_msi>(Irq_mgr::mgr);
137 printf("Enable MSI support: chained IRQ mgr @ %p\n", m->_orig);
140 STATIC_INITIALIZE(Irq_mgr_msi);