8 class Vm_svm : public Vm
11 static void resume_vm_svm(Mword phys_vmcb, Vcpu_state *regs)
12 asm("resume_vm_svm") __attribute__((__regparm__(3)));
13 Unsigned8 _asid[Config::Max_num_cpus];
14 Unsigned32 _asid_generation[Config::Max_num_cpus];
23 // ------------------------------------------------------------------------
24 INTERFACE [svm && debug]:
28 EXTENSION class Vm_svm
31 struct Log_vm_svm_exit : public Tb_entry
33 Mword exitcode, exitinfo1, exitinfo2, rip;
34 unsigned print(int max, char *buf) const;
39 // ------------------------------------------------------------------------
43 #include "mem_space.h"
47 #include "thread.h" // XXX: circular dep, move this out here!
48 #include "thread_state.h" // XXX: circular dep, move this out here!
51 // ------------------------------------------------------------------------
52 IMPLEMENTATION [svm && ia32]:
56 PRIVATE inline NEEDS["virt.h"]
58 Vm_svm::get_vm_cr3(Vmcb *)
60 // When running in 32bit mode we already return the page-table of our Vm
61 // object, whether we're running with shadow or nested paging
65 //----------------------------------------------------------------------------
66 IMPLEMENTATION [svm && amd64]:
68 #include "assert_opt.h"
71 PRIVATE inline NEEDS["assert_opt.h", "virt.h"]
73 Vm_svm::get_vm_cr3(Vmcb *v)
75 // When we have nested paging, we just return the 4lvl host page-table of
80 // When running with shadow paging and the guest is running in long mode
81 // and has paging enabled, we can just return the 4lvl page table of our
83 if ( (v->state_save_area.efer & EFER_LME)
84 && (v->state_save_area.cr0 & CR0_PG))
87 // Now it's getting tricky when running with shadow paging.
88 // We need to obey the following rules:
89 // - When the guest is not running in 64bit mode the CR3 one can set for
90 // the page-table must be below 4G physical memory (i.e. bit 32-63 must
91 // be zero). This is unfortunate when the host has memory above 4G as
92 // Fiasco gets its memory from the end of physical memory, i.e.
93 // page-table memory is above 4G.
94 // - We need an appropriate page-table format for 32bit!
95 // That means either a 2lvl page-table or a 3lvl PAE one. That would
96 // require to maintain two page-tables for the guest, one for 32bit
97 // mode execution and one for 64 bit execution. It is needed either for
98 // the transition from real to long-mode via protected mode or for
100 // There's one trick to avoid having two PTs: 4lvl-PTs and 3lvl-PAE-PTs
101 // have much in common so that it's possible to just take the the PDPE
102 // one of the host as the 3lvl-PAE-PT for the guest. Well, not quite.
103 // The problem is that SVM checks that MBZ bits in the PAE-PT entries
104 // are really 0 as written in the spec. Now the 4lvl PT contains rights
105 // bits there, so that this type of PT is refused and does not work on
107 // So why is the code still here? Well, QEmu isn't so picky about the
108 // bits in the PDPE and it thus works there...
110 Address vm_cr3 = static_cast<Mem_space*>(this)->dir()->walk(Virt_addr(0), 0).e->addr();
111 if (EXPECT_FALSE(!vm_cr3))
113 // force allocation of new secondary page-table level
114 static_cast<Mem_space*>(this)->dir()
115 ->walk(Virt_addr(0), 1, Kmem_alloc::q_allocator(ram_quota()));
116 vm_cr3 = static_cast<Mem_space*>(this)->dir()->walk(Virt_addr(0), 0).e->addr();
119 if (EXPECT_FALSE(vm_cr3 >= 1UL << 32))
121 WARN("svm: Host page-table not under 4G, sorry.\n");
128 //----------------------------------------------------------------------------
129 IMPLEMENTATION [svm]:
135 return _asid[current_cpu()];
140 Vm_svm::asid(Unsigned8 asid)
142 _asid[current_cpu()] = asid;
147 Vm_svm::asid_generation()
149 return _asid_generation[current_cpu()];
154 Vm_svm::asid_generation(Unsigned32 generation)
156 _asid_generation[current_cpu()] = generation;
160 Vm_svm::Vm_svm(Ram_quota *q)
163 memset(_asid, 0, sizeof(_asid));
164 memset(_asid_generation, 0, sizeof(_asid_generation));
169 Vm_svm::operator new (size_t size, void *p) throw()
172 assert (size == sizeof (Vm_svm));
178 Vm_svm::operator delete (void *ptr)
180 Vm_svm *t = reinterpret_cast<Vm_svm*>(ptr);
181 allocator<Vm_svm>()->q_free(t->ram_quota(), ptr);
187 // - force fpu ownership
188 // - debug registers not covered by VMCB
192 Vm_svm::copy_state_save_area(Vmcb *dest, Vmcb *src)
194 Vmcb_state_save_area *d = &dest->state_save_area;
195 Vmcb_state_save_area *s = &src->state_save_area;
197 d->es_sel = s->es_sel;
198 d->es_attrib = s->es_attrib;
199 d->es_limit = s->es_limit;
200 d->es_base = s->es_base;
202 d->cs_sel = s->cs_sel;
203 d->cs_attrib = s->cs_attrib;
204 d->cs_limit = s->cs_limit;
205 d->cs_base = s->cs_base;
207 d->ss_sel = s->ss_sel;
208 d->ss_attrib = s->ss_attrib;
209 d->ss_limit = s->ss_limit;
210 d->ss_base = s->ss_base;
212 d->ds_sel = s->ds_sel;
213 d->ds_attrib = s->ds_attrib;
214 d->ds_limit = s->ds_limit;
215 d->ds_base = s->ds_base;
217 d->fs_sel = s->fs_sel;
218 d->fs_attrib = s->fs_attrib;
219 d->fs_limit = s->fs_limit;
220 d->fs_base = s->fs_base;
222 d->gs_sel = s->gs_sel;
223 d->gs_attrib = s->gs_attrib;
224 d->gs_limit = s->gs_limit;
225 d->gs_base = s->gs_base;
227 d->gdtr_sel = s->gdtr_sel;
228 d->gdtr_attrib = s->gdtr_attrib;
229 d->gdtr_limit = s->gdtr_limit;
230 d->gdtr_base = s->gdtr_base;
232 d->ldtr_sel = s->ldtr_sel;
233 d->ldtr_attrib = s->ldtr_attrib;
234 d->ldtr_limit = s->ldtr_limit;
235 d->ldtr_base = s->ldtr_base;
237 d->idtr_sel = s->idtr_sel;
238 d->idtr_attrib = s->idtr_attrib;
239 d->idtr_limit = s->idtr_limit;
240 d->idtr_base = s->idtr_base;
242 d->tr_sel = s->tr_sel;
243 d->tr_attrib = s->tr_attrib;
244 d->tr_limit = s->tr_limit;
245 d->tr_base = s->tr_base;
255 d->rflags = s->rflags;
264 d->sfmask = s->sfmask;
265 d->kernelgsbase = s->kernelgsbase;
266 d->sysenter_cs = s->sysenter_cs;
267 d->sysenter_esp = s->sysenter_esp;
268 d->sysenter_eip = s->sysenter_eip;
272 d->dbgctl = s->dbgctl;
273 d->br_from = s->br_from;
275 d->lastexcpfrom = s->lastexcpfrom;
276 d->last_excpto = s->last_excpto;
282 Vm_svm::copy_control_area(Vmcb *dest, Vmcb *src)
284 Vmcb_control_area *d = &dest->control_area;
285 Vmcb_control_area *s = &src->control_area;
287 d->intercept_rd_crX = s->intercept_rd_crX;
288 d->intercept_wr_crX = s->intercept_wr_crX;
290 d->intercept_rd_drX = s->intercept_rd_drX;
291 d->intercept_wr_drX = s->intercept_wr_drX;
293 d->intercept_exceptions = s->intercept_exceptions;
295 d->intercept_instruction0 = s->intercept_instruction0;
296 d->intercept_instruction1 = s->intercept_instruction1;
298 // skip iopm_base_pa and msrpm_base_pa
300 d->tsc_offset = s->tsc_offset;
301 d->guest_asid_tlb_ctl = s->guest_asid_tlb_ctl;
302 d->interrupt_ctl = s->interrupt_ctl;
303 d->interrupt_shadow = s->interrupt_shadow;
304 d->exitcode = s->exitcode;
305 d->exitinfo1 = s->exitinfo1;
306 d->exitinfo2 = s->exitinfo2;
307 d->exitintinfo = s->exitintinfo;
308 d->np_enable = s->np_enable;
310 d->eventinj = s->eventinj;
312 d->lbr_virtualization_enable = s->lbr_virtualization_enable;
316 /* skip anything that does not change */
319 Vm_svm::copy_control_area_back(Vmcb *dest, Vmcb *src)
321 Vmcb_control_area *d = &dest->control_area;
322 Vmcb_control_area *s = &src->control_area;
324 d->interrupt_ctl = s->interrupt_ctl;
325 d->interrupt_shadow = s->interrupt_shadow;
327 d->exitcode = s->exitcode;
328 d->exitinfo1 = s->exitinfo1;
329 d->exitinfo2 = s->exitinfo2;
330 d->exitintinfo = s->exitintinfo;
332 d->eventinj = s->eventinj;
335 /** \brief Choose an ASID for this Vm.
337 * Choose an ASID for this Vm. The ASID provided by userspace is ignored
338 * instead the kernel picks one.
339 * Userspace uses the flush-bit to receive a new ASID for this Vm.
340 * All ASIDs are flushed as soon as the kernel runs out of ASIDs.
342 * @param vmcb_s external VMCB provided by userspace
343 * @param kernel_vmcb_s our VMCB
348 Vm_svm::configure_asid(Vmcb *vmcb_s, Vmcb *kernel_vmcb_s)
350 assert (cpu_lock.test());
352 Svm &s = Svm::cpus.cpu(current_cpu());
354 if (// vmm requests flush
355 ((vmcb_s->control_area.guest_asid_tlb_ctl >> 32) & 1) == 1 ||
356 // our asid is not valid or expired
357 !(s.asid_valid(asid(), asid_generation())))
360 asid_generation(s.global_asid_generation());
363 assert(s.asid_valid(asid(), asid_generation()));
365 kernel_vmcb_s->control_area.guest_asid_tlb_ctl = asid();
366 if (s.flush_all_asids())
368 kernel_vmcb_s->control_area.guest_asid_tlb_ctl |= (1ULL << 32);
369 s.flush_all_asids(false);
372 kernel_vmcb_s->control_area.guest_asid_tlb_ctl = 1;
373 kernel_vmcb_s->control_area.guest_asid_tlb_ctl |= (1ULL << 32);
377 PRIVATE inline NOEXPORT
379 Vm_svm::do_resume_vcpu(Context *ctxt, Vcpu_state *vcpu, Vmcb *vmcb_s)
382 Unsigned64 orig_cr3, orig_ncr3;
384 assert (cpu_lock.test());
386 /* these 4 must not use ldt entries */
387 assert (!(Cpu::get_cs() & (1 << 2)));
388 assert (!(Cpu::get_ss() & (1 << 2)));
389 assert (!(Cpu::get_ds() & (1 << 2)));
390 assert (!(Cpu::get_es() & (1 << 2)));
392 Svm &s = Svm::cpus.cpu(current_cpu());
394 // FIXME: this can be an assertion I think, however, think about MP
395 if (EXPECT_FALSE(!s.svm_enabled()))
397 WARN("svm: not supported/enabled\n");
398 return -L4_err::EInval;
401 if (EXPECT_FALSE(vmcb_s->np_enabled() && !s.has_npt()))
403 WARN("svm: No NPT available\n");
404 return -L4_err::EInval;
407 Address vm_cr3 = get_vm_cr3(vmcb_s);
408 // can only fail on 64bit, will be optimized away on 32bit
409 if (EXPECT_FALSE(is_64bit() && !vm_cr3))
410 return -L4_err::ENomem;
412 // neither EFER.LME nor EFER.LMA must be set
413 if (EXPECT_FALSE(!is_64bit()
414 && (vmcb_s->state_save_area.efer & (EFER_LME | EFER_LMA))))
416 WARN("svm: EFER invalid %llx\n", vmcb_s->state_save_area.efer);
417 return -L4_err::EInval;
420 // EFER.SVME must be set
421 if (!(vmcb_s->state_save_area.efer & 0x1000))
423 WARN("svm: EFER invalid %llx\n", vmcb_s->state_save_area.efer);
424 return -L4_err::EInval;
426 // allow PAE in combination with NPT
428 // CR4.PAE must be clear
429 if(vmcb_s->state_save_area.cr4 & 0x20)
430 return -L4_err::EInval;
434 // This generates a circular dep between thread<->task, this cries for a
435 // new abstraction...
436 if (!(ctxt->state() & Thread_fpu_owner))
438 if (!static_cast<Thread*>(ctxt)->switchin_fpu())
440 WARN("svm: switchin_fpu failed\n");
441 return -L4_err::EInval;
445 #if 0 //should never happen
446 host_cr0 = Cpu::get_cr0();
447 // the VMM does not currently own the fpu but wants to
448 // make it available for the guest. This may happen
449 // if it was descheduled between activating the fpu and
450 // executing the vm_run operation
451 if (!(vmcb_s->state_save_area.cr0 & 0x8) && (host_cr0 & 0x8))
453 WARN("svm: FPU TS\n");
454 return commit_result(-L4_err::EInval);
458 // increment our refcount, and drop it at the end automatically
459 Ref_ptr<Vm_svm> pin_myself(this);
463 orig_cr3 = vmcb_s->state_save_area.cr3;
464 orig_ncr3 = vmcb_s->control_area.n_cr3;
466 Vmcb *kernel_vmcb_s = s.kernel_vmcb();
468 copy_control_area(kernel_vmcb_s, vmcb_s);
469 copy_state_save_area(kernel_vmcb_s, vmcb_s);
471 if (EXPECT_FALSE(is_64bit() && !kernel_vmcb_s->np_enabled()
472 && (kernel_vmcb_s->state_save_area.cr0 & CR0_PG)
473 && !(kernel_vmcb_s->state_save_area.cr4 & CR4_PAE)))
475 WARN("svm: No 32bit shadow page-tables on AMD64, use PAE!\n");
476 return -L4_err::EInval;
479 // set MCE according to host
480 kernel_vmcb_s->state_save_area.cr4 |= Cpu::get_cr4() & CR4_MCE;
482 // allow w access to cr0, cr2, cr3
483 // allow r access to cr0, cr2, cr3, cr4
484 // to do: check if enabling PAE in cr4 needs to be controlled
486 // allow r/w access to dr[0-7]
487 kernel_vmcb_s->control_area.intercept_rd_drX |= 0xff00;
488 kernel_vmcb_s->control_area.intercept_wr_drX |= 0xff00;
491 // intercept exception vectors 0-31
492 kernel_vmcb_s->control_area.intercept_exceptions = 0xffffffff;
495 // enable iopm and msrpm
496 kernel_vmcb_s->control_area.intercept_instruction0 |= 0x18000000;
497 // intercept FERR_FREEZE and shutdown events
498 kernel_vmcb_s->control_area.intercept_instruction0 |= 0xc0000000;
499 // intercept INTR/NMI/SMI/INIT
500 kernel_vmcb_s->control_area.intercept_instruction0 |= 0xf;
502 kernel_vmcb_s->control_area.intercept_instruction0 |= (1 << 22);
504 kernel_vmcb_s->control_area.intercept_instruction0 |= (1 << 24);
505 // intercept task switch
506 kernel_vmcb_s->control_area.intercept_instruction0 |= (1 << 29);
507 // intercept shutdown
508 kernel_vmcb_s->control_area.intercept_instruction0 |= (1 << 31);
509 // intercept MONITOR/MWAIT
510 kernel_vmcb_s->control_area.intercept_instruction1 |= (1 << 10) | (1 << 11);
512 // intercept virtualization related instructions
513 // vmrun interception is required by the hardware
514 kernel_vmcb_s->control_area.intercept_instruction1 |= 0xff;
516 Mword kernel_vmcb_pa = s.kernel_vmcb_pa();
517 Unsigned64 iopm_base_pa = s.iopm_base_pa();
518 Unsigned64 msrpm_base_pa = s.msrpm_base_pa();
520 kernel_vmcb_s->control_area.iopm_base_pa = iopm_base_pa;
521 kernel_vmcb_s->control_area.msrpm_base_pa = msrpm_base_pa;
523 configure_asid(vmcb_s, kernel_vmcb_s);
525 // 7:0 V_TPR, 8 V_IRQ, 15:9 reserved SBZ,
526 // 19:16 V_INTR_PRIO, 20 V_IGN_TPR, 23:21 reserved SBZ
527 // 24 V_INTR_MASKING 31:25 reserved SBZ
528 // 39:32 V_INTR_VECTOR, 63:40 reserved SBZ
530 kernel_vmcb_s->control_area.interrupt_ctl = 0x10f0000;
532 // enable IRQ masking virtualization
533 kernel_vmcb_s->control_area.interrupt_ctl |= 0x01000000;
536 // 0 INTERRUPT_SHADOW, 31:1 reserved SBZ
537 // 63:32 reserved SBZ
538 kernel_vmcb_s->control_area.interrupt_shadow = 0;
541 kernel_vmcb_s->control_area.exitcode = 0;
542 kernel_vmcb_s->control_area.exitinfo1 = 0;
543 kernel_vmcb_s->control_area.exitinfo2 = 0;
544 kernel_vmcb_s->control_area.exitintinfo = 0;
547 // 0/1 NP_ENABLE, 31:1 reserved SBZ
548 kernel_vmcb_s->control_area.np_enable = 1;
550 // 31 VALID, EVENTINJ
551 kernel_vmcb_s->control_area.eventinj = 0;
555 kernel_vmcb_s->control_area.n_cr3 = vm_cr3;
557 if (!kernel_vmcb_s->np_enabled())
559 // to do: check that the vmtask has the
560 // VM property set, i.e. does not contain mappings
561 // to the fiasco kernel regions or runs with PL 3
563 // printf("nested paging disabled, use n_cr3 as cr3\n");
564 kernel_vmcb_s->state_save_area.cr3 = vm_cr3;
566 // intercept accesses to cr0, cr3 and cr4
567 kernel_vmcb_s->control_area.intercept_rd_crX = 0xfff9;
568 kernel_vmcb_s->control_area.intercept_wr_crX = 0xfff9;
572 kernel_vmcb_s->control_area.lbr_virtualization_enable = 0;
577 // - initialize VM_HSAVE_PA (done)
578 // - supply trusted msrpm_base_pa and iopm_base_pa (done)
579 // - save host state not covered by VMRUN/VMEXIT (ldt, some segments etc) (done)
580 // - disable interupts (done)
581 // - trigger interecepted device and timer interrupts (done, not necessary)
582 // - check host CR0.TS (floating point registers) (done)
584 Unsigned64 sysenter_cs, sysenter_eip, sysenter_esp;
589 sysenter_cs = Cpu::rdmsr(MSR_SYSENTER_CS);
590 sysenter_eip = Cpu::rdmsr(MSR_SYSENTER_EIP);
591 sysenter_esp = Cpu::rdmsr(MSR_SYSENTER_ESP);
596 ldtr = Cpu::get_ldt();
600 tr_entry = (*Cpu::cpus.cpu(current_cpu()).get_gdt())[tr / 8];
603 // to do: check if the nested page table walker looks
604 // into the TLB. if so, global pages have to be disabled in
606 cr4 = Cpu::get_cr4();
609 // disable support for global pages as the vm task has
610 // a divergent upper memory region from the regular tasks
611 Cpu::set_cr4(cr4 & ~CR4_PGE);
614 resume_vm_svm(kernel_vmcb_pa, vcpu);
622 Cpu::wrmsr(sysenter_cs, MSR_SYSENTER_CS);
623 Cpu::wrmsr(sysenter_eip, MSR_SYSENTER_EIP);
624 Cpu::wrmsr(sysenter_esp, MSR_SYSENTER_ESP);
633 tss_entry = (*Cpu::cpus.cpu(current_cpu()).get_gdt())[tr / 8];
634 tss_entry.access &= 0xfd;
635 (*Cpu::cpus.cpu(current_cpu()).get_gdt())[tr / 8] = tss_entry;
637 Cpu::set_tr(tr); // TODO move under stgi in asm
639 copy_state_save_area(vmcb_s, kernel_vmcb_s);
640 copy_control_area_back(vmcb_s, kernel_vmcb_s);
642 if (!(vmcb_s->np_enabled()))
643 vmcb_s->state_save_area.cr3 = orig_cr3;
645 vmcb_s->control_area.n_cr3 = orig_ncr3;
647 LOG_TRACE("VM-SVM", "svm", current(), Log_vm_svm_exit,
648 l->exitcode = vmcb_s->control_area.exitcode;
649 l->exitinfo1 = vmcb_s->control_area.exitinfo1;
650 l->exitinfo2 = vmcb_s->control_area.exitinfo2;
651 l->rip = vmcb_s->state_save_area.rip;
654 // check for IRQ exit
655 if (kernel_vmcb_s->control_area.exitcode == 0x60)
658 vcpu->state &= ~(Vcpu_state::F_traps | Vcpu_state::F_user_mode);
664 Vm_svm::resume_vcpu(Context *ctxt, Vcpu_state *vcpu, bool user_mode)
667 assert_kdb (user_mode);
669 if (EXPECT_FALSE(!(ctxt->state(true) & Thread_ext_vcpu_enabled)))
671 ctxt->arch_load_vcpu_kern_state(vcpu, true);
672 return -L4_err::EInval;
675 Vmcb *vmcb_s = reinterpret_cast<Vmcb*>(reinterpret_cast<char *>(vcpu) + 0x400);
678 // in the case of disabled IRQs and a pending IRQ directly simulate an
679 // external interrupt intercept
680 if ( !(vcpu->_saved_state & Vcpu_state::F_irqs)
681 && (vcpu->sticky_flags & Vcpu_state::Sf_irq_pending))
683 vmcb_s->control_area.exitcode = 0x60;
684 ctxt->arch_load_vcpu_kern_state(vcpu, true);
685 return 1; // return 1 to indicate pending IRQs (IPCs)
688 int r = do_resume_vcpu(ctxt, vcpu, vmcb_s);
690 // test for error or non-IRQ exit reason
693 ctxt->arch_load_vcpu_kern_state(vcpu, true);
697 // check for IRQ exits and allow to handle the IRQ
699 Proc::preemption_point();
701 // Check if the current context got a message delivered.
702 // This is done by testing for a valid continuation.
703 // When a continuation is set we have to directly
704 // leave the kernel to not overwrite the vcpu-regs
706 Thread *t = nonull_static_cast<Thread*>(ctxt);
708 if (t->continuation_test_and_restore())
710 ctxt->arch_load_vcpu_kern_state(vcpu, true);
711 t->fast_return_to_user(vcpu->_entry_ip, vcpu->_entry_sp,
712 t->vcpu_state().usr().get());
719 // ------------------------------------------------------------------------
720 IMPLEMENTATION [svm && debug]:
724 Vm_svm::Log_vm_svm_exit::print(int max, char *buf) const
726 return snprintf(buf, max, "ec=%lx ei1=%08lx ei2=%08lx rip=%08lx",
727 exitcode, exitinfo1, exitinfo2, rip);