2 * (c) 2009 Adam Lackorzynski <adam@os.inf.tu-dresden.de>
3 * economic rights: Technische Universität Dresden (Germany)
5 * This file is part of TUD:OS and distributed under the terms of the
6 * GNU General Public License 2.
7 * Please see the COPYING-GPL-2 file for details.
9 #include "uart_s3c2410.h"
14 ULCON = 0x0, // line control register
15 UCON = 0x4, // control register
16 UFCON = 0x8, // FIFO control register
17 UMCON = 0xc, // modem control register
18 UTRSTAT = 0x10, // Tx/Rx status register
19 UERSTAT = 0x14, // Rx error status register
20 UFSTAT = 0x18, // FIFO status register
21 UMSTAT = 0x1c, // modem status register
22 UTXH = 0x20, // transmit buffer register (little endian, 0x23 for BE)
23 URXH = 0x24, // receive buffer register (little endian, 0x27 for BE)
24 UBRDIV = 0x28, // baud rate divisor register
30 UFSTAT_Rx_COUNT_MASK = 0x00f,
31 UFSTAT_Tx_COUNT_MASK = 0x0f0,
32 UFSTAT_RxFULL = 0x100,
33 UFSTAT_TxFULL = 0x200,
37 UTRSTAT_Rx_RDY = 1 << 0,
38 UTRSTAT_Tx_RDY = 1 << 1,
42 unsigned long Uart_s3c2410::rd(unsigned long reg) const
44 return *(volatile unsigned long*)(_base + reg);
47 void Uart_s3c2410::wr(unsigned long reg, unsigned long val) const
49 *(volatile unsigned long *)(_base + reg) = val;
52 void Uart_s3c2410::fifo_reset()
54 wr(UFCON, 7); // enable + fifo reset
57 bool Uart_s3c2410::startup(unsigned long base)
64 wr(ULCON, ULCON_8N1_MODE);
68 for (int i=0; i < 1000; ++i)
74 void Uart_s3c2410::shutdown()
79 bool Uart_s3c2410::enable_rx_irq(bool /*enable*/)
84 bool Uart_s3c2410::enable_tx_irq(bool /*enable*/) { return false; }
86 bool Uart_s3c2410::change_mode(Transfer_mode, Baud_rate r)
91 wr(ULCON, ULCON_8N1_MODE);
100 int Uart_s3c2410::get_char(bool blocking) const
102 while (!char_avail())
106 int uer = rd(UERSTAT);
117 int Uart_s3c2410::char_avail() const
119 //return rd(UTRSTAT) & UTRSTAT_Rx_RDY;
120 //return rd(UFSTAT) & UFSTAT_Rx_COUNT_MASK;
121 return rd(UFSTAT) & (UFSTAT_Rx_COUNT_MASK | UFSTAT_RxFULL);
124 void Uart_s3c2410::out_char(char c) const
126 //while (!(rd(UTRSTAT) & UTRSTAT_Tx_RDY))
127 while (rd(UFSTAT) & UFSTAT_TxFULL)
129 //while (!(rd(UMSTAT) & 0x1))
134 int Uart_s3c2410::write(char const *s, unsigned long count) const
136 unsigned long c = count;
144 while (!(rd(UTRSTAT) & UTRSTAT_Tx_RDY))
145 //while (rd(UFSTAT) & UFSTAT_Tx_COUNT_MASK)
151 void Uart_s3c2410::auto_flow_control(bool on)
153 wr(UMCON, (rd(UMCON) & ~UMCON_AFC) | (on ? UMCON_AFC : 0));