1 INTERFACE [arm && mp && omap4]:
9 IMPLEMENTATION [arm && mp && omap4]:
16 Boot_mp::aux(unsigned cmd, Mword arg0, Mword arg1)
18 register unsigned long r0 asm("r0") = arg0;
19 register unsigned long r1 asm("r1") = arg1;
20 register unsigned long r12 asm("r12") = cmd;
22 asm volatile("dsb; smc #0"
23 : : "r" (r0), "r" (r1), "r" (r12)
24 : "r2", "r3", "r4", "r5", "r6",
25 "r7", "r8", "r9", "r10", "r11", "lr", "memory");
30 Boot_mp::start_ap_cpus(Address phys_tramp_mp_addr)
32 // two possibilities available, the memory mapped only in later board
37 AUX_CORE_BOOT_0 = 0x104,
38 AUX_CORE_BOOT_1 = 0x105,
40 aux(AUX_CORE_BOOT_1, phys_tramp_mp_addr, 0);
41 asm volatile("dsb; sev" : : : "memory");
42 aux(AUX_CORE_BOOT_0, 0x200, 0xfffffdff);
47 AUX_CORE_BOOT_0 = Kmem::Devices2_map_base + 0x81800,
48 AUX_CORE_BOOT_1 = Kmem::Devices2_map_base + 0x81804,
50 Io::write<Mword>(phys_tramp_mp_addr, AUX_CORE_BOOT_1);
51 asm volatile("dsb; sev" : : : "memory");
52 Io::write<Mword>((Io::read<Mword>(AUX_CORE_BOOT_0) & ~0xfffffdff) | 0x200,