1 #include "uart_s3c2410.h"
8 ULCON = OFFSET + 0x0, // line control register
9 UCON = OFFSET + 0x4, // control register
10 UFCON = OFFSET + 0x8, // FIFO control register
11 UMCON = OFFSET + 0xc, // modem control register
12 UTRSTAT = OFFSET + 0x10, // Tx/Rx status register
13 UERSTAT = OFFSET + 0x14, // Rx error status register
14 UFSTAT = OFFSET + 0x18, // FIFO status register
15 UMSTAT = OFFSET + 0x1c, // modem status register
16 UTXH = OFFSET + 0x20, // transmit buffer register (little endian, 0x23 for BE)
17 URXH = OFFSET + 0x24, // receive buffer register (little endian, 0x27 for BE)
18 UBRDIV = OFFSET + 0x28, // baud rate divisor register
22 UCON_MODE = 0x045 | (1 << 7),
24 UFSTAT_Rx_COUNT_MASK = 0x00f,
25 UFSTAT_Tx_COUNT_MASK = 0x0f0,
26 UFSTAT_RxFULL = 0x100,
27 UFSTAT_TxFULL = 0x200,
31 unsigned long Uart_s3c2410::rd(unsigned long reg) const
33 volatile unsigned long *r = (unsigned long*)(_base + reg);
37 void Uart_s3c2410::wr(unsigned long reg, unsigned long val) const
39 volatile unsigned long *r = (unsigned long*)(_base + reg);
43 bool Uart_s3c2410::startup(unsigned long base)
47 wr(ULCON, ULCON_8N1_MODE);
55 void Uart_s3c2410::shutdown()
60 bool Uart_s3c2410::enable_rx_irq(bool enable)
63 bool Uart_s3c2410::enable_tx_irq(bool /*enable*/) { return false; }
65 bool Uart_s3c2410::change_mode(Transfer_mode, Baud_rate r)
70 wr(ULCON, ULCON_8N1_MODE);
79 int Uart_s3c2410::get_char(bool blocking) const
82 if (!blocking) return -1;
84 int c = rd(URXH) & 0xff;
88 int Uart_s3c2410::char_avail() const
90 return rd(UFSTAT) & UFSTAT_Rx_COUNT_MASK;
93 void Uart_s3c2410::out_char(char c) const
95 while (rd(UFSTAT) & UFSTAT_TxFULL)
100 int Uart_s3c2410::write(char const *s, unsigned long count) const
102 unsigned long c = count;
110 while (rd(UFSTAT) & UFSTAT_Tx_COUNT_MASK)