1 INTERFACE [arm && pxa]: // -------------------------------------
10 Multi_irq_pending = 1,
15 ICIP = Kmem::Pic_map_base + 0x000000,
16 ICMR = Kmem::Pic_map_base + 0x000004,
17 ICLR = Kmem::Pic_map_base + 0x000008,
18 ICCR = Kmem::Pic_map_base + 0x000014,
19 ICFP = Kmem::Pic_map_base + 0x00000c,
20 ICPR = Kmem::Pic_map_base + 0x000010,
24 INTERFACE [arm && sa1100]: // ----------------------------------
33 Multi_irq_pending = 1,
38 ICIP = Kmem::Pic_map_base + 0x00000,
39 ICMR = Kmem::Pic_map_base + 0x00004,
40 ICLR = Kmem::Pic_map_base + 0x00008,
41 ICCR = Kmem::Pic_map_base + 0x0000c,
42 ICFP = Kmem::Pic_map_base + 0x00010,
43 ICPR = Kmem::Pic_map_base + 0x00020,
47 // -------------------------------------------------------------
48 IMPLEMENTATION [arm && (sa1100 || pxa)]:
53 #include "boot_info.h"
55 #include "initcalls.h"
58 #include "irq_chip_generic.h"
62 class Pxa_sa_pin : public Irq_pin
65 explicit Pxa_sa_pin(unsigned irq) { payload()[0] = irq; }
66 unsigned irq() const { return payload()[0]; }
69 class Irq_chip_arm_pxa_sa : public Irq_chip_gen
75 Irq_chip_arm_pxa_sa::setup(Irq_base *irq, unsigned irqnum)
77 irq->pin()->replace<Pxa_sa_pin>(irqnum);
82 Pxa_sa_pin::unbind_irq()
86 Irq_chip::hw_chip->free(Irq::self(this), irq());
87 replace<Sw_irq_pin>();
94 assert (cpu_lock.test());
95 Io::write(Io::read<Mword>(Pic::ICMR) & ~(1 << irq()), Pic::ICMR);
100 Pxa_sa_pin::do_mask_and_ack()
102 assert (cpu_lock.test());
104 Io::write(Io::read<Mword>(Pic::ICMR) & ~(1 << irq()), Pic::ICMR);
117 Pxa_sa_pin::do_unmask()
119 Io::write(Io::read<Mword>(Pic::ICMR) | (1 << irq()), Pic::ICMR);
124 Pxa_sa_pin::do_set_mode(unsigned)
130 Pxa_sa_pin::check_debug_irq()
132 return !Vkey::check_(irq());
137 Pxa_sa_pin::set_cpu(unsigned)
143 IMPLEMENT FIASCO_INIT
146 // only unmasked interrupts wakeup from idle
147 Io::write(0x01, ICCR);
148 // mask all interrupts
149 Io::write(0x00, ICMR);
150 // all interrupts are IRQ's (no FIQ)
151 Io::write(0x00, ICLR);
154 IMPLEMENT inline NEEDS["io.h"]
155 Pic::Status Pic::disable_all_save()
158 s = Io::read<Mword>(ICMR);
163 IMPLEMENT inline NEEDS["io.h"]
164 void Pic::restore_all( Status s )
169 PUBLIC static inline NEEDS["io.h"]
170 Unsigned32 Pic::pending()
172 return Io::read<Unsigned32>(ICIP);
175 PUBLIC static inline NEEDS[Pic::pending]
176 Mword Pic::is_pending(Mword &irqs, Mword irq)
178 Mword ret = irqs & (1 << irq);
183 // -------------------------------------------------------------
184 IMPLEMENTATION [arm && debug && (sa1100 || pxa)]:
188 Pxa_sa_pin::pin_type() const
189 { return "HW PXA/SA IRQ"; }