1 /* This file is lisenced under LGPL.
2 * Copyright (C) 2002-2003, George Thanos <george.thanos@gdt.gr>
3 * Yannis Mitsos <yannis.mitsos@gdt.gr>
5 #ifndef _BITS_UNISTD_H_
6 #define _BITS_UNISTD_H_
8 #include <bits/proto.h>
11 #define __E1_COFF_GCC__
13 /* The following macros have been provided by C.Baumhof
14 * They can be inlined in contrast to the previous ones*/
15 #define _syscall0(type, name) \
18 register int par1 __asm__("L15"); \
19 register int par2 __asm__("L14"); \
22 __asm__ __volatile__( \
25 :"0"(par1), "l"(par2) \
26 :"memory","L14","L15"); \
29 __set_errno( -par1 ); \
32 return (type)(par1); \
35 #define _syscall1(type, name,atype, a) \
38 register int par1 __asm__("L15"); \
39 register int par2 __asm__("L14"); \
40 register int par3 __asm__("L13"); \
44 __asm__ __volatile__( \
47 :"0"(par1), "l"(par2), "l"(par3) \
48 :"memory","L13","L14","L15"); \
51 __set_errno( -par1 ); \
54 return (type)(par1); \
57 #define _syscall2(type, name,atype, a, btype, b) \
58 type name(atype a, btype b) \
60 register int par1 __asm__("L15"); \
61 register int par2 __asm__("L14"); \
62 register int par3 __asm__("L13"); \
63 register int par4 __asm__("L12"); \
68 __asm__ __volatile__( \
71 :"0"(par1), "l"(par2), "l"(par3), "l"(par4) \
72 :"memory","L12","L13","L14","L15"); \
75 __set_errno( -par1 ); \
78 return (type)(par1); \
81 #define _syscall3(type, name,atype, a, btype, b, ctype, c) \
82 type name(atype a, btype b, ctype c) \
84 register int par1 __asm__("L15"); \
85 register int par2 __asm__("L14"); \
86 register int par3 __asm__("L13"); \
87 register int par4 __asm__("L12"); \
88 register int par5 __asm__("L11"); \
94 __asm__ __volatile__( \
97 :"0"(par1), "l"(par2), "l"(par3), "l"(par4), "l"(par5) \
98 :"memory","L11","L12","L13","L14","L15"); \
101 __set_errno( -par1 ); \
104 return (type)(par1); \
107 #define _syscall4(type, name,atype, a, btype, b, ctype, c, dtype, d) \
108 type name(atype a, btype b, ctype c,dtype d) \
110 register int par1 __asm__("L15"); \
111 register int par2 __asm__("L14"); \
112 register int par3 __asm__("L13"); \
113 register int par4 __asm__("L12"); \
114 register int par5 __asm__("L11"); \
115 register int par6 __asm__("L10"); \
117 par2 = __NR_##name; \
122 __asm__ __volatile__( \
125 :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6) \
126 :"memory","L10","L11","L12","L13","L14","L15"); \
129 __set_errno( -par1 ); \
132 return (type)(par1); \
135 #define _syscall5(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e) \
136 type name(atype a, btype b, ctype c,dtype d, etype e) \
138 register int par1 __asm__("L15"); \
139 register int par2 __asm__("L14"); \
140 register int par3 __asm__("L13"); \
141 register int par4 __asm__("L12"); \
142 register int par5 __asm__("L11"); \
143 register int par6 __asm__("L10"); \
144 register int par7 __asm__("L9"); \
146 par2 = __NR_##name; \
152 __asm__ __volatile__( \
155 :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7) \
156 :"memory","L9","L10","L11","L12","L13","L14","L15"); \
159 __set_errno( -par1 ); \
162 return (type)(par1); \
163 return (type)(par1); \
166 #define _syscall6(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e, ftype, f) \
167 type name(atype a, btype b, ctype c,dtype d, etype e, ftype f) \
169 register int par1 __asm__("L15"); \
170 register int par2 __asm__("L14"); \
171 register int par3 __asm__("L13"); \
172 register int par4 __asm__("L12"); \
173 register int par5 __asm__("L11"); \
174 register int par6 __asm__("L10"); \
175 register int par7 __asm__("L9"); \
176 register int par8 __asm__("L8"); \
179 par2 = __NR_##name; \
186 __asm__ __volatile__( \
189 :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7),"l"(par8) \
190 :"memory","L8","L9","L10","L11","L12","L13","L14","L15"); \
193 __set_errno( -par1 ); \
196 return (type)(par1); \
199 #define __syscall0(type, name) \
202 register int par1 __asm__("L15"); \
203 register int par2 __asm__("L14"); \
205 par2 = __NR_##name; \
206 __asm__ __volatile__( \
209 :"0"(par1), "l"(par2)\
210 :"memory","L14","L15"); \
213 __set_errno( -par1 ); \
216 return (type)(par1); \
219 #define __syscall1(type, name, atype, a) \
220 type name(atype a, ...) \
222 register int par1 __asm__("L15"); \
223 register int par2 __asm__("L14"); \
224 register int par3 __asm__("L13"); \
226 par2 = __NR_##name; \
228 __asm__ __volatile__( \
231 :"0"(par1), "l"(par2), "l"(par3)\
232 :"memory","L13","L14","L15"); \
235 __set_errno( -par1 ); \
238 return (type)(par1); \
241 #define __syscall2(type, name,atype, a, btype, b) \
242 type name(atype a, btype b, ...) \
244 register int par1 __asm__("L15"); \
245 register int par2 __asm__("L14"); \
246 register int par3 __asm__("L13"); \
247 register int par4 __asm__("L12"); \
249 par2 = __NR_##name; \
252 __asm__ __volatile__( \
255 :"0"(par1), "l"(par2), "l"(par3), "l"(par4)\
256 :"memory","L12","L13","L14","L15"); \
259 __set_errno( -par1 ); \
262 return (type)(par1); \
265 #define __syscall3(type, name,atype, a, btype, b, ctype, c) \
266 type name(atype a, btype b, ctype c, ...) \
268 register int par1 __asm__("L15"); \
269 register int par2 __asm__("L14"); \
270 register int par3 __asm__("L13"); \
271 register int par4 __asm__("L12"); \
272 register int par5 __asm__("L11"); \
274 par2 = __NR_##name; \
278 __asm__ __volatile__( \
281 :"0"(par1), "l"(par2), "l"(par3), "l"(par4), "l"(par5) \
282 :"memory","L11","L12","L13","L14","L15"); \
285 __set_errno( -par1 ); \
288 return (type)(par1); \
291 #define __syscall4(type, name,atype, a, btype, b, ctype, c, dtype, d) \
292 type name(atype a, btype b, ctype c,dtype d, ...) \
294 register int par1 __asm__("L15"); \
295 register int par2 __asm__("L14"); \
296 register int par3 __asm__("L13"); \
297 register int par4 __asm__("L12"); \
298 register int par5 __asm__("L11"); \
299 register int par6 __asm__("L10"); \
301 par2 = __NR_##name; \
306 __asm__ __volatile__( \
309 :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6) \
310 :"memory","L10","L11","L12","L13","L14","L15"); \
313 __set_errno( -par1 ); \
316 return (type)(par1); \
319 #define __syscall5(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e) \
320 type name(atype a, btype b, ctype c,dtype d, etype e, ...) \
322 register int par1 __asm__("L15"); \
323 register int par2 __asm__("L14"); \
324 register int par3 __asm__("L13"); \
325 register int par4 __asm__("L12"); \
326 register int par5 __asm__("L11"); \
327 register int par6 __asm__("L10"); \
328 register int par7 __asm__("L9"); \
330 par2 = __NR_##name; \
336 __asm__ __volatile__( \
339 :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7) \
340 :"memory","L9","L10","L11","L12","L13","L14","L15"); \
343 __set_errno( -par1 ); \
346 return (type)(par1); \
349 #define __syscall6(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e, ftype, f) \
350 type name(atype a, btype b, ctype c,dtype d, etype e, ftype f, ...) \
352 register int par1 __asm__("L15"); \
353 register int par2 __asm__("L14"); \
354 register int par3 __asm__("L13"); \
355 register int par4 __asm__("L12"); \
356 register int par5 __asm__("L11"); \
357 register int par6 __asm__("L10"); \
358 register int par7 __asm__("L9"); \
359 register int par8 __asm__("L8"); \
361 par2 = __NR_##name; \
368 __asm__ __volatile__( \
371 :"0"(par1),"l"(par2),"l"(par3),"l"(par4),"l"(par5),"l"(par6),"l"(par7),"l"(par8) \
372 :"memory","L8","L9","L10","L11","L12","L13","L14","L15"); \
375 __set_errno( -par1 ); \
378 return (type)(par1); \
381 #include <sys/types.h>
382 /* Taken from <bits/errno.h> */
384 /* We don't support pthreads for the moment*/
385 #define __set_errno(val) ((errno) = (val))
389 #define _syscall3(type, name,atype, a , btype, b, ctype, c) \
390 type name(atype a, btype b, ctype c,) \
392 __asm__ __volatile__( \
395 "ldw.d G3, L7, 0\n\t" \
396 "ldw.d G3, L6, 4\n\t" \
397 "ldw.d G3, L5, 8\n\t" \
400 :"cc","memory","%L5","L6","L7","L8","L9");\
401 __asm__ __volatile__( \
406 #define _syscall4(type, name,atype, a, btype, b, ctype, c, dtype, d) \
407 type name(atype a, btype b, ctype c,dtype d) \
409 __asm__ __volatile__( \
412 "ldw.d G3, L9, 0\n\t" \
413 "ldw.d G3, L8, 4\n\t" \
414 "ldw.d G3, L7, 8\n\t" \
415 "ldw.d G3, L6, 12\n\t" \
418 :"cc","memory","L6","L7","L8","L9","L10","L11");\
419 __asm__ __volatile__( \
421 "mov L2, L11\n\t"); \
424 #define _syscall5(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e) \
425 type name(atype a, btype b, ctype c,dtype d, etype e) \
427 __asm__ __volatile__( \
430 "ldw.d G3, L11, 0\n\t" \
431 "ldw.d G3, L10, 4\n\t" \
432 "ldw.d G3, L9, 8\n\t" \
433 "ldw.d G3, L8, 12\n\t" \
434 "ldw.d G3, L7, 16\n\t" \
437 :"cc","memory","L7","L8","L9","L10","L11","L12","L13");\
438 __asm__ __volatile__( \
440 "mov L2, L13\n\t"); \
443 #define _syscall6(type, name,atype, a, btype, b, ctype, c, dtype, d, etype, e, ftype, f) \
444 type name(atype a, btype b, ctype c,dtype d, etype e, ftype f) \
446 __asm__ __volatile__( \
449 "ldw.d G3, L13, 0\n\t" \
450 "ldw.d G3, L12, 4\n\t" \
451 "ldw.d G3, L11, 8\n\t" \
452 "ldw.d G3, L10, 12\n\t" \
453 "ldw.d G3, L9, 16\n\t" \
454 "ldw.d G3, L8, 20\n\t" \
457 :"cc","memory","L8","L9","L10","L11","L12","L13","L14","L15");\
458 __asm__ __volatile__( \
460 "mov L2, L15\n\t"); \
464 #endif /* !_HYPERSTONE_NOMMU_UNISTD_H_ */