10 pci_conf_addr0(l4_uint32_t bus, l4_uint32_t dev,
11 l4_uint32_t fn, l4_uint32_t reg)
12 { return (bus << 16) | (dev << 11) | (fn << 8) | (reg & ~3); }
14 class Pci_iomem_root_bridge : public Pci_root_bridge, public Hw::Device
17 typedef Hw::Pci::Cfg_width Cfg_width;
19 Pci_iomem_root_bridge()
20 : Pci_root_bridge(this), _iobase_virt(0), _iobase_phys(~0UL),
21 _dev_start(~0UL), _dev_end(~0UL), _iosize(0)
23 set_discover_bus_if(this);
26 int cfg_read(unsigned bus, l4_uint32_t devfn, l4_uint32_t reg,
27 l4_uint32_t *value, Cfg_width);
29 int cfg_write(unsigned bus, l4_uint32_t devfn, l4_uint32_t reg,
30 l4_uint32_t value, Cfg_width);
36 int set_property(cxx::String const &prop, Prop_val const &val);
38 int getval(const char *s, cxx::String const &prop,
39 Prop_val const &val, T *rval);
40 int int_map(int i) const { return _int_map[i]; }
43 l4_addr_t _iobase_virt, _iobase_phys, _dev_start, _dev_end;
48 // Irq router that maps INTA-D to GSI
49 class Irq_router_rs : public Resource_space
52 bool request(Resource *parent, Device *, Resource *child, Device *cdev);
53 bool alloc(Resource *, Device *, Resource *, Device *, bool)
58 Pci_iomem_root_bridge::init()
60 if (_iobase_phys == ~0UL)
62 printf("ERROR: Pci_root_bridge: 'iobase' not set.\n");
68 printf("ERROR: Pci_root_bridge: 'iosize' not set.\n");
72 if (_dev_start == ~0UL || _dev_end == ~0UL)
74 printf("ERROR: Pci_root_bridge: 'dev_start' and/or 'dev_end' not set.\n");
78 _iobase_virt = res_map_iomem(_iobase_phys, _iosize);
82 add_resource(new Adr_resource(Resource::Mmio_res
83 | Resource::F_fixed_size
84 | Resource::F_fixed_addr,
86 _iobase_phys + _iosize - 1));
88 Adr_resource *r = new Adr_resource_provider(Resource::Mmio_res
89 | Resource::F_fixed_size
90 | Resource::F_fixed_addr);
91 r->alignment(0xfffff);
92 r->start_end(_dev_start, _dev_end);
95 r = new Adr_resource_provider(Resource::Io_res
96 | Resource::F_fixed_size
97 | Resource::F_fixed_addr);
98 r->start_end(0, 0xffff);
101 add_resource(new Pci_irq_router_res<Irq_router_rs>());
107 Pci_iomem_root_bridge::scan_bus()
111 Pci_root_bridge::scan_bus();
115 Pci_iomem_root_bridge::cfg_read(unsigned bus, l4_uint32_t devfn,
117 l4_uint32_t *value, Cfg_width order)
124 l4_uint32_t a = _iobase_virt + pci_conf_addr0(bus, devfn >> 16, devfn & 0xffff, reg);
127 case Pci::Cfg_byte: *value = *(volatile unsigned char *)(a + (reg & 3)); break;
128 case Pci::Cfg_short: *value = *(volatile unsigned short *)(a + (reg & 2)); break;
129 case Pci::Cfg_long: *value = *(volatile unsigned int *)a; break;
133 printf("Pci_iomem_root_bridge::cfg_read(%x, %x, %x, %x, %d)\n",
134 bus, devfn, reg, *value, order);
140 Pci_iomem_root_bridge::cfg_write(unsigned bus, l4_uint32_t devfn,
142 l4_uint32_t value, Cfg_width order)
150 printf("Pci_iomem_root_bridge::cfg_write(%x, %x, %x, %x, %d)\n",
151 bus, devfn, reg, value, order);
153 l4_uint32_t a = _iobase_virt + pci_conf_addr0(bus, devfn >> 16, devfn & 0xffff, reg);
156 case Pci::Cfg_byte: *(volatile unsigned char *)(a + (reg & 3)) = value; break;
157 case Pci::Cfg_short: *(volatile unsigned short *)(a + (reg & 2)) = value; break;
158 case Pci::Cfg_long: *(volatile unsigned int *)a = value; break;
163 template< typename T>
165 Pci_iomem_root_bridge::getval(const char *s, cxx::String const &prop,
166 Prop_val const &val, T *rval)
170 if (val.type != Prop_val::Int)
173 *rval = val.val.integer;
180 Pci_iomem_root_bridge::set_property(cxx::String const &prop, Prop_val const &val)
184 if ((r = getval("iobase", prop, val, &_iobase_phys)) != -E_no_prop)
186 else if ((r = getval("iosize", prop, val, &_iosize)) != -E_no_prop)
188 else if ((r = getval("dev_start", prop, val, &_dev_start)) != -E_no_prop)
190 else if ((r = getval("dev_end", prop, val, &_dev_end)) != -E_no_prop)
192 else if ((r = getval("int_a", prop, val, &_int_map[0])) != -E_no_prop)
194 else if ((r = getval("int_b", prop, val, &_int_map[1])) != -E_no_prop)
196 else if ((r = getval("int_c", prop, val, &_int_map[2])) != -E_no_prop)
198 else if ((r = getval("int_d", prop, val, &_int_map[3])) != -E_no_prop)
201 return Hw::Device::set_property(prop, val);
204 static Hw::Device_factory_t<Pci_iomem_root_bridge>
205 __hw_pci_root_bridge_factory("Pci_iomem_root_bridge");
207 bool Irq_router_rs::request(Resource *parent, Device *pdev,
208 Resource *child, Device *cdev)
210 Adr_resource *cr = dynamic_cast<Adr_resource*>(child);
214 child->parent(parent);
218 Hw::Device *cd = dynamic_cast<Hw::Device*>(cdev);
225 int i = (cr->start() + (cd->adr() >> 16)) & 3;
227 Pci_iomem_root_bridge *pd = dynamic_cast<Pci_iomem_root_bridge *>(pdev);
232 cr->del_flags(Resource::F_relative);
233 cr->start(pd->int_map(i));
234 cr->del_flags(Resource::Irq_info_base * 3);
235 cr->add_flags(Resource::Irq_level | Resource::Irq_low);