l4/pkg/arm_drivers/lcd/src/lcd-omap3.h

   1 #pragma once
   2
   3 enum
   4 {
   5   Reg_dss_control       = 0x40,
   6 };
   7
   8 enum
   9 {
  10   Reg_dispc_revision                 = 0x400,
  11   Reg_dispc_sysconfig                = 0x410,
  12   Reg_dispc_sysstatus                = 0x414,
  13   Reg_dispc_irqstatus                = 0x418,
  14   Reg_dispc_irqenable                = 0x41C,
  15   Reg_dispc_control                  = 0x440,
  16   Reg_dispc_config                   = 0x444,
  17   Reg_dispc_capable                  = 0x448,
  18   Reg_dispc_default_colour0          = 0x44C,
  19   Reg_dispc_default_colour1          = 0x450,
  20   Reg_dispc_trans_colour0            = 0x454,
  21   Reg_dispc_trans_colour1            = 0x458,
  22   Reg_dispc_line_status              = 0x45C,
  23   Reg_dispc_line_number              = 0x460,
  24   Reg_dispc_timing_h                 = 0x464,
  25   Reg_dispc_timing_v                 = 0x468,
  26   Reg_dispc_pol_freq                 = 0x46C,
  27   Reg_dispc_divisor                  = 0x470,
  28   Reg_dispc_size_dig                 = 0x478,
  29   Reg_dispc_size_lcd                 = 0x47C,
  30   Reg_dispc_gfx_ba0                  = 0x480,
  31   Reg_dispc_gfx_ba1                  = 0x484,
  32   Reg_dispc_gfx_position             = 0x488,
  33   Reg_dispc_gfx_size                 = 0x48C,
  34   Reg_dispc_gfx_attributes           = 0x4A0,
  35   Reg_dispc_gfx_fifo_threshold       = 0x4A4,
  36   Reg_dispc_gfx_fifo_size_status     = 0x4A8,
  37   Reg_dispc_gfx_row_inc              = 0x4AC,
  38   Reg_dispc_gfx_pixel_inc            = 0x4B0,
  39   Reg_dispc_gfx_window_skip          = 0x4B4,
  40   Reg_dispc_gfx_table_ba             = 0x4B8,
  41 };
  42
  43 enum
  44 {
  45   Default_colour_mask           = 0x0FFFFFF,
  46   Transparency_colour_mask      = 0x0FFFFFF,
  47   X_pos_mask                    = 0x00007FF,
  48   Y_pos_mask                    = 0x00007FF,
  49   Pixel_inc_mask                = 0x000FFFF,
  50   Attributes_enable             = (1 << 0),
  51 };
  52
  53 /* DISPC_CONTROL register fields. */
  54 #define Dispc_control_gpout1                    (1 << 16)
  55 #define Dispc_control_gpout0                    (1 << 15)
  56 #define Dispc_control_rfbimode                  (1 << 11)
  57 #define Dispc_control_tftdatalines_oalsb24b     (3 <<  8)
  58 #define Dispc_control_tftdatalines_oalsb18b     (2 <<  8)
  59 #define Dispc_control_tftdatalines_oalsb16b     (1 <<  8)
  60 #define Dispc_control_godigital                 (1 <<  6)
  61 #define Dispc_control_golcd                     (1 <<  5)
  62 #define Dispc_control_stntft                    (1 <<  3)
  63 #define Dispc_control_digitalenable             (1 <<  1)
  64 #define Dispc_control_lcdenable                 (1 <<  0)
  65
  66 /* DISPC_SYSCONFIG register fields. */
  67 #define Dispc_sysconfig_midlemode_nstandby      (1 << 12)
  68 #define Dispc_sysconfig_sidlemode_nidle         (1 <<  3)
  69 #define Dispc_sysconfig_softreset               (1 <<  1)
  70
  71 /* DISPC_SYSSTATUS register field. */
  72 #define Dispc_sysstatus_resetdone               (1 << 0)
  73
  74 /* DISPC_CONFIG register fields. */
  75 #define Dispc_config_palettegammatable          (1 <<  3)
  76 #define Dispc_config_loadmode_frdatlefr         (1 <<  2)
  77 #define Dispc_config_loadmode_pgtabusetb        (1 <<  1)
  78
  79 /* DISPC_TIMING_H register fields. */
  80 #define Dispc_timing_h_hbp_shift                (20)
  81 #define Dispc_timing_h_hfp_shift                (8)
  82 #define Dispc_timing_h_hsw_shift                (0)
  83
  84 /* DISPC_TIMING_V register fields. */
  85 #define Dispc_timing_v_vbp_shift                (20)
  86 #define Dispc_timing_v_vfp_shift                (8)
  87 #define Dispc_timing_v_vsw_shift                (0)
  88
  89 /* DISPC_POL_FREQ register fields. */
  90 #define Dispc_pol_freq_ihs                      (1 << 13)
  91 #define Dispc_pol_freq_rf_shift                 (16)
  92 #define Dispc_pol_freq_onoff_shift              (17)
  93 #define Dispc_pol_freq_ipc_shift                (14)
  94 #define Dispc_pol_freq_ihs_shift                (13)
  95 #define Dispc_pol_freq_ivs_shift                (12)
  96
  97 /* DISPC_DIVISOR. */
  98 #define Dispc_divisor_lcd_shift                 (16)
  99 #define Dispc_divisor_pcd_shift                 (0)
 100
 101 /* DISPC_SIZE_LCD register fields. */
 102 #define Dispc_size_lcd_lpp                      (0x7FF << 16)
 103 #define Dispc_size_lcd_lpp_shift                (16)
 104 #define Dispc_size_lcd_ppl                      (0x7FF)
 105 #define Dispc_size_lcd_ppl_shift                (0)
 106
 107 /* DISPC_GFX_SIZE register fields. */
 108 #define Dispc_gfx_size_lpp                      (0x7FF << 16)
 109 #define Dispc_gfx_size_lpp_shift                (16)
 110 #define Dispc_gfx_size_ppl                      (0x7FF)
 111 #define Dispc_gfx_size_ppl_shift                (0)
 112
 113 /* DISPC_ATTRIBUTES register fields. */
 114 #define Dispc_attributes_gfxenable              (1 << 0)
 115 #define Dispc_gfx_attributes_replication_en     (1 << 5)
 116 #define Dispc_vid_attributes_replication_en     (1 << 10)
 117
 118 /* DISPC_GFX_FIFO_THRESHOLD register fields. */
 119 #define Dispc_gfx_fifo_threshold_high_shift     (16)
 120 #define Dispc_gfx_fifo_threshold_low_shift      (0)
 121 #define Dispc_fifo_threshold_high               (225)
 122 #define Dispc_fifo_threshold_low                (194)
 123
 124 /* DISPC_IRQSTATUS registerr fields. */
 125 #define Dispc_irqstatus_framedone               (1 <<  0)
 126
 127 /* Image Formats. */
 128 #define BITMAP1     (0x0)
 129 #define BITMAP2     (0x1)
 130 #define BITMAP4     (0x2)
 131 #define BITMAP8     (0x3)
 132 #define RGB12       (0x4)
 133 #define RGB16       (0x6)
 134 #define RGB24       (0x8)
 135 #define YUV422      (0xA)
 136 #define UYVY422     (0xB)
 137
 138
 139 #define GPIO_NUM_RESB       155
 140 #define GPIO_NUM_QVGA_nVGA  154
 141 #define GPIO_NUM_VDD        153
 142 #define GPIO_NUM_INI        152
 143 #define GPIO_NUM_LR           2
 144 #define GPIO_NUM_UD           3
 145
 146
 147 #define CONV_SCAN_DIRECTION     1
 148 #define INVR_SCAN_DIRECTION     0
 149
 150 #define T2_I2C_LED_ADDR_GROUP   0x4a
 151 #define T2_I2C_XXX_ADDR_GROUP   0x4b
 152
 153 /* Triton2 power module  registers */
 154 #define TRITON2_LED_LEDEN_REG       0xee
 155 #define TRITON2_LED_PWMAON_REG      0xef
 156 #define TRITON2_LED_PWMAOFF_REG     0xf0
 157 #define TRITON2_LED_PWMBON_REG      0xf1
 158 #define TRITON2_LED_PWMBOFF_REG     0xf2
 159 #define TRITON2_VDAC_DEDICATED      0x91
 160 #define TRITON2_VDAC_DEV_GRP        0x8e