1 INTERFACE [arm && omap3]:
12 Multi_irq_pending = 0,
14 No_irq_pending = 1023,
19 INTCPS_SYSCONFIG = Kmem::Intc_map_base + 0x010,
20 INTCPS_SYSSTATUS = Kmem::Intc_map_base + 0x014,
21 INTCPS_CONTROL = Kmem::Intc_map_base + 0x048,
22 INTCPS_TRESHOLD = Kmem::Intc_map_base + 0x068,
23 INTCPS_ITRn_base = Kmem::Intc_map_base + 0x080,
24 INTCPS_MIRn_base = Kmem::Intc_map_base + 0x084,
25 INTCPS_MIR_CLEARn_base = Kmem::Intc_map_base + 0x088,
26 INTCPS_MIR_SETn_base = Kmem::Intc_map_base + 0x08c,
27 INTCPS_ISR_SETn_base = Kmem::Intc_map_base + 0x090,
28 INTCPS_ISR_CLEARn_base = Kmem::Intc_map_base + 0x094,
29 INTCPS_PENDING_IRQn_base = Kmem::Intc_map_base + 0x098,
30 INTCPS_ILRm_base = Kmem::Intc_map_base + 0x100,
35 //-------------------------------------------------------------------
36 IMPLEMENTATION [arm && omap3]:
41 #include "boot_info.h"
43 #include "initcalls.h"
46 #include "irq_chip_generic.h"
51 class Omap3_pin : public Irq_pin
54 explicit Omap3_pin(unsigned irq) { payload()[0] = irq; }
55 unsigned irq() const { return payload()[0]; }
60 Omap3_pin::unbind_irq()
64 Irq_chip::hw_chip->free(Irq::self(this), irq());
65 replace<Sw_irq_pin>();
72 assert (cpu_lock.test());
73 Io::write<Mword>(1 << (irq() & 31), Pic::INTCPS_MIR_SETn_base + (irq() & 0xe0));
78 Omap3_pin::do_mask_and_ack()
80 assert (cpu_lock.test());
82 Io::write<Mword>(1 << (irq() & 31), Pic::INTCPS_MIR_SETn_base + (irq() & 0xe0));
83 Io::write<Mword>(1, Pic::INTCPS_CONTROL);
90 Io::write<Mword>(1, Pic::INTCPS_CONTROL);
97 Irq::self(this)->Irq::hit();
102 Omap3_pin::do_unmask()
104 assert (cpu_lock.test());
105 Io::write<Mword>(1 << (irq() & 31), Pic::INTCPS_MIR_CLEARn_base + (irq() & 0xe0));
111 Omap3_pin::check_debug_irq()
113 return !Vkey::check_(irq());
118 Omap3_pin::set_cpu(unsigned)
125 class Irq_chip_arm_x : public Irq_chip_gen
131 Irq_chip_arm_x::setup(Irq_base *irq, unsigned irqnum)
133 if (irqnum < Config::Max_num_dirqs)
134 irq->pin()->replace<Omap3_pin>(irqnum);
138 IMPLEMENT FIASCO_INIT
141 static Irq_chip_arm_x _ia;
142 Irq_chip::hw_chip = &_ia;
145 Io::write<Mword>(2, INTCPS_SYSCONFIG);
146 while (!Io::read<Mword>(INTCPS_SYSSTATUS))
150 Io::write<Mword>(1, INTCPS_SYSCONFIG);
153 Io::write<Mword>(0xff, INTCPS_TRESHOLD);
155 // set priority for each interrupt line, lets take 0x20
156 // setting bit0 to 0 means IRQ (1 would mean FIQ)
157 for (int m = 0; m < Config::Max_num_dirqs; ++m)
158 Io::write<Mword>(0x20 << 2, INTCPS_ILRm_base + (4 * m));
160 // mask all interrupts
161 for (int n = 0; n < 3; ++n)
162 Io::write<Mword>(0xffffffff, INTCPS_MIR_SETn_base + 0x20 * n);
166 Pic::Status Pic::disable_all_save()
170 void Pic::restore_all( Status /*s*/ )
173 PUBLIC static inline NEEDS["io.h",<cstdio>]
174 Unsigned32 Pic::pending()
176 for (int n = 0; n < (Config::Max_num_dirqs >> 5); ++n)
178 unsigned long x = Io::read<Mword>(INTCPS_PENDING_IRQn_base + 0x20 * n);
179 for (int i = 0; i < 32; ++i)
189 Mword Pic::is_pending(Mword &irqs, Mword irq)
190 { return irqs == irq; }
192 //---------------------------------------------------------------------------
193 IMPLEMENTATION [debug && omap3]:
197 Omap3_pin::pin_type() const
198 { return "HW OMAP3 IRQ"; }