1 INTERFACE [arm && omap3]: //--------------------------------------------
3 EXTENSION class Mem_layout
6 enum Virt_layout_omap3 {
7 Devices1_map_base = Registers_map_start,
8 L4_addr_prot_map_base = Devices1_map_base + 0x00040000,
9 Uart1_map_base = Devices1_map_base + 0x0006a000,
10 Gptimer10_map_base = Devices1_map_base + 0x00086000,
11 Wkup_cm_map_base = Devices1_map_base + 0x00004c00,
13 Devices2_map_base = Registers_map_start + 0x00100000,
14 Intc_map_base = Devices2_map_base + 0x0,
16 Devices3_map_base = Registers_map_start + 0x00200000,
17 Gptimer1_map_base = Devices3_map_base + 0x00018000,
18 Prm_global_reg_map_base = Devices3_map_base + 0x00007200,
20 Devices4_map_base = Registers_map_start + 0x00300000,
21 Uart3_map_base = Devices4_map_base + 0x00020000,
23 Timer_base = Gptimer1_map_base,
26 enum Phys_layout_omap3 {
27 Devices1_phys_base = 0x48000000,
28 L4_addr_prot_phys_base = Devices1_phys_base + 0x00040000,
29 Uart1_phys_base = Devices1_phys_base + 0x0006a000,
30 Gptimer10_phys_base = Devices1_phys_base + 0x00086000,
31 Wkup_cm_phys_base = Devices1_phys_base + 0x00004c00,
33 Devices2_phys_base = 0x48200000,
34 Intc_phys_base = Devices2_phys_base + 0x0,
36 Devices3_phys_base = 0x48300000,
37 Gptimer1_phys_base = Devices3_phys_base + 0x00018000,
38 Prm_global_reg_phys_base = Devices3_phys_base + 0x00007200,
40 Devices4_phys_base = 0x49000000,
41 Uart3_phys_base = Devices4_phys_base + 0x00020000,
43 Sdram_phys_base = 0x80000000,
45 Flush_area_phys_base = 0xe0000000,
49 INTERFACE [arm && omap3_evm]: //-------------------------------------------
51 EXTENSION class Mem_layout
54 enum Virt_layout_omap3_evm {
55 Uart_base = Uart1_map_base,
59 INTERFACE [arm && omap3_beagleboard]: //-----------------------------------
61 EXTENSION class Mem_layout
64 enum Virt_layout_omap3_beagleboard {
65 Uart_base = Uart3_map_base,