1 // AsmJit - Complete JIT Assembler for C++ Language.
3 // Copyright (c) 2008-2010, Petr Kobalicek <kobalicek.petr@gmail.com>
5 // Permission is hereby granted, free of charge, to any person
6 // obtaining a copy of this software and associated documentation
7 // files (the "Software"), to deal in the Software without
8 // restriction, including without limitation the rights to use,
9 // copy, modify, merge, publish, distribute, sublicense, and/or sell
10 // copies of the Software, and to permit persons to whom the
11 // Software is furnished to do so, subject to the following
14 // The above copyright notice and this permission notice shall be
15 // included in all copies or substantial portions of the Software.
17 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 // EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
19 // OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20 // NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
21 // HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
22 // WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
23 // FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
24 // OTHER DEALINGS IN THE SOFTWARE.
27 #ifndef _ASMJIT_DEFSX86X64_H
28 #define _ASMJIT_DEFSX86X64_H
30 #if !defined(_ASMJIT_DEFS_H)
31 #warning "AsmJit/DefsX86X64.h can be only included by AsmJit/Defs.h"
32 #endif // _ASMJIT_DEFS_H
46 //! @addtogroup AsmJit_Core
49 // ============================================================================
51 // ============================================================================
54 //! @brief Count of General purpose registers and XMM registers.
56 //! Count of general purpose registers and XMM registers depends to current
57 //! bit-mode. If application is compiled for 32-bit platform then this number
58 //! is 8, 64-bit platforms have 8 extra general purpose and xmm registers (16
61 //! @brief Count of registers.
66 //! Count of general purpose registers and XMM registers depends to current
67 //! bit-mode. If application is compiled for 32-bit platform then this number
68 //! is 8, 64-bit platforms have 8 extra general purpose and xmm registers (16
70 #if defined(ASMJIT_X86)
76 //! @brief Count of general purpose registers.
78 //! 8 in 32-bit mode and 16 in 64-bit mode.
79 REG_NUM_GP = REG_NUM_BASE,
81 //! @brief Count of MM registers (always 8).
84 //! @brief Count of FPU stack registers (always 8).
87 //! @brief Count of XMM registers.
89 //! 8 in 32-bit mode and 16 in 64-bit mode.
90 REG_NUM_XMM = REG_NUM_BASE
93 // ============================================================================
94 // [AsmJit::REG_INDEX]
95 // ============================================================================
97 //! @brief Valid X86 register indexes.
99 //! These codes are real, don't miss with @c REG enum! and don't use these
100 //! values if you are not writing AsmJit code.
103 //! @brief Mask for register code (index).
104 REG_INDEX_MASK = 0x00FF,
106 //! @brief ID for AX/EAX/RAX registers.
108 //! @brief ID for CX/ECX/RCX registers.
110 //! @brief ID for DX/EDX/RDX registers.
112 //! @brief ID for BX/EBX/RBX registers.
114 //! @brief ID for SP/ESP/RSP registers.
116 //! @brief ID for BP/EBP/RBP registers.
118 //! @brief ID for SI/ESI/RSI registers.
120 //! @brief ID for DI/EDI/RDI registers.
123 #if defined(ASMJIT_X64)
124 //! @brief ID for AX/EAX/RAX registers.
126 //! @brief ID for CX/ECX/RCX registers.
128 //! @brief ID for DX/EDX/RDX registers.
130 //! @brief ID for BX/EBX/RBX registers.
132 //! @brief ID for SP/ESP/RSP registers.
134 //! @brief ID for BP/EBP/RBP registers.
136 //! @brief ID for SI/ESI/RSI registers.
138 //! @brief ID for DI/EDI/RDI registers.
141 //! @brief ID for r8 register (additional register introduced by 64-bit architecture).
143 //! @brief ID for R9 register (additional register introduced by 64-bit architecture).
145 //! @brief ID for R10 register (additional register introduced by 64-bit architecture).
147 //! @brief ID for R11 register (additional register introduced by 64-bit architecture).
149 //! @brief ID for R12 register (additional register introduced by 64-bit architecture).
151 //! @brief ID for R13 register (additional register introduced by 64-bit architecture).
153 //! @brief ID for R14 register (additional register introduced by 64-bit architecture).
155 //! @brief ID for R15 register (additional register introduced by 64-bit architecture).
159 //! @brief ID for mm0 register.
161 //! @brief ID for mm1 register.
163 //! @brief ID for mm2 register.
165 //! @brief ID for mm3 register.
167 //! @brief ID for mm4 register.
169 //! @brief ID for mm5 register.
171 //! @brief ID for mm6 register.
173 //! @brief ID for mm7 register.
176 //! @brief ID for xmm0 register.
178 //! @brief ID for xmm1 register.
180 //! @brief ID for xmm2 register.
182 //! @brief ID for xmm3 register.
184 //! @brief ID for xmm4 register.
186 //! @brief ID for xmm5 register.
188 //! @brief ID for xmm6 register.
190 //! @brief ID for xmm7 register.
193 #if defined(ASMJIT_X64)
196 //! @brief ID for xmm8 register (additional register introduced by 64-bit architecture).
198 //! @brief ID for xmm9 register (additional register introduced by 64-bit architecture).
200 //! @brief ID for xmm10 register (additional register introduced by 64-bit architecture).
201 REG_INDEX_XMM10 = 10,
202 //! @brief ID for xmm11 register (additional register introduced by 64-bit architecture).
203 REG_INDEX_XMM11 = 11,
204 //! @brief ID for xmm12 register (additional register introduced by 64-bit architecture).
205 REG_INDEX_XMM12 = 12,
206 //! @brief ID for xmm13 register (additional register introduced by 64-bit architecture).
207 REG_INDEX_XMM13 = 13,
208 //! @brief ID for xmm14 register (additional register introduced by 64-bit architecture).
209 REG_INDEX_XMM14 = 14,
210 //! @brief ID for xmm15 register (additional register introduced by 64-bit architecture).
215 // ============================================================================
216 // [AsmJit::REG_TYPE]
217 // ============================================================================
219 //! @brief Pseudo (not real X86) register types.
222 //! @brief Mask for register type.
223 REG_TYPE_MASK = 0xFF00,
225 // First byte contains register type (mask 0xFF00), Second byte contains
226 // register index code.
228 // --------------------------------------------------------------------------
229 // [GP Register Types]
230 // --------------------------------------------------------------------------
232 //! @brief 8-bit general purpose register type (LO).
233 REG_TYPE_GPB_LO = 0x0100,
234 //! @brief 8-bit general purpose register type (HI, only AH, BH, CH, DH).
235 REG_TYPE_GPB_HI = 0x0200,
236 //! @brief 16-bit general purpose register type.
237 REG_TYPE_GPW = 0x1000,
238 //! @brief 32-bit general purpose register type.
239 REG_TYPE_GPD = 0x2000,
240 //! @brief 64-bit general purpose register type.
241 REG_TYPE_GPQ = 0x3000,
244 //! @brief 32-bit or 64-bit general purpose register type.
246 // native 32-bit or 64-bit register type (depends to x86 or x64 mode).
247 #if defined(ASMJIT_X86)
248 REG_TYPE_GPN = REG_TYPE_GPD,
250 REG_TYPE_GPN = REG_TYPE_GPQ,
253 // --------------------------------------------------------------------------
254 // [X87 (FPU) Register Type]
255 // --------------------------------------------------------------------------
257 //! @brief X87 (FPU) register type.
258 REG_TYPE_X87 = 0x5000,
260 // --------------------------------------------------------------------------
261 // [MM Register Type]
262 // --------------------------------------------------------------------------
264 //! @brief 64-bit MM register type.
265 REG_TYPE_MM = 0x6000,
267 // --------------------------------------------------------------------------
268 // [XMM Register Type]
269 // --------------------------------------------------------------------------
271 //! @brief 128-bit XMM register type.
272 REG_TYPE_XMM = 0x7000
275 // ============================================================================
276 // [AsmJit::REG_CODE]
277 // ============================================================================
279 //! @brief Pseudo (not real X86) register codes used for generating opcodes.
281 //! From this register code can be generated real x86 register ID, type of
282 //! register and size of register.
285 // --------------------------------------------------------------------------
287 // --------------------------------------------------------------------------
289 REG_AL = REG_TYPE_GPB_LO,
293 #if defined(ASMJIT_X64)
300 #if defined(ASMJIT_X64)
311 REG_AH = REG_TYPE_GPB_HI,
316 // --------------------------------------------------------------------------
317 // [16-bit Registers]
318 // --------------------------------------------------------------------------
320 REG_AX = REG_TYPE_GPW,
328 #if defined(ASMJIT_X64)
339 // --------------------------------------------------------------------------
340 // [32-bit Registers]
341 // --------------------------------------------------------------------------
343 REG_EAX = REG_TYPE_GPD,
351 #if defined(ASMJIT_X64)
362 // --------------------------------------------------------------------------
363 // [64-bit Registers]
364 // --------------------------------------------------------------------------
366 #if defined(ASMJIT_X64)
367 REG_RAX = REG_TYPE_GPQ,
385 // --------------------------------------------------------------------------
387 // --------------------------------------------------------------------------
389 REG_MM0 = REG_TYPE_MM,
398 // --------------------------------------------------------------------------
400 // --------------------------------------------------------------------------
402 REG_XMM0 = REG_TYPE_XMM,
410 #if defined(ASMJIT_X64)
421 // --------------------------------------------------------------------------
422 // [Native registers (depends if processor runs in 32-bit or 64-bit mode)]
423 // --------------------------------------------------------------------------
425 REG_NAX = REG_TYPE_GPN,
435 // ============================================================================
436 // [AsmJit::SEGMENT_PREFIX]
437 // ============================================================================
439 //! @brief Segment override prefixes.
442 // DO NOT MODIFY INDEX CODES - They are used by logger in this order.
444 //! @brief No segment override prefix.
446 //! @brief Use 'cs' segment override prefix.
448 //! @brief Use 'ss' segment override prefix.
450 //! @brief Use 'ds' segment override prefix.
452 //! @brief Use 'es' segment override prefix.
454 //! @brief Use 'fs' segment override prefix.
456 //! @brief Use 'gs' segment override prefix.
458 //! @brief End of prefix codes
462 // ============================================================================
463 // [AsmJit::PREFETCH_HINT]
464 // ============================================================================
466 //! @brief Prefetch hints.
469 //! @brief Prefetch to L0 cache.
471 //! @brief Prefetch to L1 cache.
473 //! @brief Prefetch to L2 cache.
475 //! @brief Prefetch using NT hint.
479 // ============================================================================
480 // [AsmJit::CONDITION]
481 // ============================================================================
483 //! @brief Condition codes.
486 //! @brief No condition code.
489 // Condition codes from processor manuals.
521 // Simplified condition codes
535 C_GREATER_EQUAL = 0xD,
545 // x87 floating point only
547 C_FP_NOT_UNORDERED = 17
550 //! @brief Returns the equivalent of !cc.
552 //! Negation of the default no_condition (-1) results in a non-default
553 //! no_condition value (-2). As long as tests for no_condition check
554 //! for condition < 0, this will work as expected.
555 static inline CONDITION negateCondition(CONDITION cc)
557 return static_cast<CONDITION>(cc ^ 1);
560 //! @brief Corresponds to transposing the operands of a comparison.
561 static inline CONDITION reverseCondition(CONDITION cc)
569 return C_BELOW_EQUAL;
571 return C_ABOVE_EQUAL;
576 case C_GREATER_EQUAL:
579 return C_GREATER_EQUAL;
585 struct ASMJIT_API ConditionToInstruction
587 //! @brief Used to map condition code to jcc instructions.
588 static const uint32_t _jcctable[16];
589 //! @brief Used to map condition code to cmovcc instructions.
590 static const uint32_t _cmovcctable[16];
591 //! @brief Used to map condition code to setcc instructions.
592 static const uint32_t _setcctable[16];
594 //! @brief Translate condition code @a cc to jcc instruction code.
595 //! @sa @c INST_CODE, @c INST_J.
596 static inline uint32_t toJCC(CONDITION cc) ASMJIT_NOTHROW
598 ASMJIT_ASSERT(static_cast<uint32_t>(cc) <= 0xF);
599 return _jcctable[cc];
602 //! @brief Translate condition code @a cc to cmovcc instruction code.
603 //! @sa @c INST_CODE, @c INST_CMOV.
604 static inline uint32_t toCMovCC(CONDITION cc) ASMJIT_NOTHROW
606 ASMJIT_ASSERT(static_cast<uint32_t>(cc) <= 0xF);
607 return _cmovcctable[cc];
610 //! @brief Translate condition code @a cc to setcc instruction code.
611 //! @sa @c INST_CODE, @c INST_SET.
612 static inline uint32_t toSetCC(CONDITION cc) ASMJIT_NOTHROW
614 ASMJIT_ASSERT(static_cast<uint32_t>(cc) <= 0xF);
615 return _setcctable[cc];
619 // ============================================================================
621 // ============================================================================
623 //! @brief Scale, can be used for addressing.
625 //! See @c Op and addressing methods like @c byte_ptr(), @c word_ptr(),
626 //! @c dword_ptr(), etc...
629 //! @brief Scale 1 times (no scale).
631 //! @brief Scale 2 times (same as shifting to left by 1).
633 //! @brief Scale 4 times (same as shifting to left by 2).
635 //! @brief Scale 8 times (same as shifting to left by 3).
639 // ============================================================================
641 // ============================================================================
643 //! @brief Condition hint, see @c AsmJit::Assembler::jz(), @c AsmJit::Compiler::jz()
649 //! @brief Condition will be taken (likely).
651 //! @brief Condition will be not taken (unlikely).
652 HINT_NOT_TAKEN = 0x02
655 //! @brief Hint byte value is the byte that will be emitted if hint flag
656 //! is specified by @c HINT.
659 //! @brief Condition will be taken (likely).
660 HINT_BYTE_VALUE_TAKEN = 0x3E,
661 //! @brief Condition will be not taken (unlikely).
662 HINT_BYTE_VALUE_NOT_TAKEN = 0x2E
665 // ============================================================================
666 // [AsmJit::FP_STATUS]
667 // ============================================================================
669 //! @brief Floating point status.
679 // ============================================================================
681 // ============================================================================
683 //! @brief Floating point control word.
686 FP_CW_INVOPEX_MASK = 0x001,
687 FP_CW_DENOPEX_MASK = 0x002,
688 FP_CW_ZERODIV_MASK = 0x004,
689 FP_CW_OVFEX_MASK = 0x008,
690 FP_CW_UNDFEX_MASK = 0x010,
691 FP_CW_PRECEX_MASK = 0x020,
692 FP_CW_PRECC_MASK = 0x300,
693 FP_CW_ROUNDC_MASK = 0xC00,
695 // Values for precision control.
696 FP_CW_PREC_SINGLE = 0x000,
697 FP_CW_PREC_DOUBLE = 0x200,
698 FP_CW_PREC_EXTENDED = 0x300,
700 // Values for rounding control.
701 FP_CW_ROUND_NEAREST = 0x000,
702 FP_CW_ROUND_DOWN = 0x400,
703 FP_CW_ROUND_UP = 0x800,
704 FP_CW_ROUND_TOZERO = 0xC00
707 // ============================================================================
708 // [AsmJit::INST_CODE]
709 // ============================================================================
711 //! @brief Instruction codes.
713 //! Note that these instruction codes are AsmJit specific. Each instruction is
714 //! unique ID into AsmJit instruction table. Instruction codes are used together
715 //! with AsmJit::Assembler and you can also use instruction codes to serialize
716 //! instructions by @ref AssemblerCore::_emitInstruction() or
717 //! @ref CompilerCore::_emitInstruction()
741 INST_BSWAP, // X86/X64 (i486)
746 INST_CALL, // X86/X64
748 INST_CDQE, // X64 only
754 INST_CMOV, // Begin (cmovcc) (i586)
755 INST_CMOVA = INST_CMOV, //X86/X64 (cmovcc) (i586)
756 INST_CMOVAE, // X86/X64 (cmovcc) (i586)
757 INST_CMOVB, // X86/X64 (cmovcc) (i586)
758 INST_CMOVBE, // X86/X64 (cmovcc) (i586)
759 INST_CMOVC, // X86/X64 (cmovcc) (i586)
760 INST_CMOVE, // X86/X64 (cmovcc) (i586)
761 INST_CMOVG, // X86/X64 (cmovcc) (i586)
762 INST_CMOVGE, // X86/X64 (cmovcc) (i586)
763 INST_CMOVL, // X86/X64 (cmovcc) (i586)
764 INST_CMOVLE, // X86/X64 (cmovcc) (i586)
765 INST_CMOVNA, // X86/X64 (cmovcc) (i586)
766 INST_CMOVNAE, // X86/X64 (cmovcc) (i586)
767 INST_CMOVNB, // X86/X64 (cmovcc) (i586)
768 INST_CMOVNBE, // X86/X64 (cmovcc) (i586)
769 INST_CMOVNC, // X86/X64 (cmovcc) (i586)
770 INST_CMOVNE, // X86/X64 (cmovcc) (i586)
771 INST_CMOVNG, // X86/X64 (cmovcc) (i586)
772 INST_CMOVNGE, // X86/X64 (cmovcc) (i586)
773 INST_CMOVNL, // X86/X64 (cmovcc) (i586)
774 INST_CMOVNLE, // X86/X64 (cmovcc) (i586)
775 INST_CMOVNO, // X86/X64 (cmovcc) (i586)
776 INST_CMOVNP, // X86/X64 (cmovcc) (i586)
777 INST_CMOVNS, // X86/X64 (cmovcc) (i586)
778 INST_CMOVNZ, // X86/X64 (cmovcc) (i586)
779 INST_CMOVO, // X86/X64 (cmovcc) (i586)
780 INST_CMOVP, // X86/X64 (cmovcc) (i586)
781 INST_CMOVPE, // X86/X64 (cmovcc) (i586)
782 INST_CMOVPO, // X86/X64 (cmovcc) (i586)
783 INST_CMOVS, // X86/X64 (cmovcc) (i586)
784 INST_CMOVZ, // X86/X64 (cmovcc) (i586)
791 INST_CMPXCHG, // X86/X64 (i486)
792 INST_CMPXCHG16B, // X64 only
793 INST_CMPXCHG8B, // X86/X64 (i586)
796 INST_CPUID, // X86/X64 (i486)
820 INST_CWDE, // X86/X64
821 INST_DAA, // X86 only
822 INST_DAS, // X86 only
832 INST_ENTER, // X86/X64
846 INST_FCMOVNBE, // X87
861 INST_FEMMS, // 3dNow!
934 INST_IDIV, // X86/X64
935 INST_IMUL, // X86/X64
937 INST_INT3, // X86/X64
938 INST_J, // Begin (jcc)
940 INST_J, // X86/X64 (jcc)
941 INST_JAE, // X86/X64 (jcc)
942 INST_JB, // X86/X64 (jcc)
943 INST_JBE, // X86/X64 (jcc)
944 INST_JC, // X86/X64 (jcc)
945 INST_JE, // X86/X64 (jcc)
946 INST_JG, // X86/X64 (jcc)
947 INST_JGE, // X86/X64 (jcc)
948 INST_JL, // X86/X64 (jcc)
949 INST_JLE, // X86/X64 (jcc)
950 INST_JNA, // X86/X64 (jcc)
951 INST_JNAE, // X86/X64 (jcc)
952 INST_JNB, // X86/X64 (jcc)
953 INST_JNBE, // X86/X64 (jcc)
954 INST_JNC, // X86/X64 (jcc)
955 INST_JNE, // X86/X64 (jcc)
956 INST_JNG, // X86/X64 (jcc)
957 INST_JNGE, // X86/X64 (jcc)
958 INST_JNL, // X86/X64 (jcc)
959 INST_JNLE, // X86/X64 (jcc)
960 INST_JNO, // X86/X64 (jcc)
961 INST_JNP, // X86/X64 (jcc)
962 INST_JNS, // X86/X64 (jcc)
963 INST_JNZ, // X86/X64 (jcc)
964 INST_JO, // X86/X64 (jcc)
965 INST_JP, // X86/X64 (jcc)
966 INST_JPE, // X86/X64 (jcc)
967 INST_JPO, // X86/X64 (jcc)
968 INST_JS, // X86/X64 (jcc)
969 INST_JZ, // X86/X64 (jcc)
970 INST_JMP, // X86/X64 (jmp)
973 INST_LAHF, // X86/X64 (CPUID NEEDED)
975 INST_LEAVE, // X86/X64
978 INST_MASKMOVQ, // MMX Extensions
1011 INST_MOVNTQ, // MMX Extensions
1018 INST_MOVSX, // X86/X64
1019 INST_MOVSXD, // X86/X64
1022 INST_MOVZX, // X86/X64
1023 INST_MOV_PTR, // X86/X64
1025 INST_MUL, // X86/X64
1031 INST_NEG, // X86/X64
1032 INST_NOP, // X86/X64
1033 INST_NOT, // X86/X64
1056 INST_PAVGB, // MMX Extensions
1057 INST_PAVGW, // MMX Extensions
1075 INST_PEXTRW, // MMX Extensions
1076 INST_PF2ID, // 3dNow!
1077 INST_PF2IW, // 3dNow! Extensions
1078 INST_PFACC, // 3dNow!
1079 INST_PFADD, // 3dNow!
1080 INST_PFCMPEQ, // 3dNow!
1081 INST_PFCMPGE, // 3dNow!
1082 INST_PFCMPGT, // 3dNow!
1083 INST_PFMAX, // 3dNow!
1084 INST_PFMIN, // 3dNow!
1085 INST_PFMUL, // 3dNow!
1086 INST_PFNACC, // 3dNow! Extensions
1087 INST_PFPNACC, // 3dNow! Extensions
1088 INST_PFRCP, // 3dNow!
1089 INST_PFRCPIT1, // 3dNow!
1090 INST_PFRCPIT2, // 3dNow!
1091 INST_PFRSQIT1, // 3dNow!
1092 INST_PFRSQRT, // 3dNow!
1093 INST_PFSUB, // 3dNow!
1094 INST_PFSUBR, // 3dNow!
1102 INST_PI2FD, // 3dNow!
1103 INST_PI2FW, // 3dNow! Extensions
1107 INST_PINSRW, // MMX Extensions
1112 INST_PMAXSW, // MMX Extensions
1113 INST_PMAXUB, // MMX Extensions
1118 INST_PMINSW, // MMX Extensions
1119 INST_PMINUB, // MMX Extensions
1122 INST_PMOVMSKB, // MMX Extensions
1137 INST_PMULHUW, // MMX Extensions
1142 INST_POP, // X86/X64
1143 INST_POPAD, // X86 only
1145 INST_POPFD, // X86 only
1146 INST_POPFQ, // X64 only
1148 INST_PREFETCH, // MMX Extensions
1149 INST_PSADBW, // MMX Extensions
1152 INST_PSHUFW, // MMX Extensions
1176 INST_PSWAPD, // 3dNow! Extensions
1186 INST_PUSH, // X86/X64
1187 INST_PUSHAD, // X86 only
1188 INST_PUSHFD, // X86 only
1189 INST_PUSHFQ, // X64 only
1191 INST_RCL, // X86/X64
1194 INST_RCR, // X86/X64
1195 INST_RDTSC, // X86/X64
1196 INST_RDTSCP, // X86/X64
1197 INST_REP_LODSB, // X86/X64 (REP)
1198 INST_REP_LODSD, // X86/X64 (REP)
1199 INST_REP_LODSQ, // X64 only (REP)
1200 INST_REP_LODSW, // X86/X64 (REP)
1201 INST_REP_MOVSB, // X86/X64 (REP)
1202 INST_REP_MOVSD, // X86/X64 (REP)
1203 INST_REP_MOVSQ, // X64 only (REP)
1204 INST_REP_MOVSW, // X86/X64 (REP)
1205 INST_REP_STOSB, // X86/X64 (REP)
1206 INST_REP_STOSD, // X86/X64 (REP)
1207 INST_REP_STOSQ, // X64 only (REP)
1208 INST_REP_STOSW, // X86/X64 (REP)
1209 INST_REPE_CMPSB, // X86/X64 (REP)
1210 INST_REPE_CMPSD, // X86/X64 (REP)
1211 INST_REPE_CMPSQ, // X64 only (REP)
1212 INST_REPE_CMPSW, // X86/X64 (REP)
1213 INST_REPE_SCASB, // X86/X64 (REP)
1214 INST_REPE_SCASD, // X86/X64 (REP)
1215 INST_REPE_SCASQ, // X64 only (REP)
1216 INST_REPE_SCASW, // X86/X64 (REP)
1217 INST_REPNE_CMPSB, // X86/X64 (REP)
1218 INST_REPNE_CMPSD, // X86/X64 (REP)
1219 INST_REPNE_CMPSQ, // X64 only (REP)
1220 INST_REPNE_CMPSW, // X86/X64 (REP)
1221 INST_REPNE_SCASB, // X86/X64 (REP)
1222 INST_REPNE_SCASD, // X86/X64 (REP)
1223 INST_REPNE_SCASQ, // X64 only (REP)
1224 INST_REPNE_SCASW, // X86/X64 (REP)
1225 INST_RET, // X86/X64
1226 INST_ROL, // X86/X64
1227 INST_ROR, // X86/X64
1234 INST_SAHF, // X86/X64 (CPUID NEEDED)
1235 INST_SAL, // X86/X64
1236 INST_SAR, // X86/X64
1237 INST_SBB, // X86/X64
1238 INST_SET, // Begin (setcc)
1239 INST_SETA=INST_SET, // X86/X64 (setcc)
1240 INST_SETAE, // X86/X64 (setcc)
1241 INST_SETB, // X86/X64 (setcc)
1242 INST_SETBE, // X86/X64 (setcc)
1243 INST_SETC, // X86/X64 (setcc)
1244 INST_SETE, // X86/X64 (setcc)
1245 INST_SETG, // X86/X64 (setcc)
1246 INST_SETGE, // X86/X64 (setcc)
1247 INST_SETL, // X86/X64 (setcc)
1248 INST_SETLE, // X86/X64 (setcc)
1249 INST_SETNA, // X86/X64 (setcc)
1250 INST_SETNAE, // X86/X64 (setcc)
1251 INST_SETNB, // X86/X64 (setcc)
1252 INST_SETNBE, // X86/X64 (setcc)
1253 INST_SETNC, // X86/X64 (setcc)
1254 INST_SETNE, // X86/X64 (setcc)
1255 INST_SETNG, // X86/X64 (setcc)
1256 INST_SETNGE, // X86/X64 (setcc)
1257 INST_SETNL, // X86/X64 (setcc)
1258 INST_SETNLE, // X86/X64 (setcc)
1259 INST_SETNO, // X86/X64 (setcc)
1260 INST_SETNP, // X86/X64 (setcc)
1261 INST_SETNS, // X86/X64 (setcc)
1262 INST_SETNZ, // X86/X64 (setcc)
1263 INST_SETO, // X86/X64 (setcc)
1264 INST_SETP, // X86/X64 (setcc)
1265 INST_SETPE, // X86/X64 (setcc)
1266 INST_SETPO, // X86/X64 (setcc)
1267 INST_SETS, // X86/X64 (setcc)
1268 INST_SETZ, // X86/X64 (setcc)
1269 INST_SFENCE, // MMX Extensions
1270 INST_SHL, // X86/X64
1271 INST_SHLD, // X86/X64
1272 INST_SHR, // X86/X64
1273 INST_SHRD, // X86/X64
1280 INST_STC, // X86/X64
1281 INST_STD, // X86/X64
1283 INST_SUB, // X86/X64
1288 INST_TEST, // X86/X64
1291 INST_UD2, // X86/X64
1296 INST_XADD, // X86/X64 (i486)
1297 INST_XCHG, // X86/X64 (i386)
1298 INST_XOR, // X86/X64
1304 _INST_J_BEGIN = INST_J,
1305 _INST_J_END = INST_JMP
1308 // ============================================================================
1309 // [AsmJit::Instruction Name]
1310 // ============================================================================
1314 //! @brief Instruction names.
1315 ASMJIT_API extern const char instructionName[];
1317 // ============================================================================
1318 // [AsmJit::Instruction Description]
1319 // ============================================================================
1321 struct InstructionDescription
1323 // --------------------------------------------------------------------------
1324 // [Instruction Groups]
1325 // --------------------------------------------------------------------------
1327 //! @brief Instruction groups.
1329 //! This should be only used by assembler, because it's @c AsmJit::Assembler
1330 //! specific grouping. Each group represents one 'case' in the Assembler's
1331 //! main emit method.
1334 // Gloup categories.
1353 G_PUSH, // I_PUSH is implemented before I_POP
1366 // Group for x87 FP instructions in format mem or st(i), st(i) (fadd, fsub, fdiv, ...)
1368 // Group for x87 FP instructions in format st(i), st(i)
1370 // Group for fld/fst/fstp instruction, internally uses I_X87_MEM group.
1372 // Group for x87 FP instructions that uses Word, DWord, QWord or TWord memory pointer.
1374 // Group for x87 FSTSW/FNSTSW instructions
1377 // Group for movbe instruction
1380 // Group for MMX/SSE instructions in format (X)MM|Reg|Mem <- (X)MM|Reg|Mem,
1381 // 0x66 prefix must be set manually in opcodes.
1382 // - Primary opcode is used for instructions in (X)MM <- (X)MM/Mem format,
1383 // - Secondary opcode is used for instructions in (X)MM/Mem <- (X)MM format.
1386 // Group for movd and movq instructions.
1390 // Group for pextrd, pextrq and pextrw instructions (it's special instruction
1391 // not similar to others)
1394 // Group for prefetch instruction
1397 // Group for MMX/SSE instructions in format (X)MM|Reg <- (X)MM|Reg|Mem|Imm,
1398 // 0x66 prefix is added for MMX instructions that used by SSE2 registers.
1399 // - Primary opcode is used for instructions in (X)MM|Reg <- (X)MM|Reg|Mem format,
1400 // - Secondary opcode is iused for instructions in (X)MM|Reg <- Imm format.
1404 // Group for 3dNow instructions
1408 // --------------------------------------------------------------------------
1409 // [Instruction Core Flags]
1410 // --------------------------------------------------------------------------
1412 //! @brief Instruction core flags.
1415 //! @brief No flags.
1417 //! @brief Instruction is jump, conditional jump, call or ret.
1419 //! @brief Instruction will overwrite first operand - o[0].
1421 //! @brief Instruction is X87 FPU.
1423 //! @brief Instruction can be prepended using LOCK prefix
1424 //! (usable for multithreaded applications).
1427 //! @brief Instruction is special, this is for @c Compiler.
1429 //! @brief Instruction always performs memory access.
1431 //! This flag is always combined with @c F_SPECIAL and signalizes that
1432 //! there is implicit address which is accessed (usually EDI/RDI or ESI/EDI).
1433 F_SPECIAL_MEM = 0x20
1436 // --------------------------------------------------------------------------
1437 // [Instruction Operand Flags]
1438 // --------------------------------------------------------------------------
1440 //! @brief Instruction operand flags.
1454 O_GB_MEM = O_GB | O_MEM,
1455 O_GW_MEM = O_GW | O_MEM,
1456 O_GD_MEM = O_GD | O_MEM,
1457 O_GQ_MEM = O_GQ | O_MEM,
1459 O_GQDWB = O_GQ | O_GD | O_GW | O_GB,
1460 O_GQDW = O_GQ | O_GD | O_GW,
1461 O_GQD = O_GQ | O_GD,
1462 O_GWB = O_GW | O_GB,
1464 O_GQDWB_MEM = O_GQDWB | O_MEM,
1465 O_GQDW_MEM = O_GQDW | O_MEM,
1466 O_GQD_MEM = O_GQD | O_MEM,
1467 O_GWB_MEM = O_GWB | O_MEM,
1469 O_MM_MEM = O_MM | O_MEM,
1470 O_XMM_MEM = O_XMM | O_MEM,
1471 O_MM_XMM = O_MM | O_XMM,
1472 O_MM_XMM_MEM = O_MM | O_XMM | O_MEM,
1475 O_FM_2 = O_MEM | 0x0100,
1476 O_FM_4 = O_MEM | 0x0200,
1477 O_FM_8 = O_MEM | 0x0400,
1478 O_FM_10 = O_MEM | 0x0800,
1480 O_FM_2_4 = O_FM_2 | O_FM_4,
1481 O_FM_2_4_8 = O_FM_2 | O_FM_4 | O_FM_8,
1482 O_FM_4_8 = O_FM_4 | O_FM_8,
1483 O_FM_4_8_10 = O_FM_4 | O_FM_8 | O_FM_10,
1485 // Don't emit REX prefix.
1489 // --------------------------------------------------------------------------
1491 // --------------------------------------------------------------------------
1493 //! @brief Instruction code.
1495 //! @brief Instruction name index in instructionName[] array.
1497 //! @brief Instruction group, used also by @c Compiler.
1499 //! @brief Instruction type flags.
1501 //! @brief First and second operand flags (some groups depends to these settings, used also by @c Compiler).
1503 //! @brief If instruction has only memory operand, this is register opcode.
1505 //! @brief Primary and secondary opcodes.
1508 //! @brief Get the instruction name (null terminated string).
1509 inline const char* getName() const { return instructionName + nameIndex; }
1511 //! @brief Get whether the instruction is conditional or standard jump.
1512 inline bool isJump() const { return (flags & F_JUMP) != 0; }
1513 //! @brief Get whether the instruction is MOV type.
1514 inline bool isMov() const { return (flags & F_MOV) != 0; }
1515 //! @brief Get whether the instruction is X87 FPU type.
1516 inline bool isFPU() const { return (flags & F_FPU) != 0; }
1517 //! @brief Get whether the instruction can be prefixed by LOCK prefix.
1518 inline bool isLockable() const { return (flags & F_LOCKABLE) != 0; }
1520 //! @brief Get whether the instruction is special type (this is used by
1521 //! @c Compiler to manage additional variables or functionality).
1522 inline bool isSpecial() const { return (flags & F_SPECIAL) != 0; }
1523 //! @brief Get whether the instruction is special type and it performs
1525 inline bool isSpecialMem() const { return (flags & F_SPECIAL_MEM) != 0; }
1528 ASMJIT_API extern const InstructionDescription instructionDescription[];
1530 // ============================================================================
1531 // [AsmJit::EMIT_OPTIONS]
1532 // ============================================================================
1534 //! @brief Emit options, mainly for internal purposes.
1537 //! @brief Force REX prefix to be emitted.
1539 //! This option should be used carefully, because there are unencodable
1540 //! combinations. If you want to access ah, bh, ch or dh registers then you
1541 //! can't emit REX prefix and it will cause an illegal instruction error.
1542 EMIT_OPTION_REX_PREFIX = (1 << 0),
1544 //! @brief Tell @c Assembler or @c Compiler to emit and validate lock prefix.
1546 //! If this option is used and instruction doesn't support LOCK prefix then
1547 //! invalid instruction error is generated.
1548 EMIT_OPTION_LOCK_PREFIX = (1 << 1),
1550 //! @brief Emit short/near jump or conditional jump instead of far one,
1551 //! saving some bytes.
1552 EMIT_OPTION_SHORT_JUMP = (1 << 2)
1555 // ============================================================================
1556 // [AsmJit::CALL_CONV]
1557 // ============================================================================
1559 //! @brief Calling convention type.
1561 //! Calling convention is scheme how function arguments are passed into
1562 //! function and how functions returns values. In assembler programming
1563 //! it's needed to always comply with function calling conventions, because
1564 //! even small inconsistency can cause undefined behavior or crash.
1566 //! List of calling conventions for 32-bit x86 mode:
1567 //! - @c CALL_CONV_CDECL - Calling convention for C runtime.
1568 //! - @c CALL_CONV_STDCALL - Calling convention for WinAPI functions.
1569 //! - @c CALL_CONV_MSTHISCALL - Calling convention for C++ members under
1570 //! Windows (produced by MSVC and all MSVC compatible compilers).
1571 //! - @c CALL_CONV_MSFASTCALL - Fastest calling convention that can be used
1572 //! by MSVC compiler.
1573 //! - @c CALL_CONV_BORNANDFASTCALL - Borland fastcall convention.
1574 //! - @c CALL_CONV_GCCFASTCALL - GCC fastcall convention (2 register arguments).
1575 //! - @c CALL_CONV_GCCREGPARM_1 - GCC regparm(1) convention.
1576 //! - @c CALL_CONV_GCCREGPARM_2 - GCC regparm(2) convention.
1577 //! - @c CALL_CONV_GCCREGPARM_3 - GCC regparm(3) convention.
1579 //! List of calling conventions for 64-bit x86 mode (x64):
1580 //! - @c CALL_CONV_X64W - Windows 64-bit calling convention (WIN64 ABI).
1581 //! - @c CALL_CONV_X64U - Unix 64-bit calling convention (AMD64 ABI).
1583 //! There is also @c CALL_CONV_DEFAULT that is defined to fit best to your
1586 //! These types are used together with @c AsmJit::Compiler::newFunction()
1590 //! @brief Calling convention is invalid (can't be used).
1593 // [X64 Calling Conventions]
1595 //! @brief X64 calling convention for Windows platform (WIN64 ABI).
1597 //! For first four arguments are used these registers:
1598 //! - 1. 32/64-bit integer or floating point argument - rcx/xmm0
1599 //! - 2. 32/64-bit integer or floating point argument - rdx/xmm1
1600 //! - 3. 32/64-bit integer or floating point argument - r8/xmm2
1601 //! - 4. 32/64-bit integer or floating point argument - r9/xmm3
1603 //! Note first four arguments here means arguments at positions from 1 to 4
1604 //! (included). For example if second argument is not passed by register then
1605 //! rdx/xmm1 register is unused.
1607 //! All other arguments are pushed on the stack in right-to-left direction.
1608 //! Stack is aligned by 16 bytes. There is 32-byte shadow space on the stack
1609 //! that can be used to save up to four 64-bit registers (probably designed to
1610 //! be used to save first four arguments passed in registers).
1612 //! Arguments direction:
1613 //! - Right to Left (except for first 4 parameters that's in registers)
1615 //! Stack is cleaned by:
1619 //! - Integer types - RAX register.
1620 //! - Floating points - XMM0 register.
1622 //! Stack is always aligned by 16 bytes.
1624 //! More information about this calling convention can be found on MSDN:
1625 //! http://msdn.microsoft.com/en-us/library/9b372w95.aspx .
1628 //! @brief X64 calling convention for Unix platforms (AMD64 ABI).
1630 //! First six 32 or 64-bit integer arguments are passed in rdi, rsi, rdx,
1631 //! rcx, r8, r9 registers. First eight floating point or XMM arguments
1632 //! are passed in xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7 registers.
1633 //! This means that in registers can be transferred up to 14 arguments total.
1635 //! There is also RED ZONE below the stack pointer that can be used for
1636 //! temporary storage. The red zone is the space from [rsp-128] to [rsp-8].
1638 //! Arguments direction:
1639 //! - Right to Left (Except for arguments passed in registers).
1641 //! Stack is cleaned by:
1645 //! - Integer types - RAX register.
1646 //! - Floating points - XMM0 register.
1648 //! Stack is always aligned by 16 bytes.
1651 // [X86 Calling Conventions]
1653 //! @brief Cdecl calling convention (used by C runtime).
1655 //! Compatible across MSVC and GCC.
1657 //! Arguments direction:
1660 //! Stack is cleaned by:
1662 CALL_CONV_CDECL = 3,
1664 //! @brief Stdcall calling convention (used by WinAPI).
1666 //! Compatible across MSVC and GCC.
1668 //! Arguments direction:
1671 //! Stack is cleaned by:
1675 //! - Integer types - EAX:EDX registers.
1676 //! - Floating points - st(0) register.
1677 CALL_CONV_STDCALL = 4,
1679 //! @brief MSVC specific calling convention used by MSVC/Intel compilers
1680 //! for struct/class methods.
1682 //! This is MSVC (and Intel) only calling convention used in Windows
1683 //! world for C++ class methods. Implicit 'this' pointer is stored in
1684 //! ECX register instead of storing it on the stack.
1686 //! Arguments direction:
1687 //! - Right to Left (except this pointer in ECX)
1689 //! Stack is cleaned by:
1693 //! - Integer types - EAX:EDX registers.
1694 //! - Floating points - st(0) register.
1696 //! C++ class methods that have variable count of arguments uses different
1697 //! calling convention called cdecl.
1699 //! @note This calling convention is always used by MSVC for class methods,
1700 //! it's implicit and there is no way how to override it.
1701 CALL_CONV_MSTHISCALL = 5,
1703 //! @brief MSVC specific fastcall.
1705 //! Two first parameters (evaluated from left-to-right) are in ECX:EDX
1706 //! registers, all others on the stack in right-to-left order.
1708 //! Arguments direction:
1709 //! - Right to Left (except to first two integer arguments in ECX:EDX)
1711 //! Stack is cleaned by:
1715 //! - Integer types - EAX:EDX registers.
1716 //! - Floating points - st(0) register.
1718 //! @note This calling convention differs to GCC one in stack cleaning
1720 CALL_CONV_MSFASTCALL = 6,
1722 //! @brief Borland specific fastcall with 2 parameters in registers.
1724 //! Two first parameters (evaluated from left-to-right) are in ECX:EDX
1725 //! registers, all others on the stack in left-to-right order.
1727 //! Arguments direction:
1728 //! - Left to Right (except to first two integer arguments in ECX:EDX)
1730 //! Stack is cleaned by:
1734 //! - Integer types - EAX:EDX registers.
1735 //! - Floating points - st(0) register.
1737 //! @note Arguments on the stack are in left-to-right order that differs
1738 //! to other fastcall conventions used in different compilers.
1739 CALL_CONV_BORLANDFASTCALL = 7,
1741 //! @brief GCC specific fastcall convention.
1743 //! Two first parameters (evaluated from left-to-right) are in ECX:EDX
1744 //! registers, all others on the stack in right-to-left order.
1746 //! Arguments direction:
1747 //! - Right to Left (except to first two integer arguments in ECX:EDX)
1749 //! Stack is cleaned by:
1753 //! - Integer types - EAX:EDX registers.
1754 //! - Floating points - st(0) register.
1756 //! @note This calling convention should be compatible to
1757 //! @c CALL_CONV_MSFASTCALL.
1758 CALL_CONV_GCCFASTCALL = 8,
1760 //! @brief GCC specific regparm(1) convention.
1762 //! The first parameter (evaluated from left-to-right) is in EAX register,
1763 //! all others on the stack in right-to-left order.
1765 //! Arguments direction:
1766 //! - Right to Left (except to first one integer argument in EAX)
1768 //! Stack is cleaned by:
1772 //! - Integer types - EAX:EDX registers.
1773 //! - Floating points - st(0) register.
1774 CALL_CONV_GCCREGPARM_1 = 9,
1776 //! @brief GCC specific regparm(2) convention.
1778 //! Two first parameters (evaluated from left-to-right) are in EAX:EDX
1779 //! registers, all others on the stack in right-to-left order.
1781 //! Arguments direction:
1782 //! - Right to Left (except to first two integer arguments in EAX:EDX)
1784 //! Stack is cleaned by:
1788 //! - Integer types - EAX:EDX registers.
1789 //! - Floating points - st(0) register.
1790 CALL_CONV_GCCREGPARM_2 = 10,
1792 //! @brief GCC specific fastcall with 3 parameters in registers.
1794 //! Three first parameters (evaluated from left-to-right) are in
1795 //! EAX:EDX:ECX registers, all others on the stack in right-to-left order.
1797 //! Arguments direction:
1798 //! - Right to Left (except to first three integer arguments in EAX:EDX:ECX)
1800 //! Stack is cleaned by:
1804 //! - Integer types - EAX:EDX registers.
1805 //! - Floating points - st(0) register.
1806 CALL_CONV_GCCREGPARM_3 = 11,
1808 // [Preferred Calling Convention]
1810 //! @def CALL_CONV_DEFAULT
1811 //! @brief Default calling convention for current platform / operating system.
1813 #if defined(ASMJIT_X86)
1815 CALL_CONV_DEFAULT = CALL_CONV_CDECL,
1817 # if defined(_MSC_VER)
1818 CALL_CONV_COMPAT_FASTCALL = CALL_CONV_MSFASTCALL,
1819 # elif defined(__GNUC__)
1820 CALL_CONV_COMPAT_FASTCALL = CALL_CONV_GCCFASTCALL,
1821 # elif defined(__BORLANDC__)
1822 CALL_CONV_COMPAT_FASTCALL = CALL_CONV_BORLANDFASTCALL,
1824 # error "AsmJit::CALL_CONV_COMPATIBLE_FASTCALL_2 - Unsupported."
1827 CALL_CONV_COMPAT_STDCALL = CALL_CONV_STDCALL,
1828 CALL_CONV_COMPAT_CDECL = CALL_CONV_CDECL
1832 # if defined(ASMJIT_WINDOWS)
1833 CALL_CONV_DEFAULT = CALL_CONV_X64W,
1835 CALL_CONV_DEFAULT = CALL_CONV_X64U,
1838 CALL_CONV_COMPAT_FASTCALL = CALL_CONV_DEFAULT,
1839 CALL_CONV_COMPAT_STDCALL = CALL_CONV_DEFAULT,
1840 CALL_CONV_COMPAT_CDECL = CALL_CONV_DEFAULT
1842 #endif // ASMJIT_X86
1845 // ============================================================================
1846 // [AsmJit::VARIABLE_TYPE]
1847 // ============================================================================
1849 //! @brief Variable type.
1852 // --------------------------------------------------------------------------
1853 // [Platform Dependent]
1854 // --------------------------------------------------------------------------
1856 //! @brief Variable is 32-bit general purpose register.
1857 VARIABLE_TYPE_GPD = 0,
1858 //! @brief Variable is 64-bit general purpose register.
1859 VARIABLE_TYPE_GPQ = 1,
1861 //! @var VARIABLE_TYPE_GPN
1862 //! @brief Variable is system wide general purpose register (32-bit or 64-bit).
1863 #if defined(ASMJIT_X86)
1864 VARIABLE_TYPE_GPN = VARIABLE_TYPE_GPD,
1866 VARIABLE_TYPE_GPN = VARIABLE_TYPE_GPQ,
1869 //! @brief Variable is X87 (FPU).
1870 VARIABLE_TYPE_X87 = 2,
1872 //! @brief Variable is X87 (FPU) SP-FP number (float).
1873 VARIABLE_TYPE_X87_1F = 3,
1875 //! @brief Variable is X87 (FPU) DP-FP number (double).
1876 VARIABLE_TYPE_X87_1D = 4,
1878 //! @brief Variable is MM register / memory location.
1879 VARIABLE_TYPE_MM = 5,
1881 //! @brief Variable is XMM register / memory location.
1882 VARIABLE_TYPE_XMM = 6,
1884 //! @brief Variable is SSE scalar SP-FP number.
1885 VARIABLE_TYPE_XMM_1F = 7,
1886 //! @brief Variable is SSE packed SP-FP number (4 floats).
1887 VARIABLE_TYPE_XMM_4F = 8,
1889 //! @brief Variable is SSE2 scalar DP-FP number.
1890 VARIABLE_TYPE_XMM_1D = 9,
1891 //! @brief Variable is SSE2 packed DP-FP number (2 doubles).
1892 VARIABLE_TYPE_XMM_2D = 10,
1894 //! @brief Count of variable types.
1895 _VARIABLE_TYPE_COUNT = 11,
1897 // --------------------------------------------------------------------------
1898 // [Platform Independent]
1899 // --------------------------------------------------------------------------
1901 //! @brief Variable is 32-bit integer.
1902 VARIABLE_TYPE_INT32 = VARIABLE_TYPE_GPD,
1903 //! @brief Variable is 64-bit integer.
1904 VARIABLE_TYPE_INT64 = VARIABLE_TYPE_GPQ,
1905 //! @brief Variable is system dependent integer / pointer.
1906 VARIABLE_TYPE_INTPTR = VARIABLE_TYPE_GPN,
1908 #if !defined(ASMJIT_NODOC)
1909 #if defined(ASMJIT_X86)
1910 VARIABLE_TYPE_FLOAT = VARIABLE_TYPE_X87_1F,
1911 VARIABLE_TYPE_DOUBLE = VARIABLE_TYPE_X87_1D
1913 VARIABLE_TYPE_FLOAT = VARIABLE_TYPE_XMM_1F,
1914 VARIABLE_TYPE_DOUBLE = VARIABLE_TYPE_XMM_1D
1917 //! @brief Variable is SP-FP (x87 or xmm).
1918 VARIABLE_TYPE_FLOAT = XXX,
1919 //! @brief Variable is DP-FP (x87 or xmm).
1920 VARIABLE_TYPE_DOUBLE = XXX
1924 // ============================================================================
1925 // [AsmJit::VARIABLE_HINT]
1926 // ============================================================================
1928 //! @brief Variable hint (used by @ref Compiler).
1930 //! @sa @ref Compiler.
1933 //! @brief Alloc variable.
1934 VARIABLE_HINT_ALLOC = 0,
1935 //! @brief Spill variable.
1936 VARIABLE_HINT_SPILL = 1,
1937 //! @brief Save variable if modified.
1938 VARIABLE_HINT_SAVE = 2,
1939 //! @brief Save variable if modified and mark it as unused.
1940 VARIABLE_HINT_SAVE_AND_UNUSE = 3,
1941 //! @brief Mark variable as unused.
1942 VARIABLE_HINT_UNUSE = 4
1947 } // AsmJit namespace
1953 #endif // _ASMJIT_DEFSX86X64_H