6 #include "mem_layout.h"
19 Valid = 0x00000001LL, ///< Valid
20 Writable = 0x00000002LL, ///< Writable
21 User = 0x00000004LL, ///< User accessible
22 Write_through = 0x00000008LL, ///< Write through
23 Cacheable = 0x00000000LL, ///< Cache is enabled
24 Noncacheable = 0x00000010LL, ///< Caching is off
25 Referenced = 0x00000020LL, ///< Page was referenced
26 Dirty = 0x00000040LL, ///< Page was modified
27 Pse_bit = 0x00000080LL, ///< Indicates a super page
28 Cpu_global = 0x00000100LL, ///< pinned in the TLB
29 L4_global = 0x00000200LL, ///< pinned in the TLB
30 Pfn = 0x000ffffffffff000LL, ///< page frame number
33 Mword addr() const { return _raw & Pfn; }
39 static Unsigned32 _cpu_global;
42 class Pt_entry : public Pte_base
45 enum { Page_shift = Config::PAGE_SHIFT };
46 Mword leaf() const { return true; }
47 void set(Address p, bool intermed, bool present, unsigned long attrs = 0)
49 _raw = (p & Pfn) | (present ? 1 : 0)
50 | (intermed ? (Writable | User | Cacheable) : 0) | attrs;
54 class Pd_entry : public Pte_base
57 enum { Page_shift = Config::SUPERPAGE_SHIFT };
58 Mword leaf() const { return _raw & Pse_bit; }
59 void set(Address p, bool intermed, bool present, unsigned long attrs = 0)
61 _raw = (p & Pfn) | (present ? 1 : 0)
62 | (intermed ? (Writable | User | Cacheable) : Pse_bit) | attrs;
66 class Pdp_entry : public Pte_base
69 // this is just a dummy, because there are no real pages on level 0 and 1
70 enum { Page_shift = 0 };
71 Mword leaf() const { return false; }
72 void set(Address p, bool, bool present, unsigned long attrs = 0)
74 _raw = (p & Pfn) | (present ? 1 : 0)
75 | (Writable | User | Cacheable) | attrs;
80 typedef Ptab::List< Ptab::Traits<Pdp_entry, 39, 9, false>,
81 Ptab::List< Ptab::Traits<Pdp_entry, 30, 9, false>,
82 Ptab::List< Ptab::Traits<Pd_entry, 21, 9, true>,
83 Ptab::Traits<Pt_entry, 12, 9, true> > > > Ptab_traits;
85 typedef Ptab::Shift<Ptab_traits, Virt_addr::Shift>::List Ptab_traits_vpn;
86 typedef Ptab::Page_addr_wrap<Page_number, Virt_addr::Shift> Ptab_va_vpn;