6 //-----------------------------------------------------------------------------
7 INTERFACE [arm && armv5]:
14 typedef Unsigned32 Attribs;
18 KERN_RW = 0x0400, ///< User No access
19 USER_RO = 0x0000, ///< User Read only
20 USER_RW = 0x0c00, ///< User Read/Write
25 NONCACHEABLE = 0x00, ///< Caching is off
26 CACHEABLE = 0x0c, ///< Cache is enabled
28 // The next are ARM specific
29 WRITETHROUGH = 0x08, ///< Write through cached
30 BUFFERED = 0x04, ///< Write buffer enabled
41 //----------------------------------------------------------------------------
42 INTERFACE [arm && (armv6 || armv7)]:
48 typedef Unsigned32 Attribs;
53 KERN_RW = 0x0010, ///< User No access
54 USER_RO = 0x0230, ///< User Read only
55 USER_RW = 0x0030, ///< User Read/Write
60 NONCACHEABLE = 0x000, ///< Caching is off
61 CACHEABLE = 0x144, ///< Cache is enabled
63 // The next are ARM specific
64 WRITETHROUGH = 0x08, ///< Write through cached
65 BUFFERED = 0x40, ///< Write buffer enabled -- Normal, non-cached
73 //-----------------------------------------------------------------------------
76 #include "ptab_base.h"
93 Raw raw() const { return _raw; }
94 Address addr() const { return _raw & (~0UL << 12); }
100 class Pd_entry : public Pte_base
103 enum { Page_shift = Config::SUPERPAGE_SHIFT };
104 Mword leaf() const { return (_raw & Type_mask) == Type_1MB; }
105 void set(Address p, bool intermed, bool present, unsigned long attrs = 0)
107 _raw = (p & (~0UL << Page_shift))
108 | (present ? (intermed ? Type_coarse_pt : Type_1MB) : 0) | attrs;
112 class Pt_entry : public Pte_base
115 enum { Page_shift = Config::PAGE_SHIFT };
116 Mword leaf() const { return true; }
117 void set(Address p, bool, bool present, unsigned long attrs = 0)
119 _raw = (p & (~0UL << Page_shift)) | (present ? Type_4KB : 0) | attrs;
123 typedef Ptab::List< Ptab::Traits< Pd_entry, 20, 12, true>,
124 Ptab::Traits< Pt_entry, 12, 8, true> > Ptab_traits;
126 typedef Ptab_traits Ptab_traits_vpn;
127 typedef Ptab::Page_addr_wrap<Virt_addr, 0> Ptab_va_vpn;
129 //---------------------------------------------------------------------------
130 IMPLEMENTATION [arm && armv5]:
133 Mword PF::is_alignment_error(Mword error)
134 { return (error & 0xf0000d) == 0x400001; }
136 //---------------------------------------------------------------------------
137 IMPLEMENTATION [arm && (armv6 || armv7)]:
140 Mword PF::is_alignment_error(Mword error)
141 { return (error & 0xf0040f) == 0x400001; }
143 //---------------------------------------------------------------------------
144 IMPLEMENTATION [arm]:
153 Pte_base::valid() const
159 Mword PF::is_translation_error( Mword error )
161 return (error & 0x0d/*FSR_STATUS_MASK*/) == 0x05/*FSR_TRANSL*/;
165 Mword PF::is_usermode_error( Mword error )
167 return (error & 0x00010000/*PF_USERMODE*/);
171 Mword PF::is_read_error( Mword error )
173 return !(error & (1UL << 11));
177 Mword PF::addr_to_msgword0( Address pfa, Mword error )
180 if(is_translation_error( error ))
182 if(!is_read_error(error))