9 * Author Copyright (c) Marc A. Viredaz, 1998
10 * DEC Western Research Laboratory, Palo Alto, CA
11 * Date January 1998 (April 1997)
12 * System StrongARM SA-1100
13 * Language C or ARM Assembly
14 * Purpose Definition of constants related to the StrongARM
15 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
16 * architecture version 4). This file is based on the
17 * StrongARM SA-1100 data sheet version 2.2.
19 * Language-specific definitions are selected by the
20 * macro "LANGUAGE", which should be defined as either
21 * "C" (default) or "Assembly".
23 * and hacked by davep@crl.dec.com
26 #define Fld(Size, Shft) (((Size) << 16) + (Shft))
27 #define FSize(Field) ((Field) >> 16)
28 #define FShft(Field) ((Field) & 0x0000FFFF)
29 #define FMsk(Field) (((UData (1) << FSize (Field)) - 1) << FShft (Field))
30 #define FAlnMsk(Field) ((UData (1) << FSize (Field)) - 1)
31 #define F1stBit(Field) (UData (1) << FShft (Field))
33 #define LCD_MAX_BPP (16) /* that we allow in this simple situation */
35 #define LCD_MONO_BPP (4)
36 #define LCD_XRES (320)
37 #define LCD_YRES (240)
39 #define MAX_PALETTE_COLORS() (1<<12)
40 #define NUM_PALETTE_ENTRIES(bpp) ((bpp)==8?256:16)
41 #define PALETTE_MEM_SIZE(bpp) (NUM_PALETTE_ENTRIES(bpp)<<1)
42 #define PALETTE_MODE_VAL(bpp) (((bpp) & 0x018) << 9)
44 #define LCD_PALETTE_SIZExx (512)
45 #define LCD_NUM_PIXELS() (LCD_XRES * LCD_YRES)
46 #define LCD_NUM_DISPLAY_BYTES(bpp) ((LCD_NUM_PIXELS() * (bpp) + 7)/8)
48 #define LCD_FB_SIZE(bpp) ((LCD_NUM_DISPLAY_BYTES(bpp) + \
49 PALETTE_MEM_SIZE(bpp) + 3) & ~3)
51 #define LCD_FB_MAX() LCD_FB_SIZE(LCD_MAX_BPP)
52 #define LCD_FB_IMAGE_OFFSET(bpp) PALETTE_MEM_SIZE(bpp)
53 #define LCD_FB_IMAGE(p, bpp) (((char*)(p)) + LCD_FB_IMAGE_OFFSET(bpp))
56 typedef unsigned long u_long;
57 typedef unsigned long Word;
58 typedef unsigned long Address;
61 * Liquid Crystal Display (LCD) control registers
64 * LCCR0 Liquid Crystal Display (LCD) Control Register 0
66 * [Bits LDM, BAM, and ERM are only implemented in
67 * versions 2.0 (rev. = 8) and higher of the StrongARM
69 * LCSR Liquid Crystal Display (LCD) Status Register
71 * [Bit LDD can be only read in versions 1.0 (rev. = 1)
72 * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
73 * read and written (cleared) in versions 2.0 (rev. = 8)
75 * DBAR1 Liquid Crystal Display (LCD) Direct Memory Access
76 * (DMA) Base Address Register channel 1 (read/write).
77 * DCAR1 Liquid Crystal Display (LCD) Direct Memory Access
78 * (DMA) Current Address Register channel 1 (read).
79 * DBAR2 Liquid Crystal Display (LCD) Direct Memory Access
80 * (DMA) Base Address Register channel 2 (read/write).
81 * DCAR2 Liquid Crystal Display (LCD) Direct Memory Access
82 * (DMA) Current Address Register channel 2 (read).
83 * LCCR1 Liquid Crystal Display (LCD) Control Register 1
85 * [The LCCR1 register can be only written in
86 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
87 * StrongARM SA-1100, it can be written and read in
88 * versions 2.0 (rev. = 8) and higher.]
89 * LCCR2 Liquid Crystal Display (LCD) Control Register 2
91 * [The LCCR1 register can be only written in
92 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
93 * StrongARM SA-1100, it can be written and read in
94 * versions 2.0 (rev. = 8) and higher.]
95 * LCCR3 Liquid Crystal Display (LCD) Control Register 3
97 * [The LCCR1 register can be only written in
98 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
99 * StrongARM SA-1100, it can be written and read in
100 * versions 2.0 (rev. = 8) and higher. Bit PCP is only
101 * implemented in versions 2.0 (rev. = 8) and higher of
102 * the StrongARM SA-1100.]
105 * fcpu, Tcpu Frequency, period of the CPU core clock (CCLK).
106 * fmem, Tmem Frequency, period of the memory clock (fmem = fcpu/2).
107 * fpix, Tpix Frequency, period of the pixel clock.
108 * fln, Tln Frequency, period of the line clock.
109 * fac, Tac Frequency, period of the AC bias clock.
112 #define LCD_PEntrySp 2 /* LCD Palette Entry Space [byte] */
113 #define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \
116 #define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \
119 #define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \
120 /* dummy-Palette Space [byte] */ \
123 #define LCD_PGrey Fld (4, 0) /* LCD Palette entry Grey value */
124 #define LCD_PBlue Fld (4, 0) /* LCD Palette entry Blue value */
125 #define LCD_PGreen Fld (4, 4) /* LCD Palette entry Green value */
126 #define LCD_PRed Fld (4, 8) /* LCD Palette entry Red value */
127 #define LCD_PBS Fld (2, 12) /* LCD Pixel Bit Size */
128 #define LCD_4Bit /* LCD 4-Bit pixel mode */ \
129 (0 << FShft (LCD_PBS))
130 #define LCD_8Bit /* LCD 8-Bit pixel mode */ \
131 (1 << FShft (LCD_PBS))
132 #define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \
133 (2 << FShft (LCD_PBS))
135 #define LCD_Int0_0 0x0 /* LCD Intensity = 0.0% = 0 */
136 #define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */
137 #define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */
138 #define LCD_Int26_7 0x3 /* LCD Intensity = 26.7% = 4/15 */
139 #define LCD_Int33_3 0x4 /* LCD Intensity = 33.3% = 3/9 */
140 #define LCD_Int40_0 0x5 /* LCD Intensity = 40.0% = 2/5 */
141 #define LCD_Int44_4 0x6 /* LCD Intensity = 44.4% = 4/9 */
142 #define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */
143 #define LCD_Int55_6 0x8 /* LCD Intensity = 55.6% = 5/9 */
144 #define LCD_Int60_0 0x9 /* LCD Intensity = 60.0% = 3/5 */
145 #define LCD_Int66_7 0xA /* LCD Intensity = 66.7% = 6/9 */
146 #define LCD_Int73_3 0xB /* LCD Intensity = 73.3% = 11/15 */
147 #define LCD_Int80_0 0xC /* LCD Intensity = 80.0% = 4/5 */
148 #define LCD_Int88_9 0xD /* LCD Intensity = 88.9% = 8/9 */
149 #define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */
150 #define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
153 #define _LCCR0 0xB0100000 /* LCD Control Reg. 0 */
154 #define _LCSR 0xB0100004 /* LCD Status Reg. */
155 #define _DBAR1 0xB0100010 /* LCD DMA Base Address Reg. */
157 #define _DCAR1 0xB0100014 /* LCD DMA Current Address Reg. */
159 #define _DBAR2 0xB0100018 /* LCD DMA Base Address Reg. */
161 #define _DCAR2 0xB010001C /* LCD DMA Current Address Reg. */
163 #define _LCCR1 0xB0100020 /* LCD Control Reg. 1 */
164 #define _LCCR2 0xB0100024 /* LCD Control Reg. 2 */
165 #define _LCCR3 0xB0100028 /* LCD Control Reg. 3 */
168 #define LCCR0 /* LCD Control Reg. 0 */ \
169 (*((volatile Word *) io_p2v (_LCCR0)))
170 #define LCSR /* LCD Status Reg. */ \
171 (*((volatile Word *) io_p2v (_LCSR)))
172 #define DBAR1 /* LCD DMA Base Address Reg. */ \
174 (*((volatile Address *) io_p2v (_DBAR1)))
175 #define DCAR1 /* LCD DMA Current Address Reg. */ \
177 (*((volatile Address *) io_p2v (_DCAR1)))
178 #define DBAR2 /* LCD DMA Base Address Reg. */ \
180 (*((volatile Address *) io_p2v (_DBAR2)))
181 #define DCAR2 /* LCD DMA Current Address Reg. */ \
183 (*((volatile Address *) io_p2v (_DCAR2)))
184 #define LCCR1 /* LCD Control Reg. 1 */ \
185 (*((volatile Word *) io_p2v (_LCCR1)))
186 #define LCCR2 /* LCD Control Reg. 2 */ \
187 (*((volatile Word *) io_p2v (_LCCR2)))
188 #define LCCR3 /* LCD Control Reg. 3 */ \
189 (*((volatile Word *) io_p2v (_LCCR3)))
190 #endif /* LANGUAGE == C */
192 #define LCCR0_LEN 0x00000001 /* LCD ENable */
193 #define LCCR0_CMS 0x00000002 /* Color/Monochrome display Select */
194 #define LCCR0_Color (LCCR0_CMS*0) /* Color display */
195 #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
196 #define LCCR0_SDS 0x00000004 /* Single/Dual panel display */
198 #define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
199 #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
200 #define LCCR0_LDM 0x00000008 /* LCD Disable done (LDD) */
201 /* interrupt Mask (disable) */
202 #define LCCR0_BAM 0x00000010 /* Base Address update (BAU) */
203 /* interrupt Mask (disable) */
204 #define LCCR0_ERM 0x00000020 /* LCD ERror (BER, IOL, IUL, IOU, */
205 /* IUU, OOL, OUL, OOU, and OUU) */
206 /* interrupt Mask (disable) */
207 #define LCCR0_PAS 0x00000080 /* Passive/Active display Select */
208 #define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
209 #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
210 #define LCCR0_BLE 0x00000100 /* Big/Little Endian select */
211 #define LCCR0_LtlEnd (LCCR0_BLE*0) /* Little Endian frame buffer */
212 #define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */
213 #define LCCR0_DPD 0x00000200 /* Double Pixel Data (monochrome */
215 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
217 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
219 #define LCCR0_PDD Fld (8, 12) /* Palette DMA request Delay */
221 #define LCCR0_DMADel(Tcpu) /* palette DMA request Delay */ \
222 /* [0..510 Tcpu] */ \
223 ((Tcpu)/2 << FShft (LCCR0_PDD))
225 #define LCSR_LDD 0x00000001 /* LCD Disable Done */
226 #define LCSR_BAU 0x00000002 /* Base Address Update (read) */
227 #define LCSR_BER 0x00000004 /* Bus ERror */
228 #define LCSR_ABC 0x00000008 /* AC Bias clock Count */
229 #define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */
231 #define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */
233 #define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */
235 #define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */
237 #define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */
239 #define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */
241 #define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */
243 #define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */
246 #define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */
247 #define LCCR1_DisWdth(Pixel) /* Display Width [16..1024 pix.] */ \
248 (((Pixel) - 16)/16 << FShft (LCCR1_PPL))
249 #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
250 /* pulse Width - 2 [Tpix] (L_LCLK) */
251 #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
252 /* pulse Width [2..65 Tpix] */ \
253 (((Tpix) - 2) << FShft (LCCR1_HSW))
254 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
255 /* count - 1 [Tpix] */
256 #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
257 /* [1..256 Tpix] */ \
258 (((Tpix) - 1) << FShft (LCCR1_ELW))
259 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
260 /* Wait count - 1 [Tpix] */
261 #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
262 /* [1..256 Tpix] */ \
263 (((Tpix) - 1) << FShft (LCCR1_BLW))
265 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
266 #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
267 (((Line) - 1) << FShft (LCCR2_LPP))
268 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
269 /* Width - 1 [Tln] (L_FCLK) */
270 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
271 /* Width [1..64 Tln] */ \
272 (((Tln) - 1) << FShft (LCCR2_VSW))
273 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
275 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
277 ((Tln) << FShft (LCCR2_EFW))
278 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
279 /* Wait count [Tln] */
280 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
282 ((Tln) << FShft (LCCR2_BFW))
284 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
285 /* [1..255] (L_PCLK) */
286 /* fpix = fcpu/(2*(PCD + 2)) */
287 /* Tpix = 2*(PCD + 2)*Tcpu */
288 #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor [6..514] */ \
289 (((Div) - 4)/2 << FShft (LCCR3_PCD))
290 /* fpix = fcpu/(2*Floor (Div/2)) */
291 /* Tpix = 2*Floor (Div/2)*Tcpu */
292 #define LCCR3_CeilPixClkDiv(Div) /* Ceil. of PixClkDiv [6..514] */ \
293 (((Div) - 3)/2 << FShft (LCCR3_PCD))
294 /* fpix = fcpu/(2*Ceil (Div/2)) */
295 /* Tpix = 2*Ceil (Div/2)*Tcpu */
296 #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */
298 #define LCCR3_ACBsDiv(Div) /* AC Bias clock Divisor [2..512] */ \
299 (((Div) - 2)/2 << FShft (LCCR3_ACB))
300 /* fac = fln/(2*Floor (Div/2)) */
301 /* Tac = 2*Floor (Div/2)*Tln */
302 #define LCCR3_CeilACBsDiv(Div) /* Ceil. of ACBsDiv [2..512] */ \
303 (((Div) - 1)/2 << FShft (LCCR3_ACB))
304 /* fac = fln/(2*Ceil (Div/2)) */
305 /* Tac = 2*Ceil (Div/2)*Tln */
306 #define LCCR3_API Fld (4, 16) /* AC bias Pin transitions per */
308 #define LCCR3_ACBsCntOff /* AC Bias clock transition Count */ \
310 (0 << FShft (LCCR3_API))
311 #define LCCR3_ACBsCnt(Trans) /* AC Bias clock transition Count */ \
313 ((Trans) << FShft (LCCR3_API))
314 #define LCCR3_VSP 0x00100000 /* Vertical Synchronization pulse */
315 /* Polarity (L_FCLK) */
316 #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
318 #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
320 #define LCCR3_HSP 0x00200000 /* Horizontal Synchronization */
321 /* pulse Polarity (L_LCLK) */
322 #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
323 /* pulse active High */
324 #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
325 /* pulse active Low */
326 #define LCCR3_PCP 0x00400000 /* Pixel Clock Polarity (L_PCLK) */
327 #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
328 #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
329 #define LCCR3_OEP 0x00800000 /* Output Enable Polarity (L_BIAS, */
330 /* active display mode) */
331 #define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
332 #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
334 #endif /* _SA1100_LCD_H_ */