kernel/fiasco/src/kern/arm/bsp/omap/pic-arm-gic-omap4.cpp

   1 INTERFACE [arm && pic_gic && omap4]:
   2
   3 #include "gic.h"
   4
   5 // ------------------------------------------------------------------------
   6 IMPLEMENTATION [arm && pic_gic && omap4]:
   7
   8 #include "irq_mgr_multi_chip.h"
   9 #include "kmem.h"
  10
  11 IMPLEMENT FIASCO_INIT
  12 void
  13 Pic::init()
  14 {
  15   typedef Irq_mgr_multi_chip<8> M;
  16
  17   M *m = new Boot_object<M>(1);
  18
  19   gic.construct(Kmem::mmio_remap(Mem_layout::Gic_cpu_phys_base),
  20                 Kmem::mmio_remap(Mem_layout::Gic_dist_phys_base));
  21   m->add_chip(0, gic, gic->nr_irqs());
  22
  23   Irq_mgr::mgr = m;
  24 }
  25
  26 IMPLEMENT inline
  27 Pic::Status Pic::disable_all_save()
  28 { return 0; }
  29
  30 IMPLEMENT inline
  31 void Pic::restore_all(Status)
  32 {}
  33
  34 // ------------------------------------------------------------------------
  35 IMPLEMENTATION [arm && mp && pic_gic && omap4]:
  36
  37 PUBLIC static
  38 void Pic::init_ap(Cpu_number, bool resume)
  39 {
  40   gic->init_ap(resume);
  41 }