kernel/fiasco/src/kern/arm/bsp/tegra2/pic-arm-tegra2.cpp

   1 INTERFACE [arm && pic_gic && tegra2]:
   2
   3 #include "gic.h"
   4
   5 //-------------------------------------------------------------------
   6 IMPLEMENTATION [arm && pic_gic && tegra2]:
   7
   8 #include "irq_chip.h"
   9 #include "irq_mgr_multi_chip.h"
  10 #include "gic.h"
  11 #include "kmem.h"
  12
  13 IMPLEMENT FIASCO_INIT
  14 void Pic::init()
  15 {
  16   typedef Irq_mgr_multi_chip<8> M;
  17
  18   M *m = new Boot_object<M>(1);
  19
  20   gic.construct(Kmem::Gic_cpu_map_base, Kmem::Gic_dist_map_base);
  21   m->add_chip(0, gic, gic->nr_irqs());
  22
  23   Irq_mgr::mgr = m;
  24 }
  25
  26 IMPLEMENT inline
  27 Pic::Status Pic::disable_all_save()
  28 { return 0; }
  29
  30 IMPLEMENT inline
  31 void Pic::restore_all(Status)
  32 {}
  33
  34 //-------------------------------------------------------------------
  35 IMPLEMENTATION [arm && mp && pic_gic && tegra2]:
  36
  37 PUBLIC static
  38 void Pic::init_ap(unsigned)
  39 {
  40   gic->init_ap();
  41 }