1 //-----------------------------------------------------------------------------
2 INTERFACE [arm && imx]:
5 Cache_flush_area = 0xe0000000,
8 //-----------------------------------------------------------------------------
9 IMPLEMENTATION [arm && imx21]:
14 map_1mb(pd, Mem_layout::Device_map_base_1, Mem_layout::Device_phys_base_1, false, false);
17 //-----------------------------------------------------------------------------
18 IMPLEMENTATION [arm && imx35]:
22 map_1mb(pd, Mem_layout::Device_map_base_1, Mem_layout::Device_phys_base_1, false, false);
23 map_1mb(pd, Mem_layout::Device_map_base_2, Mem_layout::Device_phys_base_2, false, false);
24 map_1mb(pd, Mem_layout::Device_map_base_3, Mem_layout::Device_phys_base_3, false, false);
27 //-----------------------------------------------------------------------------
28 IMPLEMENTATION [arm && imx51]:
32 map_1mb(pd, Mem_layout::Device_map_base_1, Mem_layout::Device_phys_base_1, false, false);
33 map_1mb(pd, Mem_layout::Device_map_base_2, Mem_layout::Device_phys_base_2, false, false);