1 /****************************************************************************/
2 /* Copyright 2000 Compaq Computer Corporation. */
4 /* Copying or modifying this code for any purpose is permitted, */
5 /* provided that this copyright notice is preserved in its entirety */
6 /* in all copies or modifications. COMPAQ COMPUTER CORPORATION */
7 /* MAKES NO WARRANTIES, EXPRESSED OR IMPLIED, AS TO THE USEFULNESS */
8 /* OR CORRECTNESS OF THIS CODE OR ITS FITNESS FOR ANY PARTICULAR */
10 /****************************************************************************/
11 #ifndef SA1100_H_INCLUDED
12 #define SA1100_H_INCLUDED
24 #define UTCR0_PE (1 << 0) /* parity enable */
25 #define UTCR0_OES (1 << 1) /* 1 for even parity */
26 #define UTCR0_2STOP (1 << 2) /* 1 for 2 stop bits */
27 #define UTCR0_8BIT (1 << 3) /* 1 for 8 bit data */
28 #define UTCR0_SCE (1 << 4) /* sample clock enable */
29 #define UTCR0_RCE (1 << 5) /* receive clock edge select */
30 #define UTCR0_TCE (1 << 6) /* transmit clock edge select */
32 #define UTCR1_BRDHIMASK 0xF
33 #define UTCR2_BRDLoMASK 0xFF
35 #define UTCR3_RXE (1 << 0) /* receiver enable */
36 #define UTCR3_TXE (1 << 1) /* transmit enable */
37 #define UTCR3_BRK (1 << 2) /* send a BRK */
38 #define UTCR3_RIE (1 << 3) /* receive FIFO interrupt enable */
39 #define UTCR3_TIE (1 << 4) /* transmit FIFO interrupt enable */
40 #define UTCR3_LBM (1 << 5) /* loopback mode */
43 #define UTDR_PRE (1 << 8) /* parity error */
44 #define UTDR_FRE (1 << 9) /* framing error */
45 #define UTDR_ROR (1 << 10) /* receiver overrun */
48 #define UTSR0_TFS 0x00000001 /* transmit FIFO service request */
49 #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */
50 /* more Service request (read) */
51 #define UTSR0_RID 0x00000004 /* Receiver IDle */
52 #define UTSR0_RBB 0x00000008 /* Receive Beginning of Break */
53 #define UTSR0_REB 0x00000010 /* Receive End of Break */
54 #define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */
57 #define UTSR1_TBY (1 << 0) /* transmit FIFO busy */
58 #define UTSR1_RNE (1 << 1) /* receive FIFO not empty */
59 #define UTSR1_TNF (1 << 2) /* transmit FIFO not full */
60 #define UTSR1_PRE (1 << 3) /* parity error */
61 #define UTSR1_FRE (1 << 4) /* framing error */
62 #define UTSR1_ROR (1 << 5) /* receiver overrun */
65 #define HSCR0_ITR 0x00000001 /* IrDA Transmission Rate */
66 #define HSCR0_UART (HSCR0_ITR*0) /* UART mode (115.2 kb/s if IrDA) */
67 #define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */
69 /* (HP-SIR) modulation Enable */
70 #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */
71 #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */
72 #define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */
73 #define UTCR4_LPM 0x00000002 /* Low-Power Mode */
74 #define UTCR4_Z3_16Bit (UTCR4_LPM*0) /* Zero pulse = 3/16 Bit time */
75 #define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */
78 #define UTSR1_ERROR_MASK 0x38
80 #define SDLCBASE 0x80020060
81 #define UART1BASE 0x80010000
82 #define UART2BASE 0x80030000
83 #define UART3BASE 0x80050000
85 #define UART1_UTCR0 (UART1BASE + UTCR0)
86 #define UART1_UTCR1 (UART1BASE + UTCR1)
87 #define UART1_UTCR2 (UART1BASE + UTCR2)
88 #define UART1_UTCR3 (UART1BASE + UTCR3)
89 #define UART1_UTDR (UART1BASE + UTDR)
90 #define UART1_UTSR0 (UART1BASE + UTSR0)
91 #define UART1_UTSR1 (UART1BASE + UTSR1)
93 #define UART2_UTCR0 (UART2BASE + UTCR0)
94 #define UART2_UTCR1 (UART2BASE + UTCR1)
95 #define UART2_UTCR2 (UART2BASE + UTCR2)
96 #define UART2_UTCR3 (UART2BASE + UTCR3)
97 /* the IR uart has an extra control register */
98 #define UART2_UTCR4 (UART2BASE + UTCR4)
99 #define UART2_UTDR (UART2BASE + UTDR)
100 #define UART2_UTSR0 (UART2BASE + UTSR0)
101 #define UART2_UTSR1 (UART2BASE + UTSR1)
103 #define UART3_UTCR0 (UART3BASE + UTCR0)
104 #define UART3_UTCR1 (UART3BASE + UTCR1)
105 #define UART3_UTCR2 (UART3BASE + UTCR2)
106 #define UART3_UTCR3 (UART3BASE + UTCR3)
107 #define UART3_UTDR (UART3BASE + UTDR)
108 #define UART3_UTSR0 (UART3BASE + UTSR0)
109 #define UART3_UTSR1 (UART3BASE + UTSR1)
113 * Operating System (OS) timer control registers
116 * OSMR0 Operating System (OS) timer Match Register 0
118 * OSMR1 Operating System (OS) timer Match Register 1
120 * OSMR2 Operating System (OS) timer Match Register 2
122 * OSMR3 Operating System (OS) timer Match Register 3
124 * OSCR Operating System (OS) timer Counter Register
126 * OSSR Operating System (OS) timer Status Register
128 * OWER Operating System (OS) timer Watch-dog Enable Register
130 * OIER Operating System (OS) timer Interrupt Enable Register
134 #define OSMR0 *(long*)(0x90000000) /* OS timer Match Reg. 0 */
135 #define OSMR1 *(long*)(0x90000004) /* OS timer Match Reg. 1 */
136 #define OSMR2 *(long*)(0x90000008) /* OS timer Match Reg. 2 */
137 #define OSMR3 *(long*)(0x9000000c) /* OS timer Match Reg. 3 */
138 #define OSCR *(volatile long*)(0x90000010) /* OS timer Counter Reg. */
139 #define OSSR *(volatile long*)(0x90000014 ) /* OS timer Status Reg. */
140 #define OWER *(volatile long*)(0x90000018 ) /* OS timer Watch-dog Enable Reg. */
141 #define OIER *(volatile long*)(0x9000001C ) /* OS timer Interrupt Enable Reg. */
145 * DRAM Configuration values
149 #define DRAM_CONFIGURATION_BASE 0xA0000000
151 #define MDCNFG 0x00 /* must be initialized */
152 #define MDCAS00 0x04 /* must be initialized */
153 #define MDCAS01 0x08 /* must be initialized */
154 #define MDCAS02 0x0c /* must be initialized */
156 #define MSC0 0x10 /* must be initialized */
157 #define MSC1 0x14 /* must be initialized */
158 #define MECR 0x18 /* should be initialized */
159 #define MDREFR 0x1c /* must be initialized */
161 #define MDCAS20 0x20 /* OK not to initialize this register, because the enable bits are cleared on reset */
162 #define MDCAS21 0x24 /* OK not to initialize this register, because the enable bits are cleared on reset */
163 #define MDCAS22 0x28 /* OK not to initialize this register, because the enable bits are cleared on reset */
165 #define MSC2 0x2C /* must be initialized */
167 #define SMCNFG 0x30 /* should be initialized */
169 #define ABS_MDCNFG *(volatile unsigned long*)(((char*)DRAM_CONFIGURATION_BASE)+MDCNFG)
170 #define ABS_MSC0 *(volatile unsigned long*)(((char*)DRAM_CONFIGURATION_BASE)+MSC0)
171 #define ABS_MSC1 *(volatile unsigned long*)(((char*)DRAM_CONFIGURATION_BASE)+MSC1)
172 #define ABS_MSC2 *(volatile unsigned long*)(((char*)DRAM_CONFIGURATION_BASE)+MSC2)
174 #define MDCNFG_BANK0_ENABLE (1 << 0)
175 #define MDCNFG_BANK1_ENABLE (1 << 1)
176 #define MDCNFG_DTIM0_SDRAM (1 << 2)
177 #define MDCNFG_DWID0_32B (0 << 3)
178 #define MDCNFG_DWID0_16B (1 << 3)
179 #define MDCNFG_DRAC0(n_) (((n_) & 7) << 4)
180 #define MDCNFG_TRP0(n_) (((n_) & 0xF) << 8)
181 #define MDCNFG_TDL0(n_) (((n_) & 3) << 12)
182 #define MDCNFG_TWR0(n_) (((n_) & 3) << 14)
184 /* DRAM Refresh Control Register (MDREFR) [1] 10.2.2 */
185 #define MDREFR_TRASR(n_) (((n_) & 0xF) << 0)
186 #define MDREFR_DRI(n_) (((n_) & 0xFFF) << 4)
187 #define MDREFR_E0PIN (1 << 16)
188 #define MDREFR_K0RUN (1 << 17)
189 #define MDREFR_K0DB2 (1 << 18)
190 #define MDREFR_E1PIN (1 << 20) /* SDRAM clock enable pin 1 (banks 0-1) */
191 #define MDREFR_K1RUN (1 << 21) /* SDRAM clock pin 1 run (banks 0-1) */
192 #define MDREFR_K1DB2 (1 << 22) /* SDRAM clock pin 1 divide-by-two (banks 0-1) */
193 #define MDREFR_K2RUN (1 << 25) /* SDRAM clock enable pin 2 (banks 2-3) */
194 #define MDREFR_K2DB2 (1 << 26) /* SDRAM clock pin 2 run (banks 2-3) */
195 #define MDREFR_EAPD (1 << 28) /* SDRAM clock pin 2 divide-by-two (banks 2-3) */
196 #define MDREFR_KAPD (1 << 29)
197 #define MDREFR_SLFRSH (1 << 31) /* SDRAM self refresh */
200 #define MSC_RT_ROMFLASH 0
201 #define MSC_RT_SRAM_012 1
202 #define MSC_RT_VARLAT_345 1
203 #define MSC_RT_BURST4 2
204 #define MSC_RT_BURST8 3
206 #define MSC_RBW32 (0 << 2)
207 #define MSC_RBW16 (1 << 2)
209 #define MSC_RDF(n_) (((n_)&0x1f)<<3)
210 #define MSC_RDN(n_) (((n_)&0x1f)<<8)
211 #define MSC_RRR(n_) (((n_)&0x7)<<13)
213 #define RCSR_REG 0x90030004
214 #define RCSR_HWR (1 << 0)
215 #define RCSR_SWR (1 << 1)
216 #define RCSR_WDR (1 << 2)
217 #define RCSR_SMR (1 << 3)
219 #define PSSR_REG 0x90020004
220 #define PSSR_SSS (1 << 0)
221 #define PSSR_BFS (1 << 1)
222 #define PSSR_VFS (1 << 2)
223 #define PSSR_DH (1 << 3)
224 #define PSSR_PH (1 << 4)
226 #define PSPR_REG 0x90020008
228 #define ICMR_REG 0x90050004
230 #define PPCR_REG 0x90020014
235 #define PPCR_103MHZ 3
236 #define PPCR_118MHZ 4
237 #define PPCR_132MHZ 5
238 #define PPCR_147MHZ 6
239 #define PPCR_162MHZ 7
240 #define PPCR_176MHZ 8
241 #define PPCR_191MHZ 9
242 #define PPCR_206MHZ 10
243 #define PPCR_221MHZ 11
246 #define PPC_TXD2 0x00004000 /* IPC Transmit Data 2 */
247 #define PPC_RXD2 0x00008000 /* IPC Receive Data 2 */
249 #define PPDR_REG 0x90060000 /* PPC Pin Direction Reg. */
250 #define PPDR_LFCLK 0x400
252 #define PPSR_REG 0x90060004 /* PPC Pin State Reg. */
255 #define GPIO_GPIO(Nb) /* GPIO [0..27] */ \
258 #if defined(CONFIG_MACH_IPAQ)
259 /* The EGPIO is a write only control register at physical address 0x49000000
260 * See the hardware spec for more details.
262 #define IPAQ_EGPIO 0x49000000
263 #define H3600_EGPIO_VIRT 0x49000000
264 #define H3800_ASIC_BASE 0x49000000
266 #define H3800_FLASH_VPP_ADDR (H3800_ASIC_BASE + _H3800_ASIC2_FlashWP_Base)
267 #define H3800_FLASH_VPP_ON 0xf1e1;
268 #define H3800_FLASH_VPP_OFF 0xf1e0;
269 // defines for our access to the 3800 asics. requires h3600_asic.h andh3600_gpio.h from linux.
270 #define H3800_ASIC1_GPIO_MASK_ADDR (H3800_ASIC_BASE + _H3800_ASIC1_GPIO_Base + _H3800_ASIC1_GPIO_Mask)
271 #define H3800_ASIC1_GPIO_DIR_ADDR (H3800_ASIC_BASE + _H3800_ASIC1_GPIO_Base + _H3800_ASIC1_GPIO_Direction)
272 #define H3800_ASIC1_GPIO_OUT_ADDR (H3800_ASIC_BASE + _H3800_ASIC1_GPIO_Base + _H3800_ASIC1_GPIO_Out)
273 #define _H3800_ASIC2_KPIO_Base 0x0200
274 #define _H3800_ASIC2_KPIO_Data 0x0014 /* R/W, 16 bits */
275 #define _H3800_ASIC2_KPIO_Alternate 0x003c /* R/W, 6 bits */
276 #define H3800_ASIC2_KPIO_ADDR (H3800_ASIC_BASE + _H3800_ASIC2_KPIO_Base + _H3800_ASIC2_KPIO_Data)
277 #define H3800_ASIC1_GPIO_MASK_INIT 0x7fff
278 #define H3800_ASIC1_GPIO_DIR_INIT 0x7fff
279 #define H3800_ASIC1_GPIO_OUT_INIT 0x2405
281 #include "ipaq-egpio.h"
285 #if defined(CONFIG_MACH_ASSABET) || defined(CONFIG_NEPONSET)
287 #define ASSABET_BCR 0x12000000
288 #define BCR_CF_PWR (1 << 0)
289 #define BCR_CF_RST (1 << 1)
290 #define BCR_SOFT_RST (1 << 2)
291 #define BCR_IRDA_FSEL (1 << 3)
292 #define BCR_CF_BUS_ON (1 << 7)
293 #define BCR_RS232EN (1 << 12)
296 #if defined(CONFIG_MACH_JORNADA56X) || defined(CONFIG_MACH_IPAQ)
297 #define JORNADA56X_ASIC_BASE_PHYSICAL 0x40000000
299 #define JORNADA_E_GPIO_BASE_PHYSICAL(A) (JORNADA56X_ASIC_BASE_PHYSICAL+0x700 + (A * 4))
301 #define JORNADA_E_GPIO_BASE_PHYSICAL(A) (*(long*)(JORNADA56X_ASIC_BASE_PHYSICAL+0x700 + (A * 4)))
303 #define JORNADA_GPDPSR_PHYSICAL JORNADA_E_GPIO_BASE_PHYSICAL(24)
304 #define JORNADA_GPDPCR_PHYSICAL JORNADA_E_GPIO_BASE_PHYSICAL(25)
305 #define JORNADA_GPDPLR_PHYSICAL JORNADA_E_GPIO_BASE_PHYSICAL(26)
306 #define JORNADA_GPDPDR_PHYSICAL JORNADA_E_GPIO_BASE_PHYSICAL(27)
307 #define JORNADA_RS232_ON (1 << 1) /* ASIC GPIO D */
309 #define JORNADA_ASIC_RESET (1 << 20) /* SA-1110 GPIO */
313 #if defined(CONFIG_MACH_SKIFF)
314 #define GPIO_BASE (0x41800000)
316 #define GPIO_BASE (0x90040000)
320 #define GPIO_GPLR_OFF (0)
321 #define GPIO_GPDR_OFF (4)
322 #define GPIO_GPSR_OFF (8)
323 #define GPIO_GPCR_OFF (0xc)
324 #define GPIO_GRER_OFF (0x10)
325 #define GPIO_GFER_OFF (0x14)
326 #define GPIO_GEDR_OFF (0x18)
327 #define GPIO_GAFR_OFF (0x1c)
330 #define GPIO_SET(off, bits) \
331 ((*((volatile unsigned long *)(((char*)GPIO_BASE)+(off))))|=(bits))
333 #define GPIO_CLR(off, bits) \
334 ((*((volatile unsigned long *)(((char*)GPIO_BASE)+(off))))&=~(bits))
336 #define GPIO_READ(off) \
337 (*((volatile unsigned long *)(((char*)GPIO_BASE)+(off))))
339 #define GPIO_WRITE(off, v) \
340 ((*((volatile unsigned long *)(((char*)GPIO_BASE)+(off)))) = (v))
342 #define GPIO_GAFR_LCD_BITS (0xff << 2)
343 #define GPIO_GPDR_LCD_BITS (0xff << 2)
345 #define GPIO_GPLR_READ() GPIO_READ(GPIO_GPLR_OFF)
346 #define GPIO_GPDR_READ() GPIO_READ(GPIO_GPDR_OFF)
347 #define GPIO_GPSR_READ() GPIO_READ(GPIO_GPSR_OFF)
348 #define GPIO_GPCR_READ() GPIO_READ(GPIO_GPCR_OFF)
349 #define GPIO_GRER_READ() GPIO_READ(GPIO_GRER_OFF)
350 #define GPIO_GFER_READ() GPIO_READ(GPIO_GFER_OFF)
351 #define GPIO_GEDR_READ() GPIO_READ(GPIO_GEDR_OFF)
352 #define GPIO_GAFR_READ() GPIO_READ(GPIO_GAFR_OFF)
354 #define GPIO_GPLR_WRITE(v) GPIO_WRITE(GPIO_GPLR_OFF,v)
355 #define GPIO_GPDR_WRITE(v) GPIO_WRITE(GPIO_GPDR_OFF,v)
356 #define GPIO_GPSR_WRITE(v) GPIO_WRITE(GPIO_GPSR_OFF,v)
357 #define GPIO_GPCR_WRITE(v) GPIO_WRITE(GPIO_GPCR_OFF,v)
358 #define GPIO_GRER_WRITE(v) GPIO_WRITE(GPIO_GRER_OFF,v)
359 #define GPIO_GFER_WRITE(v) GPIO_WRITE(GPIO_GFER_OFF,v)
360 #define GPIO_GEDR_WRITE(v) GPIO_WRITE(GPIO_GEDR_OFF,v)
361 #define GPIO_GAFR_WRITE(v) GPIO_WRITE(GPIO_GAFR_OFF,v)
363 #define GPIO_GPLR_SET(v) GPIO_SET(GPIO_GPLR_OFF,v)
364 #define GPIO_GPDR_SET(v) GPIO_SET(GPIO_GPDR_OFF,v)
365 #define GPIO_GPSR_SET(v) GPIO_SET(GPIO_GPSR_OFF,v)
366 #define GPIO_GPCR_SET(v) GPIO_SET(GPIO_GPCR_OFF,v)
367 #define GPIO_GRER_SET(v) GPIO_SET(GPIO_GRER_OFF,v)
368 #define GPIO_GFER_SET(v) GPIO_SET(GPIO_GFER_OFF,v)
369 #define GPIO_GEDR_SET(v) GPIO_SET(GPIO_GEDR_OFF,v)
370 #define GPIO_GAFR_SET(v) GPIO_SET(GPIO_GAFR_OFF,v)
372 #define GPIO_GPLR_CLR(v) GPIO_CLR(GPIO_GPLR_OFF,v)
373 #define GPIO_GPDR_CLR(v) GPIO_CLR(GPIO_GPDR_OFF,v)
374 #define GPIO_GPSR_CLR(v) GPIO_CLR(GPIO_GPSR_OFF,v)
375 #define GPIO_GPCR_CLR(v) GPIO_CLR(GPIO_GPCR_OFF,v)
376 #define GPIO_GRER_CLR(v) GPIO_CLR(GPIO_GRER_OFF,v)
377 #define GPIO_GFER_CLR(v) GPIO_CLR(GPIO_GFER_OFF,v)
378 #define GPIO_GEDR_CLR(v) GPIO_CLR(GPIO_GEDR_OFF,v)
379 #define GPIO_GAFR_CLR(v) GPIO_CLR(GPIO_GAFR_OFF,v)
381 #define GPIO_LDD8 (1 << 2)
382 #define GPIO_LDD9 (1 << 3)
383 #define GPIO_LDD10 (1 << 4)
384 #define GPIO_LDD11 (1 << 5)
385 #define GPIO_LDD12 (1 << 6)
386 #define GPIO_LDD13 (1 << 7)
387 #define GPIO_LDD14 (1 << 8)
388 #define GPIO_LDD15 (1 << 9)
390 #define GAFR *(volatile unsigned long*)(((char*)GPIO_BASE)+(GPIO_GAFR_OFF))
391 #define GPCR *(volatile unsigned long*)(((char*)GPIO_BASE)+(GPIO_GPCR_OFF))
392 #define GPDR *(volatile unsigned long*)(((char*)GPIO_BASE)+(GPIO_GPDR_OFF))
393 #define GPLR *(volatile unsigned long*)(((char*)GPIO_BASE)+(GPIO_GPLR_OFF))
394 #define GPSR *(volatile unsigned long*)(((char*)GPIO_BASE)+(GPIO_GPSR_OFF))
397 * power management reggies
400 #define PMCR 0x90020000 /* Power manager control register */
401 #define PSSR 0x90020004 /* Power manager sleep status register */
402 #define PSPR 0x90020008 /* Power manager scratch pad register */
403 #define PWER 0x9002000C /* Power manager wake-up enable register */
404 #define PCFR 0x90020010 /* Power manager general configuration reg */
405 #define PCFR_OPDE (1<<0) /* power down 3.6MHz osc */
406 #define PCFR_FP (1<<1) /* float PCMCIA controls during sleep */
407 #define PCFR_FS (1<<2) /* float static chip selects during sleep */
408 #define PCFR_FO (1<<3) /* force 32KHz osc enable on */
410 #define PPCR 0x90020014 /* Power manager PLL configuration register */
411 #define PGSR 0x90020018 /* Power manager GPIO sleep state register */
412 #define POSR 0x9002001C /* Power manager oscillator status register */
415 #define RSRR_SWR (1<<0) /* software reset bit */
416 #define RSRR 0x90030000 /* Reset controller software reset register */
417 #define RCSR 0x90030004 /* Reset controller status register */
420 #define ICIP 0x90050000 /* interrupt controller IRQ pend reg */
421 #define ICFP 0x90050010 /* interrupt controller FIQ pend reg */
422 #define ICMR 0x90050004 /* interrupt controller mask reg */
423 #define ICLR 0x90050008 /* interrupt controller level reg */
424 #define ICCR 0x9005000C /* interrupt controller control reg */
426 #define RTC_BASE 0x90010000
427 #define RTAR_OFFSET 0 /* RTC alarm reg */
428 #define RTAR (RTC_BASE + RTAR_OFFSET)
429 #define RCNR_OFFSET 4 /* RTC count reg */
430 #define RCNR (RTC_BASE + RCNR_OFFSET)
431 #define RTTR_OFFSET 8 /* RTC timer trim reg */
432 #define RTTR (RTC_BASE + RTTR_OFFSET)
433 #define RTSR_OFFSET 0x10 /* RTC status reg */
434 #define RTSR (RTC_BASE + RTSR_OFFSET)
435 #define UART2_HSCR0_OFFSET 0x80040060
436 #define UART2_HSCR0 (RTC_BASE + UART2_HSCR0_OFFSET)
439 #endif /* SA1100_H_INCLUDED */
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