1 INTERFACE[ia32 || amd64]:
10 IMPLEMENTATION[ia32 || amd64]:
12 PUBLIC static inline ALWAYS_INLINE
14 Mem_unit::make_coherent_to_pou(void const *)
17 /** Flush the whole TLB.
19 PUBLIC static inline ALWAYS_INLINE
24 __asm__ __volatile__ ("mov %%cr3,%0; mov %0,%%cr3 " : "=r"(dummy) : : "memory");
28 /** Flush TLB at virtual address.
30 PUBLIC static inline ALWAYS_INLINE
32 Mem_unit::tlb_flush(Address addr)
34 __asm__ __volatile__ ("invlpg %0" : : "m" (*(char*)addr) : "memory");
37 PUBLIC static inline ALWAYS_INLINE
39 Mem_unit::clean_dcache()
40 { asm volatile ("wbinvd"); }
42 PUBLIC static inline ALWAYS_INLINE
44 Mem_unit::clean_dcache(void const *addr)
45 { asm volatile ("clflush %0" : : "m" (*(char const *)addr)); }
47 PUBLIC static inline ALWAYS_INLINE
49 Mem_unit::clean_dcache(void const *start, void const *end)
51 enum { Cl_size = 64 };
52 if (((Address)end) - ((Address)start) >= 8192)
55 for (char const *s = (char const *)start; s < (char const *)end;