kernel/fiasco/src/kern/arm/kernel_thread-arm.cpp

   1 IMPLEMENTATION [arm]:
   2
   3 #include "config.h"
   4
   5 IMPLEMENT inline
   6 void
   7 Kernel_thread::free_initcall_section()
   8 {
   9   //memset( &_initcall_start, 0, &_initcall_end - &_initcall_start );
  10 }
  11
  12 IMPLEMENT FIASCO_INIT
  13 void
  14 Kernel_thread::bootstrap_arch()
  15 {
  16   Proc::sti();
  17   boot_app_cpus();
  18   Proc::cli();
  19 }
  20
  21 //--------------------------------------------------------------------------
  22 IMPLEMENTATION [!mp]:
  23
  24 PUBLIC
  25 static inline void
  26 Kernel_thread::boot_app_cpus()
  27 {}
  28
  29
  30 //--------------------------------------------------------------------------
  31 IMPLEMENTATION [mp]:
  32
  33 #include "io.h"
  34 #include "platform_control.h"
  35 #include "outer_cache.h"
  36 #include "paging.h"
  37 #include <cstdio>
  38
  39 PUBLIC
  40 static void
  41 Kernel_thread::boot_app_cpus()
  42 {
  43   if (Config::Max_num_cpus <= 1)
  44     return;
  45
  46   extern char _tramp_mp_entry[];
  47   extern volatile Mword _tramp_mp_startup_cp15_c1;
  48   extern volatile Mword _tramp_mp_startup_pdbr;
  49   extern volatile Mword _tramp_mp_startup_dcr;
  50   extern volatile Mword _tramp_mp_startup_ttbcr;
  51   extern volatile Mword _tramp_mp_startup_mair0;
  52   extern volatile Mword _tramp_mp_startup_mair1;
  53
  54   if (Scu::Available)
  55     {
  56       unsigned num_ap_cpus = Cpu::scu->config() & 3;
  57       printf("Number of CPUs: %d\n", num_ap_cpus + 1);
  58     }
  59
  60   _tramp_mp_startup_cp15_c1 = Config::Cache_enabled
  61                               ? Cpu::Cp15_c1_cache_enabled : Cpu::Cp15_c1_cache_disabled;
  62   _tramp_mp_startup_pdbr
  63     = Kmem_space::kdir()->virt_to_phys((Address)Kmem_space::kdir()) | Page::Ttbr_bits;
  64   _tramp_mp_startup_ttbcr   = Page::Ttbcr_bits;
  65   _tramp_mp_startup_mair0   = Page::Mair0_prrr_bits;
  66   _tramp_mp_startup_mair1   = Page::Mair1_nmrr_bits;
  67   _tramp_mp_startup_dcr     = 0x55555555;
  68
  69   __asm__ __volatile__ ("" : : : "memory");
  70   Mem_unit::clean_dcache();
  71
  72   Outer_cache::clean(Kmem_space::kdir()->virt_to_phys((Address)&_tramp_mp_startup_cp15_c1));
  73   Outer_cache::clean(Kmem_space::kdir()->virt_to_phys((Address)&_tramp_mp_startup_pdbr));
  74   Outer_cache::clean(Kmem_space::kdir()->virt_to_phys((Address)&_tramp_mp_startup_dcr));
  75   Outer_cache::clean(Kmem_space::kdir()->virt_to_phys((Address)&_tramp_mp_startup_ttbcr));
  76   Outer_cache::clean(Kmem_space::kdir()->virt_to_phys((Address)&_tramp_mp_startup_mair0));
  77
  78   Platform_control::boot_ap_cpus(Kmem_space::kdir()->virt_to_phys((Address)_tramp_mp_entry));
  79 }
  80
  81 //--------------------------------------------------------------------------
  82 IMPLEMENTATION [arm && generic_tickless_idle]:
  83
  84 #include "mem_unit.h"
  85 #include "processor.h"
  86
  87 PROTECTED inline NEEDS["processor.h", "mem_unit.h"]
  88 void
  89 Kernel_thread::arch_tickless_idle(unsigned)
  90 {
  91   Mem_unit::tlb_flush();
  92   Proc::halt();
  93 }
  94
  95 PROTECTED inline NEEDS["processor.h"]
  96 void
  97 Kernel_thread::arch_idle(unsigned)
  98 { Proc::halt(); }
  99