1 INTERFACE [arm && pic_gic && (imx51 || imx53 || imx6)]:
6 INTERFACE [arm && pic_gic && (imx51 | imx53)]:
13 INTERFACE [arm && pic_gic && imx6]:
20 // ------------------------------------------------------------------------
21 IMPLEMENTATION [arm && pic_gic && (imx51 || imx53 || imx6)]:
23 #include "irq_mgr_multi_chip.h"
26 PUBLIC static FIASCO_INIT
30 typedef Irq_mgr_multi_chip<Gic_sz> M;
32 M *m = new Boot_object<M>(1);
34 gic.construct(Kmem::mmio_remap(Mem_layout::Gic_cpu_phys_base),
35 Kmem::mmio_remap(Mem_layout::Gic_dist_phys_base));
36 m->add_chip(0, gic, gic->nr_irqs());
41 // ------------------------------------------------------------------------
42 IMPLEMENTATION [arm && pic_gic && mp && imx6]:
45 void Pic::init_ap(Cpu_number, bool resume)