7 //-----------------------------------------------------------------------------
8 INTERFACE [arm && armv5]:
15 typedef Unsigned32 Attribs;
19 KERN_RW = 0x0400, ///< User No access
20 USER_RO = 0x0000, ///< User Read only
21 USER_RW = 0x0c00, ///< User Read/Write
26 NONCACHEABLE = 0x00, ///< Caching is off
27 CACHEABLE = 0x0c, ///< Cache is enabled
29 // The next are ARM specific
30 WRITETHROUGH = 0x08, ///< Write through cached
31 BUFFERED = 0x04, ///< Write buffer enabled
42 //----------------------------------------------------------------------------
43 INTERFACE [arm && (armv6 || armv7)]:
49 typedef Unsigned32 Attribs;
54 KERN_RW = 0x0010, ///< User No access
55 USER_RO = 0x0230, ///< User Read only
56 USER_RW = 0x0030, ///< User Read/Write
61 NONCACHEABLE = 0x000, ///< Caching is off
62 CACHEABLE = 0x144, ///< Cache is enabled
64 // The next are ARM specific
65 WRITETHROUGH = 0x08, ///< Write through cached
66 BUFFERED = 0x04, ///< Write buffer enabled
74 //-----------------------------------------------------------------------------
77 #include "mapped_alloc.h"
78 #include "ptab_base.h"
95 Raw raw() const { return _raw; }
96 Address addr() const { return _raw & (~0UL << 12); }
102 class Pd_entry : public Pte_base
105 enum { Page_shift = Config::SUPERPAGE_SHIFT };
106 Mword leaf() const { return (_raw & Type_mask) == Type_1MB; }
107 void set(Address p, bool intermed, bool present, unsigned long attrs = 0)
109 _raw = (p & (~0UL << Page_shift))
110 | (present ? (intermed ? Type_coarse_pt : Type_1MB) : 0) | attrs;
114 class Pt_entry : public Pte_base
117 enum { Page_shift = Config::PAGE_SHIFT };
118 Mword leaf() const { return true; }
119 void set(Address p, bool, bool present, unsigned long attrs = 0)
121 _raw = (p & (~0UL << Page_shift)) | (present ? Type_4KB : 0) | attrs;
125 typedef Ptab::List< Ptab::Traits< Pd_entry, 20, 12, true>,
126 Ptab::Traits< Pt_entry, 12, 8, true> > Ptab_traits;
128 typedef Ptab_traits Ptab_traits_vpn;
129 typedef Ptab::Page_addr_wrap<Virt_addr, 0> Ptab_va_vpn;
131 //---------------------------------------------------------------------------
132 IMPLEMENTATION [arm && armv5]:
135 Mword PF::is_alignment_error(Mword error)
136 { return (error & 0xf0000d) == 0x400001; }
138 //---------------------------------------------------------------------------
139 IMPLEMENTATION [arm && (armv6 || armv7)]:
142 Mword PF::is_alignment_error(Mword error)
143 { return (error & 0xf0040f) == 0x400001; }
145 //---------------------------------------------------------------------------
146 IMPLEMENTATION [arm]:
155 Pte_base::valid() const
161 Mword PF::is_translation_error( Mword error )
163 return (error & 0x0d/*FSR_STATUS_MASK*/) == 0x05/*FSR_TRANSL*/;
167 Mword PF::is_usermode_error( Mword error )
169 return (error & 0x00010000/*PF_USERMODE*/);
173 Mword PF::is_read_error( Mword error )
175 return !(error & (1UL << 11));
179 Mword PF::addr_to_msgword0( Address pfa, Mword error )
182 if(is_translation_error( error ))
184 if(!is_read_error(error))