1 INTERFACE [arm && omap3]:
12 Multi_irq_pending = 0,
14 No_irq_pending = 1023,
19 INTCPS_SYSCONFIG = Kmem::Intc_map_base + 0x010,
20 INTCPS_SYSSTATUS = Kmem::Intc_map_base + 0x014,
21 INTCPS_CONTROL = Kmem::Intc_map_base + 0x048,
22 INTCPS_TRESHOLD = Kmem::Intc_map_base + 0x068,
23 INTCPS_ITRn_base = Kmem::Intc_map_base + 0x080,
24 INTCPS_MIRn_base = Kmem::Intc_map_base + 0x084,
25 INTCPS_MIR_CLEARn_base = Kmem::Intc_map_base + 0x088,
26 INTCPS_MIR_SETn_base = Kmem::Intc_map_base + 0x08c,
27 INTCPS_ISR_SETn_base = Kmem::Intc_map_base + 0x090,
28 INTCPS_ISR_CLEARn_base = Kmem::Intc_map_base + 0x094,
29 INTCPS_PENDING_IRQn_base = Kmem::Intc_map_base + 0x098,
30 INTCPS_ILRm_base = Kmem::Intc_map_base + 0x100,
34 //-------------------------------------------------------------------
35 IMPLEMENTATION [arm && omap3]:
40 #include "boot_info.h"
42 #include "initcalls.h"
45 #include "irq_chip_generic.h"
50 class Omap3_pin : public Irq_pin
53 explicit Omap3_pin(unsigned irq) { payload()[0] = irq; }
54 unsigned irq() const { return payload()[0]; }
59 Omap3_pin::unbind_irq()
63 Irq_chip::hw_chip->free(Irq::self(this), irq());
64 replace<Sw_irq_pin>();
71 assert (cpu_lock.test());
72 Io::write<Mword>(1 << (irq() & 31), Pic::INTCPS_MIR_SETn_base + (irq() & 0xe0));
77 Omap3_pin::do_mask_and_ack()
79 assert (cpu_lock.test());
81 Io::write<Mword>(1 << (irq() & 31), Pic::INTCPS_MIR_SETn_base + (irq() & 0xe0));
82 Io::write<Mword>(1, Pic::INTCPS_CONTROL);
89 Io::write<Mword>(1, Pic::INTCPS_CONTROL);
95 Omap3_pin::do_unmask()
97 assert (cpu_lock.test());
98 Io::write<Mword>(1 << (irq() & 31), Pic::INTCPS_MIR_CLEARn_base + (irq() & 0xe0));
104 Omap3_pin::check_debug_irq()
106 return !Vkey::check_(irq());
111 Omap3_pin::set_cpu(unsigned)
118 class Irq_chip_arm_x : public Irq_chip_gen
124 Irq_chip_arm_x::setup(Irq_base *irq, unsigned irqnum)
126 if (irqnum < Config::Max_num_dirqs)
127 irq->pin()->replace<Omap3_pin>(irqnum);
131 IMPLEMENT FIASCO_INIT
134 static Irq_chip_arm_x _ia;
135 Irq_chip::hw_chip = &_ia;
138 Io::write<Mword>(2, INTCPS_SYSCONFIG);
139 while (!Io::read<Mword>(INTCPS_SYSSTATUS))
143 Io::write<Mword>(1, INTCPS_SYSCONFIG);
146 Io::write<Mword>(0xff, INTCPS_TRESHOLD);
148 // set priority for each interrupt line, lets take 0x20
149 // setting bit0 to 0 means IRQ (1 would mean FIQ)
150 for (int m = 0; m < Config::Max_num_dirqs; ++m)
151 Io::write<Mword>(0x20 << 2, INTCPS_ILRm_base + (4 * m));
153 // mask all interrupts
154 for (int n = 0; n < 3; ++n)
155 Io::write<Mword>(0xffffffff, INTCPS_MIR_SETn_base + 0x20 * n);
159 Pic::Status Pic::disable_all_save()
163 void Pic::restore_all( Status /*s*/ )
166 PUBLIC static inline NEEDS["io.h",<cstdio>]
167 Unsigned32 Pic::pending()
169 for (int n = 0; n < (Config::Max_num_dirqs >> 5); ++n)
171 unsigned long x = Io::read<Mword>(INTCPS_PENDING_IRQn_base + 0x20 * n);
172 for (int i = 0; i < 32; ++i)
182 Mword Pic::is_pending(Mword &irqs, Mword irq)
183 { return irqs == irq; }
185 //---------------------------------------------------------------------------
186 IMPLEMENTATION [debug && omap3]:
190 Omap3_pin::pin_type() const
191 { return "HW OMAP3 IRQ"; }