kernel/fiasco/src/kern/arm/bsp/realview/mem_layout-arm-realview.cpp

   1 INTERFACE [arm && realview]: //---------------------------------------------
   2
   3 #include "globalconfig.h"
   4
   5 EXTENSION class Mem_layout
   6 {
   7 public:
   8   enum Virt_layout_realview {
   9     Devices0_map_base      = Registers_map_start,
  10       System_regs_map_base = Devices0_map_base,
  11       System_ctrl_map_base = Devices0_map_base + 0x00001000,
  12       Uart0_map_base       = Devices0_map_base + 0x00009000,
  13       Uart1_map_base       = Devices0_map_base + 0x0000a000,
  14       Uart2_map_base       = Devices0_map_base + 0x0000b000,
  15       Uart3_map_base       = Devices0_map_base + 0x0000c000,
  16       Timer0_map_base      = Devices0_map_base + 0x00011000,
  17       Timer1_map_base      = Devices0_map_base + 0x00011020,
  18       Timer2_map_base      = Devices0_map_base + 0x00012000,
  19       Timer3_map_base      = Devices0_map_base + 0x00012020,
  20       Uart_base            = Uart0_map_base,
  21
  22     Devices1_map_base      = Registers_map_start + 0x00100000,
  23     Devices2_map_base      = Registers_map_start + 0x00200000,
  24   };
  25
  26   enum Phys_layout_realview {
  27     Devices0_phys_base   = 0x10000000,
  28     System_regs_phys_base= Devices0_phys_base,
  29     System_ctrl_phys_base= Devices0_phys_base + 0x00001000,
  30     Uart0_phys_base      = Devices0_phys_base + 0x00009000,
  31     Timer0_1_phys_base   = Devices0_phys_base + 0x00011000,
  32     Timer2_3_phys_base   = Devices0_phys_base + 0x00012000,
  33     Sdram_phys_base      = CONFIG_PF_REALVIEW_RAM_PHYS_BASE,
  34
  35     Flush_area_phys_base = 0xe0000000,
  36   };
  37 };
  38
  39 // ------------------------------------------------------------------------
  40 INTERFACE [arm && realview && realview_eb && !(mpcore || armca9)]:
  41
  42 EXTENSION class Mem_layout
  43 {
  44 public:
  45   enum Virt_layout_realview_single {
  46     Gic_cpu_map_base    = Devices0_map_base  + 0x00040000,
  47     Gic_dist_map_base   = Gic_cpu_map_base + 0x00001000,
  48   };
  49
  50   enum Phys_layout_realview_single {
  51     Gic_cpu_phys_base   = Devices0_phys_base  + 0x00040000,
  52     Gic_dist_phys_base  = Gic_cpu_phys_base + 0x00001000,
  53   };
  54 };
  55
  56 // ------------------------------------------------------------------------
  57 INTERFACE [arm && realview && realview_eb && (mpcore || armca9)]:
  58
  59 EXTENSION class Mem_layout
  60 {
  61 public:
  62   enum Virt_layout_realview_mp {
  63     Mp_scu_map_base      = Devices1_map_base,
  64     Gic_cpu_map_base     = Devices1_map_base + 0x00000100,
  65     Gic_dist_map_base    = Devices1_map_base + 0x00001000,
  66     L220_map_base        = Devices1_map_base + 0x00002000,
  67
  68     Gic1_cpu_map_base    = Devices0_map_base + 0x00040000,
  69     Gic1_dist_map_base   = Devices0_map_base + 0x00041000,
  70   };
  71
  72   enum Phys_layout_realview_mp {
  73     Mp_scu_phys_base     = 0x1f000000,
  74     Gic_cpu_phys_base    = Mp_scu_phys_base  + 0x00000100,
  75     Gic_dist_phys_base   = Mp_scu_phys_base  + 0x00001000,
  76     L220_phys_base       = Mp_scu_phys_base  + 0x00002000,
  77
  78     Gic1_cpu_phys_base   = Devices0_phys_base + 0x00040000,
  79     Gic1_dist_phys_base  = Devices0_phys_base + 0x00041000,
  80     Gic2_cpu_phys_base   = Devices0_phys_base + 0x00050000,
  81     Gic2_dist_phys_base  = Devices0_phys_base + 0x00051000,
  82     Gic3_cpu_phys_base   = Devices0_phys_base + 0x00060000,
  83     Gic3_dist_phys_base  = Devices0_phys_base + 0x00061000,
  84     Gic4_cpu_phys_base   = Devices0_phys_base + 0x00070000,
  85     Gic4_dist_phys_base  = Devices0_phys_base + 0x00071000,
  86   };
  87 };
  88
  89 // ------------------------------------------------------------------------
  90 INTERFACE [arm && realview && realview_pb11mp]:
  91
  92 EXTENSION class Mem_layout
  93 {
  94 public:
  95   enum Virt_layout_realview_pb11mp {
  96     Mp_scu_map_base      = Devices1_map_base,
  97     Gic_cpu_map_base     = Devices1_map_base + 0x00000100,
  98     Gic_dist_map_base    = Devices1_map_base + 0x00001000,
  99     L220_map_base        = Devices1_map_base + 0x00002000,
 100
 101     Gic1_cpu_map_base    = Devices2_map_base,
 102     Gic1_dist_map_base   = Devices2_map_base + 0x00001000,
 103   };
 104
 105   enum Phys_layout_realview_pb11mp {
 106     Devices1_phys_base   = 0x1f000000,
 107     Mp_scu_phys_base     = 0x1f000000,
 108     Gic_cpu_phys_base    = Mp_scu_phys_base + 0x00000100,
 109     Gic_dist_phys_base   = Mp_scu_phys_base + 0x00001000,
 110     L220_phys_base       = Mp_scu_phys_base + 0x00002000,
 111
 112     Devices2_phys_base   = 0x1e000000,
 113     Gic0_cpu_phys_base   = 0x1e000000,
 114     Gic0_dist_phys_base  = Gic0_cpu_phys_base + 0x00001000,
 115     Gic1_cpu_phys_base   = 0x1e010000,
 116     Gic1_dist_phys_base  = Gic1_cpu_phys_base + 0x00001000,
 117   };
 118 };
 119
 120 // ------------------------------------------------------------------------
 121 INTERFACE [arm && realview && realview_pbx]:
 122
 123 EXTENSION class Mem_layout
 124 {
 125 public:
 126   enum Virt_layout_realview_pbx {
 127     Mp_scu_map_base      = Devices1_map_base,
 128     Gic_cpu_map_base     = Devices1_map_base + 0x00000100,
 129     Gic_dist_map_base    = Devices1_map_base + 0x00001000,
 130     L220_map_base        = Devices1_map_base + 0x00002000,
 131
 132     Gic2_cpu_map_base    = Devices2_map_base + 0x00020000,
 133     Gic2_dist_map_base   = Devices2_map_base + 0x00021000,
 134     Gic3_cpu_map_base    = Devices2_map_base + 0x00030000,
 135     Gic3_dist_map_base   = Devices2_map_base + 0x00031000,
 136   };
 137
 138   enum Phys_layout_realview_pbx {
 139     Devices1_phys_base   = 0x1f000000,
 140     Mp_scu_phys_base     = 0x1f000000,
 141     Gic_cpu_phys_base    = Mp_scu_phys_base + 0x00000100,
 142     Gic_dist_phys_base   = Mp_scu_phys_base + 0x00001000,
 143     L220_phys_base       = Mp_scu_phys_base + 0x00002000,
 144
 145     Devices2_phys_base   = 0x1e000000,
 146     Gic2_cpu_phys_base   = 0x1e020000,
 147     Gic2_dist_phys_base  = Gic2_cpu_phys_base + 0x00001000,
 148     Gic3_cpu_phys_base   = 0x1e030000,
 149     Gic3_dist_phys_base  = Gic3_cpu_phys_base + 0x00001000,
 150   };
 151 };