kernel/fiasco/src/kern/arm/bsp/imx/timer-arm-imx_epit.cpp

   1 // --------------------------------------------------------------------------
   2 INTERFACE [arm && imx_epit]:
   3
   4 #include "kmem.h"
   5 #include "irq_chip.h"
   6
   7 EXTENSION class Timer
   8 {
   9 private:
  10   enum {
  11     EPITCR   = Kmem::Timer_map_base + 0x00,
  12     EPITSR   = Kmem::Timer_map_base + 0x04,
  13     EPITLR   = Kmem::Timer_map_base + 0x08,
  14     EPITCMPR = Kmem::Timer_map_base + 0x0c,
  15     EPITCNR  = Kmem::Timer_map_base + 0x10,
  16
  17     EPITCR_ENABLE                  = 1 << 0, // enable EPIT
  18     EPITCR_ENMOD                   = 1 << 1, // enable mode
  19     EPITCR_OCIEN                   = 1 << 2, // output compare irq enable
  20     EPITCR_RLD                     = 1 << 3, // reload
  21     EPITCR_SWR                     = 1 << 16, // software reset
  22     EPITCR_WAITEN                  = 1 << 19, // wait enabled
  23     EPITCR_CLKSRC_IPG_CLK          = 1 << 24,
  24     EPITCR_CLKSRC_IPG_CLK_HIGHFREQ = 2 << 24,
  25     EPITCR_CLKSRC_IPG_CLK_32K      = 3 << 24,
  26     EPITCR_PRESCALER_SHIFT         = 4,
  27     EPITCR_PRESCALER_MASK          = ((1 << 12) - 1) << EPITCR_PRESCALER_SHIFT,
  28
  29     EPITSR_OCIF = 1,
  30   };
  31 private:
  32   static Irq_base *irq;
  33 };
  34
  35 // ----------------------------------------------------------------------
  36 IMPLEMENTATION [arm && imx_epit]:
  37
  38 #include "config.h"
  39 #include "kip.h"
  40 #include "irq_chip.h"
  41 #include "irq_pin.h"
  42 #include "io.h"
  43
  44 #include <cstdio>
  45
  46 Irq_base *Timer::irq;
  47
  48 IMPLEMENT
  49 void Timer::init()
  50 {
  51   Io::write<Mword>(0, EPITCR); // Disable
  52   Io::write<Mword>(EPITCR_SWR, EPITCR);
  53   while (Io::read<Mword>(EPITCR) & EPITCR_SWR)
  54     ;
  55
  56   Io::write<Mword>(EPITSR_OCIF, EPITSR);
  57
  58   Io::write<Mword>(EPITCR_CLKSRC_IPG_CLK_32K
  59                    | (0 << EPITCR_PRESCALER_SHIFT)
  60                    | EPITCR_WAITEN
  61                    | EPITCR_RLD
  62                    | EPITCR_OCIEN
  63                    | EPITCR_ENMOD,
  64                    EPITCR);
  65
  66   Io::write<Mword>(0, EPITCMPR);
  67
  68   Io::write<Mword>(32, EPITLR);
  69
  70
  71   Irq_chip::hw_chip->reserve(Config::Scheduling_irq);
  72
  73   static Irq_base ib;
  74   Irq_chip::hw_chip->setup(&ib, Config::Scheduling_irq);
  75   irq = &ib;
  76
  77   Io::set<Mword>(EPITCR_ENABLE, EPITCR);
  78 }
  79
  80 static inline
  81 Unsigned64
  82 Timer::timer_to_us(Unsigned32 /*cr*/)
  83 { return 0; }
  84
  85 static inline
  86 Unsigned64
  87 Timer::us_to_timer(Unsigned64 us)
  88 { (void)us; return 0; }
  89
  90 IMPLEMENT inline NEEDS["io.h"]
  91 void Timer::acknowledge()
  92 {
  93   Io::write<Mword>(EPITSR_OCIF, EPITSR);
  94 }
  95
  96 IMPLEMENT inline NEEDS["irq_pin.h"]
  97 void Timer::enable()
  98 {
  99   irq->pin()->unmask();
 100 }
 101
 102 IMPLEMENT inline NEEDS["irq_pin.h"]
 103 void Timer::disable()
 104 {
 105   irq->pin()->mask();
 106 }
 107
 108 IMPLEMENT inline NEEDS["kip.h", "io.h", Timer::timer_to_us, Timer::us_to_timer]
 109 void
 110 Timer::update_one_shot(Unsigned64 /*wakeup*/)
 111 {
 112 }
 113
 114 IMPLEMENT inline NEEDS["config.h", "kip.h", "io.h", Timer::timer_to_us]
 115 Unsigned64
 116 Timer::system_clock()
 117 {
 118   if (Config::scheduler_one_shot)
 119     return 0;
 120   else
 121     return Kip::k()->clock;
 122 }
 123