1 // --------------------------------------------------------------------------
2 INTERFACE [arm && imx21]:
11 TCTL = Kmem::Timer_map_base + 0x00,
12 TPRER = Kmem::Timer_map_base + 0x04,
13 TCMP = Kmem::Timer_map_base + 0x08,
14 TCR = Kmem::Timer_map_base + 0x0c,
15 TCN = Kmem::Timer_map_base + 0x10,
16 TSTAT = Kmem::Timer_map_base + 0x14,
19 TCTL_CLKSOURCE_PERCLK1_TO_PRESCALER = 1 << 1,
20 TCTL_CLKSOURCE_32kHz = 1 << 3,
21 TCTL_COMP_EN = 1 << 4,
22 TCTL_SW_RESET = 1 << 15,
28 // ----------------------------------------------------------------------
29 IMPLEMENTATION [arm && imx21]:
44 Io::write<Mword>(0, TCTL); // Disable
45 Io::write<Mword>(TCTL_SW_RESET, TCTL); // reset timer
46 for (int i = 0; i < 10; ++i)
47 Io::read<Mword>(TCN); // docu says reset takes 5 cycles
49 Io::write<Mword>(TCTL_CLKSOURCE_32kHz | TCTL_COMP_EN, TCTL);
50 Io::write<Mword>(0, TPRER);
51 Io::write<Mword>(32, TCMP);
53 Irq_chip::hw_chip->reserve(Config::Scheduling_irq);
56 Irq_chip::hw_chip->setup(&ib, Config::Scheduling_irq);
59 Io::set<Mword>(TCTL_TEN, TCTL);
64 Timer::timer_to_us(Unsigned32 /*cr*/)
69 Timer::us_to_timer(Unsigned64 us)
70 { (void)us; return 0; }
72 IMPLEMENT inline NEEDS["io.h"]
73 void Timer::acknowledge()
75 Io::write<Mword>(1, TSTAT);
78 IMPLEMENT inline NEEDS["irq_pin.h"]
84 IMPLEMENT inline NEEDS["irq_pin.h"]
90 IMPLEMENT inline NEEDS["kip.h", "io.h", Timer::timer_to_us, Timer::us_to_timer]
92 Timer::update_one_shot(Unsigned64 /*wakeup*/)
96 IMPLEMENT inline NEEDS["config.h", "kip.h", "io.h", Timer::timer_to_us]
100 if (Config::scheduler_one_shot)
101 //return Kip::k()->clock + timer_to_us(Io::read<Unsigned32>(OSCR));
104 return Kip::k()->clock;