8 Status_mode_user = 0x10,
9 Status_mode_supervisor = 0x13,
10 Status_mode_mask = 0x1f,
12 Status_FIQ_disabled = 0x40,
13 Status_IRQ_disabled = 0x80,
14 Status_interrupts_disabled = Status_FIQ_disabled | Status_IRQ_disabled,
15 Status_interrupts_mask = 0xc0,
19 static unsigned cpu_id();
22 INTERFACE[arm && !tz]:
29 Cli_mask = Status_IRQ_disabled,
30 Sti_mask = Status_IRQ_disabled,
41 Cli_mask = Status_IRQ_disabled | Status_FIQ_disabled,
42 Sti_mask = Status_IRQ_disabled | Status_FIQ_disabled,
49 #include "std_macros.h"
51 IMPLEMENT static inline
52 Mword Proc::stack_pointer()
55 asm volatile ( "mov %0, sp \n" : "=r"(sp) );
59 IMPLEMENT static inline
60 void Proc::stack_pointer(Mword sp)
62 asm volatile ( "mov sp, %0 \n" : : "r"(sp) );
65 IMPLEMENT static inline
66 Mword Proc::program_counter()
68 register Mword pc asm ("pc");
72 IMPLEMENT static inline
75 asm volatile ( " mrs r6, cpsr \n"
78 : : "i" (Cli_mask) : "r6", "memory"
82 IMPLEMENT static inline
85 asm volatile ( " mrs r6, cpsr \n"
88 : : "i" (Sti_mask) : "r6", "memory"
92 IMPLEMENT static inline
93 Proc::Status Proc::cli_save()
96 asm volatile ( " mrs r6, cpsr \n"
100 : "=r"(ret) : "i" (Cli_mask) : "r6"
105 IMPLEMENT static inline
106 Proc::Status Proc::interrupts()
109 asm volatile (" mrs %0, cpsr \n"
112 return !(ret & Sti_mask);
115 IMPLEMENT static inline
116 void Proc::sti_restore(Status st)
118 asm volatile ( " tst %0, %1 \n"
124 : : "r"(st), "i" (Sti_mask) : "r6"
128 IMPLEMENT static inline
129 void Proc::irq_chance()
131 asm volatile ("nop; nop;" : : : "memory");
135 //----------------------------------------------------------------
136 IMPLEMENTATION[arm && !mp]:
138 IMPLEMENT static inline
139 unsigned Proc::cpu_id()
142 //----------------------------------------------------------------
143 IMPLEMENTATION[arm && mp]:
145 IMPLEMENT static inline
146 unsigned Proc::cpu_id()
149 __asm__("mrc p15, 0, %0, c0, c0, 5": "=r" (cpunum));
153 //----------------------------------------------------------------
154 IMPLEMENTATION[arm && (pxa || sa1100 || s3c2410)]:
156 IMPLEMENT static inline
160 IMPLEMENT static inline
164 //----------------------------------------------------------------
165 IMPLEMENTATION[arm && 926]:
167 IMPLEMENT static inline
172 IMPLEMENT static inline
175 Status f = cli_save();
176 asm volatile("mov r0, #0 \n\t"
177 "mrc p15, 0, r1, c1, c0, 0 @ Read control register \n\t"
178 "mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer \n\t"
179 "bic r2, r1, #1 << 12 \n\t"
180 "mcr p15, 0, r2, c1, c0, 0 @ Disable I cache \n\t"
181 "mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt \n\t"
182 "mcr 15, 0, r1, c1, c0, 0 @ Restore ICache enable \n\t"
184 "r0", "r1", "r2", "r3", "r4", "r5",
185 "r6", "r7", "r8", "r9", "r10", "r11",
186 "r12", "r13", "r14", "r15"
191 //----------------------------------------------------------------
192 IMPLEMENTATION[arm && arm1136]:
194 IMPLEMENT static inline
198 IMPLEMENT static inline
201 Status f = cli_save();
202 asm volatile("mcr p15, 0, r0, c7, c10, 4 @ DWB/DSB \n\t"
203 "mcr p15, 0, r0, c7, c0, 4 @ WFI \n\t");
208 //----------------------------------------------------------------
209 IMPLEMENTATION[arm && (arm1176 || mpcore)]:
211 IMPLEMENT static inline
215 IMPLEMENT static inline
218 Status f = cli_save();
219 asm volatile("mcr p15, 0, r0, c7, c10, 4 @ DWB/DSB \n\t"
224 //----------------------------------------------------------------
225 IMPLEMENTATION[arm && (armca8 || armca9)]:
227 IMPLEMENT static inline
231 IMPLEMENT static inline
234 Status f = cli_save();
235 asm volatile("dsb \n\t"