1 INTERFACE [arm && realview]:
13 Multi_irq_pending = 0,
15 No_irq_pending = 1023,
22 //-------------------------------------------------------------------
23 INTERFACE [arm && realview && (mpcore || armca9)]:
30 INTMODE_NEW_NO_DDC = 1 << 23,
34 //-------------------------------------------------------------------
35 IMPLEMENTATION [arm && !(mpcore || armca9)]:
38 void Pic::configure_core()
42 bool Pic::is_ipi(unsigned)
45 //-------------------------------------------------------------------
46 IMPLEMENTATION [arm && pic_gic]:
52 #include "initcalls.h"
57 //-------------------------------------------------------------------
58 IMPLEMENTATION [arm && pic_gic && realview && (realview_pb11mp || (realview_eb && (mpcore || (armca9 && mp))))]:
64 Gic_pin::_gic[1].init(Kmem::Gic1_cpu_map_base,
65 Kmem::Gic1_dist_map_base);
68 //-------------------------------------------------------------------
69 IMPLEMENTATION [arm && pic_gic && realview && realview_pbx]:
75 Gic_pin::_gic[1].init(Kmem::Gic2_cpu_map_base,
76 Kmem::Gic2_dist_map_base);
79 //-------------------------------------------------------------------
80 IMPLEMENTATION [arm && pic_gic && realview && (realview_pbx || realview_pb11mp || (realview_eb && (mpcore || (armca9 && mp))))]:
82 #include "irq_chip_generic.h"
84 class Irq_chip_arm_rv : public Irq_chip_gen
90 Irq_chip_arm_rv::setup(Irq_base *irq, unsigned irqnum)
93 irq->pin()->replace<Gic_pin>(0, irqnum);
95 irq->pin()->replace<Gic_pin>(1, irqnum - 32);
100 Pic::init_other_gics()
104 static Gic_cascade_irq casc_irq(&Gic_pin::_gic[1], 32);
106 Irq_chip::hw_chip->alloc(&casc_irq, 42);
108 casc_irq.pin()->replace<Gic_cascade_pin>(0, 42);
109 casc_irq.pin()->unmask();
112 //-------------------------------------------------------------------
113 IMPLEMENTATION [arm && pic_gic && !(realview && (realview_pbx || realview_pb11mp || (realview_eb && (mpcore || (armca9 && mp)))))]:
115 #include "irq_chip_generic.h"
117 class Irq_chip_arm_rv : public Irq_chip_gen
123 Irq_chip_arm_rv::setup(Irq_base *irq, unsigned irqnum)
126 irq->pin()->replace<Gic_pin>(0, irqnum);
129 PRIVATE static inline
131 Pic::init_other_gics()
134 //-------------------------------------------------------------------
135 IMPLEMENTATION [arm && pic_gic]:
137 IMPLEMENT FIASCO_INIT
142 static Irq_chip_arm_rv _ia;
143 Irq_chip::hw_chip = &_ia;
145 Gic_pin::_gic[0].init(Kmem::Gic_cpu_map_base, Kmem::Gic_dist_map_base);
151 Pic::Status Pic::disable_all_save()
155 void Pic::restore_all( Status /*s*/ )
159 Unsigned32 Pic::pending()
161 return Gic_pin::_gic[0].pending();
165 Mword Pic::is_pending(Mword &irqs, Mword irq)
166 { return irqs == irq; }
168 //-------------------------------------------------------------------
169 IMPLEMENTATION [arm && mp && pic_gic]:
174 Gic_pin::_gic[0].init_ap();
175 Gic_pin::_gic[1].init_ap();
178 //-------------------------------------------------------------------
179 IMPLEMENTATION [arm && pic_gic && (mpcore || armca9)]:
183 #include "platform.h"
186 void Pic::unlock_config()
187 { Io::write<Mword>(0xa05f, Platform::Sys::Lock); }
190 void Pic::lock_config()
191 { Io::write<Mword>(0x0, Platform::Sys::Lock); }
194 void Pic::configure_core()
196 // Enable 'new' interrupt-mode, no DCC
198 Io::write<Mword>(Io::read<Mword>(Platform::Sys::Pld_ctrl1) | INTMODE_NEW_NO_DDC,
199 Platform::Sys::Pld_ctrl1);