kernel/fiasco/src/kern/arm/bsp/tegra2/outer_cache-arm-tegra2.cpp

   1 IMPLEMENTATION [arm && tegra2 && outer_cache_l2cxx0]:
   2
   3 IMPLEMENT
   4 Mword
   5 Outer_cache::platform_init(Mword aux_control)
   6 {
   7   Io::write<Mword>(0x331, TAG_RAM_CONTROL);
   8   Io::write<Mword>(0x441, DATA_RAM_CONTROL);
   9
  10   aux_control &= 0x8200c3fe;
  11   aux_control |=   (1 <<  0)  // Full Line of Zero Enable
  12                  | (4 << 17)  // 128kb waysize
  13                  | (1 << 28)  // data prefetch
  14                  | (1 << 29)  // insn prefetch
  15                  | (1 << 30)  // early BRESP enable
  16                  ;
  17   return aux_control;
  18 }