1 // --------------------------------------------------------------------------
2 INTERFACE [arm && mptimer]:
10 static unsigned irq() { return 29; }
13 typedef Mmio_register_block Mp_timer;
17 Timer_load_reg = 0x600 + 0x0,
18 Timer_counter_reg = 0x600 + 0x4,
19 Timer_control_reg = 0x600 + 0x8,
20 Timer_int_stat_reg = 0x600 + 0xc,
24 Timer_control_enable = 1 << 0,
25 Timer_control_reload = 1 << 1,
26 Timer_control_itenable = 1 << 2,
27 Timer_control_prescaler = (Prescaler & 0xff) << 8,
29 Timer_int_stat_event = 1,
33 // --------------------------------------------------------------
34 IMPLEMENTATION [arm && mptimer]:
44 Timer::start_as_counter()
46 static_assert(Scu::Available, "No SCU available in this configuration");
48 Cpu::scu->write<Mword>(Timer_control_prescaler | Timer_control_reload
49 | Timer_control_enable,
53 Cpu::scu->write<Mword>(v, Timer_counter_reg);
61 Mword v = Cpu::scu->read<Mword>(Timer_counter_reg);
62 Cpu::scu->write<Mword>(0, Timer_control_reg);
68 Timer::init(Cpu_number)
73 Cpu::scu->write<Mword>(i, Timer_load_reg);
74 Cpu::scu->write<Mword>(i, Timer_counter_reg);
75 Cpu::scu->write<Mword>(Timer_control_prescaler | Timer_control_reload
76 | Timer_control_enable | Timer_control_itenable,
82 Timer::timer_to_us(Unsigned32 /*cr*/)
87 Timer::us_to_timer(Unsigned64 us)
88 { (void)us; return 0; }
94 Cpu::scu->write<Mword>(Timer_int_stat_event, Timer_int_stat_reg);
99 Timer::update_one_shot(Unsigned64 wakeup)
104 IMPLEMENT inline NEEDS["config.h", "kip.h"]
106 Timer::system_clock()
108 if (Config::Scheduler_one_shot)
110 return Kip::k()->clock;