kernel/fiasco/src/kern/arm/bsp/tegra2/pic-arm-tegra2.cpp

   1 INTERFACE [arm && pic_gic && tegra2]:
   2
   3 #include "gic.h"
   4
   5 //-------------------------------------------------------------------
   6 IMPLEMENTATION [arm && pic_gic && tegra2]:
   7
   8 #include "irq_chip.h"
   9 #include "irq_mgr_multi_chip.h"
  10 #include "gic.h"
  11 #include "kmem.h"
  12
  13 IMPLEMENT FIASCO_INIT
  14 void Pic::init()
  15 {
  16   typedef Irq_mgr_multi_chip<8> M;
  17
  18   M *m = new Boot_object<M>(1);
  19
  20   gic.construct(Kmem::mmio_remap(Mem_layout::Gic_cpu_phys_base),
  21                 Kmem::mmio_remap(Mem_layout::Gic_dist_phys_base));
  22   m->add_chip(0, gic, gic->nr_irqs());
  23
  24   Irq_mgr::mgr = m;
  25 }
  26
  27 IMPLEMENT inline
  28 Pic::Status Pic::disable_all_save()
  29 { return 0; }
  30
  31 IMPLEMENT inline
  32 void Pic::restore_all(Status)
  33 {}
  34
  35 //-------------------------------------------------------------------
  36 IMPLEMENTATION [arm && mp && pic_gic && tegra2]:
  37
  38 PUBLIC static
  39 void Pic::init_ap(Cpu_number)
  40 {
  41   gic->init_ap();
  42 }