kernel/fiasco/src/kern/arm/bsp/realview/mem_layout-arm-realview.cpp

   1 INTERFACE [arm && realview]: // -------------------------------------------
   2
   3 #include "globalconfig.h"
   4
   5 EXTENSION class Mem_layout
   6 {
   7 public:
   8   enum Phys_layout_realview_all : Address {
   9     Flush_area_phys_base = 0xe0000000,
  10   };
  11 };
  12
  13 // ------------------------------------------------------------------------
  14 INTERFACE [arm && realview && (realview_eb || realview_pb11mp || realview_pbx || realview_vexpress_a9)]:
  15
  16 #include "globalconfig.h"
  17
  18 EXTENSION class Mem_layout
  19 {
  20 public:
  21   enum Phys_layout_realview : Address {
  22     Devices0_phys_base    = 0x10000000,
  23     System_regs_phys_base = Devices0_phys_base,
  24     System_ctrl_phys_base = Devices0_phys_base + 0x00001000,
  25     Uart_phys_base        = Devices0_phys_base + 0x00009000,
  26     Timer0_phys_base      = Devices0_phys_base + 0x00011000,
  27     //Timer1_phys_base      = Devices0_phys_base + 0x00011020,
  28     //Timer2_phys_base      = Devices0_phys_base + 0x00012000,
  29     //Timer3_phys_base      = Devices0_phys_base + 0x00012020,
  30   };
  31 };
  32
  33 // ------------------------------------------------------------------------
  34 INTERFACE [arm && realview && realview_eb && !(mpcore || armca9)]:
  35
  36 EXTENSION class Mem_layout
  37 {
  38 public:
  39   enum Phys_layout_realview_single : Address {
  40     Gic_cpu_phys_base    = Devices0_phys_base  + 0x00040000,
  41     Gic_dist_phys_base   = Gic_cpu_phys_base   + 0x00001000,
  42   };
  43 };
  44
  45 // ------------------------------------------------------------------------
  46 INTERFACE [arm && realview && realview_eb && (mpcore || armca9)]:
  47
  48 EXTENSION class Mem_layout
  49 {
  50 public:
  51   enum Phys_layout_realview_mp : Address {
  52     Gic1_cpu_phys_base    = Devices0_phys_base + 0x00040000,
  53     Gic1_dist_phys_base   = Devices0_phys_base + 0x00041000,
  54 #if 0
  55     Gic2_cpu_phys_base    = Devices0_phys_base + 0x00050000,
  56     Gic2_dist_phys_base   = Devices0_phys_base + 0x00051000,
  57     Gic3_cpu_phys_base    = Devices0_phys_base + 0x00060000,
  58     Gic3_dist_phys_base   = Devices0_phys_base + 0x00061000,
  59     Gic4_cpu_phys_base    = Devices0_phys_base + 0x00070000,
  60     Gic4_dist_phys_base   = Devices0_phys_base + 0x00071000,
  61 #endif
  62     Devices1_phys_base   = 0x10100000,
  63
  64     Mp_scu_phys_base      = Devices1_phys_base,
  65     Gic_cpu_phys_base     = Devices1_phys_base + 0x00000100,
  66     Gic_dist_phys_base    = Devices1_phys_base + 0x00001000,
  67     L2cxx0_phys_base      = Devices1_phys_base + 0x00002000,
  68   };
  69 };
  70
  71 // ------------------------------------------------------------------------
  72 INTERFACE [arm && realview && realview_pb11mp]:
  73
  74 EXTENSION class Mem_layout
  75 {
  76 public:
  77   enum Phys_layout_realview_pb11mp : Address {
  78     Devices1_phys_base   = 0x1f000000,
  79     Mp_scu_phys_base      = Devices1_phys_base,
  80     Gic_cpu_phys_base     = Devices1_phys_base + 0x00000100,
  81     Gic_dist_phys_base    = Devices1_phys_base + 0x00001000,
  82     L2cxx0_phys_base      = Devices1_phys_base + 0x00002000,
  83
  84     Devices2_phys_base   = 0x1e000000,
  85     Gic1_cpu_phys_base    = Devices2_phys_base,
  86     Gic1_dist_phys_base   = Devices2_phys_base + 0x00001000,
  87   };
  88 };
  89
  90 // ------------------------------------------------------------------------
  91 INTERFACE [arm && realview && realview_pbx]:
  92
  93 EXTENSION class Mem_layout
  94 {
  95 public:
  96   enum Phys_layout_realview_pbx : Address {
  97     Devices1_phys_base    = 0x1f000000,
  98     Mp_scu_phys_base      = Devices1_phys_base,
  99     Gic_cpu_phys_base     = Devices1_phys_base + 0x00000100,
 100     Gic_dist_phys_base    = Devices1_phys_base + 0x00001000,
 101     L2cxx0_phys_base      = Devices1_phys_base + 0x00002000,
 102
 103     Devices2_phys_base    = 0x1e000000,
 104     Gic2_cpu_phys_base    = Devices2_phys_base + 0x00020000,
 105     Gic2_dist_phys_base   = Devices2_phys_base + 0x00021000,
 106     Gic3_cpu_phys_base    = Devices2_phys_base + 0x00030000,
 107     Gic3_dist_phys_base   = Devices2_phys_base + 0x00031000,
 108   };
 109 };
 110
 111 // ------------------------------------------------------------------------
 112 INTERFACE [arm && realview && realview_vexpress_a9]:
 113
 114 EXTENSION class Mem_layout
 115 {
 116 public:
 117   enum Phys_layout_realview_vexpress_a9 : Address {
 118     Devices1_phys_base   = 0x1e000000,
 119     Mp_scu_phys_base      = Devices1_phys_base,
 120     Gic_cpu_phys_base     = Devices1_phys_base + 0x00000100,
 121     Gic_dist_phys_base    = Devices1_phys_base + 0x00001000,
 122     L2cxx0_phys_base      = Devices1_phys_base + 0x00002000,
 123   };
 124 };
 125
 126 // ------------------------------------------------------------------------
 127 INTERFACE [arm && realview && realview_vexpress_a15]:
 128
 129 EXTENSION class Mem_layout
 130 {
 131 public:
 132   enum Phys_layout_realview_vexpress_a15 {
 133     Devices0_phys_base   = 0x1c000000,
 134     System_regs_phys_base = 0x1c010000,
 135     System_ctrl_phys_base = 0x1c020000,
 136     Uart_phys_base        = 0x1c090000,
 137
 138     Devices1_phys_base   = 0x1c100000,
 139     Timer0_phys_base      = Devices1_phys_base + 0x00010000,
 140     //Timer1_phys_base      = Devices1_phys_base + 0x00010020,
 141     //Timer2_phys_base      = Devices1_phys_base + 0x00020000,
 142     //Timer3_phys_base      = Devices1_phys_base + 0x00020020,
 143
 144     Devices2_phys_base   = 0x2c000000,
 145     Mp_scu_phys_base      = Devices2_phys_base,
 146     Gic_cpu_phys_base     = Devices2_phys_base + 0x00002000,
 147     Gic_dist_phys_base    = Devices2_phys_base + 0x00001000,
 148     L2cxx0_phys_base      = Devices2_phys_base + 0x00003000,
 149   };
 150 };