kernel/fiasco/src/kern/arm/bsp/omap/timer_omap_1mstimer.cpp

   1 INTERFACE [omap3]: // ------------------------------------------------
   2
   3 #include "mmio_register_block.h"
   4
   5 class Timer_omap_1mstimer : private Mmio_register_block
   6 {
   7 private:
   8   enum {
   9     TIDR      = 0x000, // IP revision code
  10     TIOCP_CFG = 0x010, // config
  11     TISTAT    = 0x014, // non-interrupt status
  12     TISR      = 0x018, // pending interrupts
  13     TIER      = 0x01c, // enable/disable of interrupt events
  14     TWER      = 0x020, // wake-up features
  15     TCLR      = 0x024, // optional features
  16     TCRR      = 0x028, // internal counter
  17     TLDR      = 0x02c, // timer load value
  18     TTGR      = 0x030, // trigger reload by writing
  19     TWPS      = 0x034, // write-posted pending
  20     TMAR      = 0x038, // compare value
  21     TCAR1     = 0x03c, // first capture value of the counter
  22     TCAR2     = 0x044, // second capture value of the counter
  23     TPIR      = 0x048, // positive inc, gpt1, 2 and 10 only
  24     TNIR      = 0x04C, // negative inc, gpt1, 2 and 10 only
  25   };
  26 };
  27
  28
  29 IMPLEMENTATION [omap3]: // ------------------------------------------------
  30
  31 #include <cassert>
  32 #include <cstdio>
  33
  34 #include "config.h"
  35 #include "kmem.h"
  36 #include "mem_layout.h"
  37
  38 PRIVATE static
  39 void
  40 Timer_omap_1mstimer::get_timer_values_32khz(unsigned &reload, int &tpir, int &tnir)
  41 {
  42   tpir   = 232000;
  43   tnir   = -768000;
  44   reload = 0xffffffe0;
  45   assert(Config::Scheduler_granularity == 1000); // need to adapt here
  46 }
  47
  48 PUBLIC explicit
  49 Timer_omap_1mstimer::Timer_omap_1mstimer(bool f_32khz)
  50 : Mmio_register_block(Kmem::mmio_remap(Mem_layout::Timer1ms_phys_base))
  51 {
  52   // reset
  53   write<Mword>(1, TIOCP_CFG);
  54   while (!read<Mword>(TISTAT))
  55     ;
  56   // reset done
  57
  58   // overflow mode
  59   write<Mword>(0x2, TIER);
  60   // no wakeup
  61   write<Mword>(0x0, TWER);
  62
  63   // program timer frequency
  64   unsigned val;
  65   int tpir, tnir;
  66   get_timer_values(val, tpir, tnir, f_32khz);
  67
  68   write<Mword>(tpir, TPIR); // gpt1, gpt2 and gpt10 only
  69   write<Mword>(tnir, TNIR); // gpt1, gpt2 and gpt10 only
  70   write<Mword>(val,  TCRR);
  71   write<Mword>(val,  TLDR);
  72
  73   // auto-reload + enable
  74   write<Mword>(1 | 2, TCLR);
  75 }
  76
  77 PUBLIC inline
  78 void
  79 Timer_omap_1mstimer::acknowledge()
  80 {
  81   write<Mword>(2, TISR);
  82 }
  83
  84
  85 IMPLEMENTATION [arm && omap3_am33xx]: // ----------------------------------
  86
  87 PRIVATE static
  88 void
  89 Timer_omap_1mstimer::get_timer_values(unsigned &reload, int &tpir, int &tnir,
  90                                       bool f_32khz)
  91 {
  92   if (f_32khz)
  93     get_timer_values_32khz(reload, tpir, tnir);
  94   else
  95     {
  96       tpir   = 100000;
  97       tnir   = 0;
  98       reload = ~0 - 24 * Config::Scheduler_granularity + 1; // 24 MHz
  99     }
 100 }
 101
 102 IMPLEMENTATION [arm && omap3_35x]: // -------------------------------------
 103
 104 PRIVATE static
 105 void
 106 Timer_omap_1mstimer::get_timer_values(unsigned &reload, int &tpir, int &tnir, bool)
 107 {
 108   get_timer_values_32khz(reload, tpir, tnir);
 109 }
 110
 111
 112